[llvm] [AArch64][GlobalISel] Use integer types in lowerVECTOR_COMPRESS. (PR #215662)
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llvm-commits at lists.llvm.org
Tue Aug 11 13:51:45 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: David Green (davemgreen)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/215662.diff
2 Files Affected:
- (modified) llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (+4-4)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-compress.mir (+95-95)
``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index a6c5a267c87db..f8919bb7dbe4f 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -9720,7 +9720,7 @@ LegalizerHelper::lowerVECTOR_COMPRESS(llvm::MachineInstr &MI) {
MachinePointerInfo ValPtrInfo =
MachinePointerInfo::getUnknownStack(*MI.getMF());
- LLT IdxTy = LLT::scalar(32);
+ LLT IdxTy = LLT::integer(32);
LLT ValTy = VecTy.getElementType();
Align ValAlign = getStackTemporaryAlignment(ValTy);
@@ -9742,7 +9742,7 @@ LegalizerHelper::lowerVECTOR_COMPRESS(llvm::MachineInstr &MI) {
} else if (HasPassthru) {
auto Popcount = MIRBuilder.buildZExt(MaskTy.changeElementSize(32), Mask);
Popcount = MIRBuilder.buildInstr(TargetOpcode::G_VECREDUCE_ADD,
- {LLT::scalar(32)}, {Popcount});
+ {LLT::integer(32)}, {Popcount});
Register LastElmtPtr =
getVectorElementPointer(StackPtr, VecTy, Popcount.getReg(0));
@@ -9762,7 +9762,7 @@ LegalizerHelper::lowerVECTOR_COMPRESS(llvm::MachineInstr &MI) {
LLT MaskITy = MaskTy.getElementType();
auto MaskI = MIRBuilder.buildExtractVectorElement(MaskITy, Mask, Idx);
if (MaskITy.getSizeInBits() > 1)
- MaskI = MIRBuilder.buildTrunc(LLT::scalar(1), MaskI);
+ MaskI = MIRBuilder.buildTrunc(LLT::integer(1), MaskI);
MaskI = MIRBuilder.buildZExt(IdxTy, MaskI);
OutPos = MIRBuilder.buildAdd(IdxTy, OutPos, MaskI);
@@ -9771,7 +9771,7 @@ LegalizerHelper::lowerVECTOR_COMPRESS(llvm::MachineInstr &MI) {
auto EndOfVector =
MIRBuilder.buildConstant(IdxTy, VecTy.getNumElements() - 1);
auto AllLanesSelected = MIRBuilder.buildICmp(
- CmpInst::ICMP_UGT, LLT::scalar(1), OutPos, EndOfVector);
+ CmpInst::ICMP_UGT, LLT::integer(1), OutPos, EndOfVector);
OutPos = MIRBuilder.buildInstr(TargetOpcode::G_UMIN, {IdxTy},
{OutPos, EndOfVector});
ElmtPtr = getVectorElementPointer(StackPtr, VecTy, OutPos.getReg(0));
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-compress.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-compress.mir
index 23eccf67cd811..c1c849cefba9b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-compress.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-compress.mir
@@ -12,48 +12,48 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i16>) = COPY $d1
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C1]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C1]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY2]], [[C2]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C1]](i64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[COPY2]], [[C2]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL]](i64)
; CHECK-NEXT: G_STORE [[EVEC]](i32), [[PTR_ADD]](p0) :: (store (i32))
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(i16) = G_EXTRACT_VECTOR_ELT [[COPY1]](<4 x i16>), [[C1]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC1]](i16)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[C]], [[AND]]
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C4]](s64)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C5]]
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[AND1]](s32)
- ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C2]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL1]](s64)
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(i16) = G_EXTRACT_VECTOR_ELT [[COPY1]](<4 x i16>), [[C1]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC1]](i16)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ANYEXT]], [[C3]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[C]], [[AND]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C4]](i64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[ADD]], [[C5]]
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[AND1]](i32)
+ ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = G_MUL [[SEXT]], [[C2]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL1]](i64)
; CHECK-NEXT: G_STORE [[EVEC2]](i32), [[PTR_ADD1]](p0) :: (store (i32))
- ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(i16) = G_EXTRACT_VECTOR_ELT [[COPY1]](<4 x i16>), [[C4]](s64)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC3]](i16)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C3]]
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND2]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C6]](s64)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C5]]
- ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[AND3]](s32)
- ; CHECK-NEXT: [[MUL2:%[0-9]+]]:_(s64) = G_MUL [[SEXT1]], [[C2]]
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL2]](s64)
+ ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(i16) = G_EXTRACT_VECTOR_ELT [[COPY1]](<4 x i16>), [[C4]](i64)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC3]](i16)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[ANYEXT1]], [[C3]]
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(i32) = G_ADD [[ADD]], [[AND2]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C6]](i64)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[ADD1]], [[C5]]
+ ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(i64) = G_SEXT [[AND3]](i32)
+ ; CHECK-NEXT: [[MUL2:%[0-9]+]]:_(i64) = G_MUL [[SEXT1]], [[C2]]
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL2]](i64)
; CHECK-NEXT: G_STORE [[EVEC4]](i32), [[PTR_ADD2]](p0) :: (store (i32))
- ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(i16) = G_EXTRACT_VECTOR_ELT [[COPY1]](<4 x i16>), [[C6]](s64)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC5]](i16)
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C3]]
- ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND4]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C7]](s64)
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C5]]
- ; CHECK-NEXT: [[SEXT2:%[0-9]+]]:_(s64) = G_SEXT [[AND5]](s32)
- ; CHECK-NEXT: [[MUL3:%[0-9]+]]:_(s64) = G_MUL [[SEXT2]], [[C2]]
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL3]](s64)
+ ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(i16) = G_EXTRACT_VECTOR_ELT [[COPY1]](<4 x i16>), [[C6]](i64)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC5]](i16)
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[ANYEXT2]], [[C3]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(i32) = G_ADD [[ADD1]], [[AND4]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C7]](i64)
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[ADD2]], [[C5]]
+ ; CHECK-NEXT: [[SEXT2:%[0-9]+]]:_(i64) = G_SEXT [[AND5]](i32)
+ ; CHECK-NEXT: [[MUL3:%[0-9]+]]:_(i64) = G_MUL [[SEXT2]], [[C2]]
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL3]](i64)
; CHECK-NEXT: G_STORE [[EVEC6]](i32), [[PTR_ADD3]](p0) :: (store (i32))
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x i32>) = G_LOAD [[FRAME_INDEX]](p0) :: (load (<4 x i32>) from %stack.0)
; CHECK-NEXT: $q0 = COPY [[LOAD]](<4 x i32>)
@@ -79,69 +79,69 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i16>) = COPY $d1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x i32>) = COPY $q2
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: G_STORE [[COPY2]](<4 x i32>), [[FRAME_INDEX]](p0) :: (store (<4 x i32>) into %stack.0)
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<4 x i32>) = G_ZEXT [[COPY1]](<4 x i16>)
- ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[ZEXT]](<4 x i32>)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[VECREDUCE_ADD]], [[C1]]
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[AND]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C2]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL]](s64)
+ ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(i32) = G_VECREDUCE_ADD [[ZEXT]](<4 x i32>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[VECREDUCE_ADD]], [[C1]]
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[AND]](i32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[SEXT]], [[C2]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL]](i64)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p0) :: (load (i32))
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C3]](s64)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C3]](s64)
- ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL [[COPY3]], [[C2]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL1]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C3]](i64)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY [[C3]](i64)
+ ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = G_MUL [[COPY3]], [[C2]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL1]](i64)
; CHECK-NEXT: G_STORE [[EVEC]](i32), [[PTR_ADD1]](p0) :: (store (i32))
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(i16) = G_EXTRACT_VECTOR_ELT [[COPY1]](<4 x i16>), [[C3]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC1]](i16)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[C]], [[AND1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C5]](s64)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C1]]
- ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[AND2]](s32)
- ; CHECK-NEXT: [[MUL2:%[0-9]+]]:_(s64) = G_MUL [[SEXT1]], [[C2]]
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL2]](s64)
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(i16) = G_EXTRACT_VECTOR_ELT [[COPY1]](<4 x i16>), [[C3]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC1]](i16)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[ANYEXT]], [[C4]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[C]], [[AND1]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C5]](i64)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[ADD]], [[C1]]
+ ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(i64) = G_SEXT [[AND2]](i32)
+ ; CHECK-NEXT: [[MUL2:%[0-9]+]]:_(i64) = G_MUL [[SEXT1]], [[C2]]
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL2]](i64)
; CHECK-NEXT: G_STORE [[EVEC2]](i32), [[PTR_ADD2]](p0) :: (store (i32))
- ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(i16) = G_EXTRACT_VECTOR_ELT [[COPY1]](<4 x i16>), [[C5]](s64)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC3]](i16)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C4]]
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND3]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C6]](s64)
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C1]]
- ; CHECK-NEXT: [[SEXT2:%[0-9]+]]:_(s64) = G_SEXT [[AND4]](s32)
- ; CHECK-NEXT: [[MUL3:%[0-9]+]]:_(s64) = G_MUL [[SEXT2]], [[C2]]
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL3]](s64)
+ ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(i16) = G_EXTRACT_VECTOR_ELT [[COPY1]](<4 x i16>), [[C5]](i64)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC3]](i16)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[ANYEXT1]], [[C4]]
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(i32) = G_ADD [[ADD]], [[AND3]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C6]](i64)
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[ADD1]], [[C1]]
+ ; CHECK-NEXT: [[SEXT2:%[0-9]+]]:_(i64) = G_SEXT [[AND4]](i32)
+ ; CHECK-NEXT: [[MUL3:%[0-9]+]]:_(i64) = G_MUL [[SEXT2]], [[C2]]
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL3]](i64)
; CHECK-NEXT: G_STORE [[EVEC4]](i32), [[PTR_ADD3]](p0) :: (store (i32))
- ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(i16) = G_EXTRACT_VECTOR_ELT [[COPY1]](<4 x i16>), [[C6]](s64)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC5]](i16)
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C4]]
- ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND5]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C7]](s64)
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C1]]
- ; CHECK-NEXT: [[SEXT3:%[0-9]+]]:_(s64) = G_SEXT [[AND6]](s32)
- ; CHECK-NEXT: [[MUL4:%[0-9]+]]:_(s64) = G_MUL [[SEXT3]], [[C2]]
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL4]](s64)
+ ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(i16) = G_EXTRACT_VECTOR_ELT [[COPY1]](<4 x i16>), [[C6]](i64)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC5]](i16)
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[ANYEXT2]], [[C4]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(i32) = G_ADD [[ADD1]], [[AND5]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C7]](i64)
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[ADD2]], [[C1]]
+ ; CHECK-NEXT: [[SEXT3:%[0-9]+]]:_(i64) = G_SEXT [[AND6]](i32)
+ ; CHECK-NEXT: [[MUL4:%[0-9]+]]:_(i64) = G_MUL [[SEXT3]], [[C2]]
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL4]](i64)
; CHECK-NEXT: G_STORE [[EVEC6]](i32), [[PTR_ADD4]](p0) :: (store (i32))
- ; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(i16) = G_EXTRACT_VECTOR_ELT [[COPY1]](<4 x i16>), [[C7]](s64)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC7]](i16)
- ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C4]]
- ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[AND7]]
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ADD3]](s32), [[C1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[ADD3]](s32), [[C1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](i32), [[ADD3]], [[C1]]
- ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C1]]
- ; CHECK-NEXT: [[SEXT4:%[0-9]+]]:_(s64) = G_SEXT [[AND8]](s32)
- ; CHECK-NEXT: [[MUL5:%[0-9]+]]:_(s64) = G_MUL [[SEXT4]], [[C2]]
- ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL5]](s64)
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(i32) = G_SELECT [[ICMP]](s32), [[EVEC6]], [[LOAD]]
+ ; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(i16) = G_EXTRACT_VECTOR_ELT [[COPY1]](<4 x i16>), [[C7]](i64)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC7]](i16)
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(i32) = G_AND [[ANYEXT3]], [[C4]]
+ ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(i32) = G_ADD [[ADD2]], [[AND7]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ugt), [[ADD3]](i32), [[C1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[ADD3]](i32), [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i32) = G_SELECT [[ICMP1]](i32), [[ADD3]], [[C1]]
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(i32) = G_AND [[SELECT]], [[C1]]
+ ; CHECK-NEXT: [[SEXT4:%[0-9]+]]:_(i64) = G_SEXT [[AND8]](i32)
+ ; CHECK-NEXT: [[MUL5:%[0-9]+]]:_(i64) = G_MUL [[SEXT4]], [[C2]]
+ ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[MUL5]](i64)
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(i32) = G_SELECT [[ICMP]](i32), [[EVEC6]], [[LOAD]]
; CHECK-NEXT: G_STORE [[SELECT1]](i32), [[PTR_ADD5]](p0) :: (store (i32))
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x i32>) = G_LOAD [[FRAME_INDEX]](p0) :: (load (<4 x i32>) from %stack.0)
; CHECK-NEXT: $q0 = COPY [[LOAD1]](<4 x i32>)
``````````
</details>
https://github.com/llvm/llvm-project/pull/215662
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