[llvm] [GlobalISel][AArch64][AMDGPU] Don't narrow saturating fp-to-int conversions (PR #215567)
Nathaniel McCallum via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 11 06:45:25 PDT 2026
https://github.com/npmccallum created https://github.com/llvm/llvm-project/pull/215567
A saturating float-to-int conversion clamps to the bounds of its **result**
type. Narrowing one to a legal integer width therefore saturates to the wrong
bounds, however small the range of the source is. Both AArch64 and AMDGPU did
that, producing wrong code with no diagnostic, because the generic legalizer
helper offered the transformation without any check and got the signedness wrong
as well.
## The generic problem
`LegalizerHelper::narrowScalar` dispatched `G_FPTOSI_SAT`/`G_FPTOUI_SAT` to
`narrowScalarFPTOI` alongside their non-saturating counterparts. That helper
converts at the narrower width and extends, which is sound only for the plain
opcodes, where out-of-range results are poison. It also derived signedness with
```cpp
bool IsSigned = MI.getOpcode() == TargetOpcode::G_FPTOSI;
```
false for `G_FPTOSI_SAT`, so a signed saturating result was zero-extended rather
than sign-extended — turning every negative result into a large positive one.
## AArch64
The legalizer narrowed any result wider than 64 bits to `i64` when the source
was a 16-bit float, reasoning that the range of an `f16` fits in an `i17`:
| call | produced | expected |
|---|---|---|
| `fptosi.sat.i128.f16(-1.0)` | `0x0..0FFFFFFFFFFFFFFFF` | `-1` |
| `fptosi.sat.i128.f16(inf)` | largest `i64` | largest `i128` |
| `fptosi.sat.i128.f16(-inf)` | `0x0..08000000000000000` | smallest `i128` |
| `fptoui.sat.i128.f16(inf)` | largest `u64` | largest `u128` |
Present since the opcodes were added in feac761f3797. AArch64 selects GlobalISel
at `-O0`, so that is where it is most readily seen, but the defect is in the
selector rather than in any optimization level.
## AMDGPU
Two independent places, both assuming a narrower width is interchangeable:
- the legalizer narrowed `{i64, f16}` to `i32` and zero-filled the upper half,
so `fptosi.sat.i64.f16(-1.0)` gave `0x00000000FFFFFFFF` and `(inf)` gave the
largest `i32`;
- `LowerFP_TO_INT_SAT` built a node with an `i64` result but an `i32` saturation
width. That form is legal — integer type legalization relies on it — but it
saturates to `i32` bounds and extends, which is a different operation. For
`bfloat` this is not confined to infinities: `bfloat` carries the exponent
range of `f32`, so ordinary finite values that fit in an `i64` were clamped to
the largest `i32`.
Introduced in 447f1e43bb9a. That commit is in the llvmorg-23.1.0-rc1 and rc2
tags but has not appeared in a final release.
## Structure
Seven commits: three baseline test commits and four fixes. Each newly added test
is committed first with the current, wrong result and a FIXME, per the precommit
workflow in `TestingGuide.md`. No fix commit introduces a test — each one only
changes expectations that already exist. The AMDGPU GlobalISel fix has no
baseline commit of its own: it is covered by the pre-existing scalar and vector
sat tests, and the new bfloat cases cannot cover it because
`bf16-conversions.ll` has no GlobalISel RUN lines.
```
[AMDGPU] Add saturating bfloat to i64 conversion tests (NFC)
[AMDGPU] Don't narrow saturating fp-to-int conversions in the legalizer
[AMDGPU] Fix saturation width in LowerFP_TO_INT_SAT
[AArch64][GlobalISel] Add saturating f16 to 128-bit legalizer test (NFC)
[AArch64][GlobalISel] Fix saturating f16 to 128-bit conversions
[GlobalISel] Add narrowScalar test for saturating fp-to-int (NFC)
[GlobalISel] Don't narrow saturating fp-to-int conversions
```
The generic commit comes last because it must: with either target rule still
present it breaks that target — AArch64 falls back to SelectionDAG and its
`CHECK-GI` lines stop matching, AMDGPU fails to legalize outright. Every commit
builds and passes on its own.
## Notes for reviewers
**On the size of the test diffs.** They are large but narrow. In
`AMDGPU/fptosi-sat-vector.ll`, 4 of 59 functions change and every added line
is a `CHECK` line. Three multipliers stack in those four: the miscompiled
sequence was about three instructions because it skipped the bounds checks,
and a correct 128-bit saturating conversion needs the convert plus three
comparisons — low bound, high bound, and unordered for NaN — with a select
per 32-bit half; the vector cases scalarize into eight independent
conversions; and the file has eight RUN lines, so each emitted instruction is
recorded eight times. The growth is confined to the `v8f16 -> v8i64` and
`v4f16 -> v4i64` shapes.
**The refusal is covered by a unit test**, not by a lit test: after the target
fixes no target requests the narrowing, so nothing in codegen reaches it.
`LegalizerHelperTest.cpp` calls `narrowScalar` on `G_FPTOSI_SAT`/`G_FPTOUI_SAT`
directly; the preceding commit records that it currently returns `Legalized`,
and the fix flips both assertions to `UnableToLegalize`. The legalizer lit test
that pins the lowered form is in the AArch64 commit, where it changes behaviour.
**Removing a legalization action** would break a target whose rule set has no
`lower` fallback. No in-tree target is affected: AArch64 has `.lowerIf`, AMDGPU
has `.lower()`.
**The near-identical rule on the non-saturating builders is left in place** and
is correct: every finite `f16` fits in an `i17`, out-of-range results are poison
for the plain opcodes, and the helper extends those correctly.
**bfloat is affected on AMDGPU but not AArch64.** Verified against the unfixed
compiler; AArch64 lowers `bfloat` correctly already.
## Testing
`check-llvm` is clean across all targets. Each commit was checked out, built and
run against the AArch64 and AMDGPU suites individually.
Separately, all 65536 `f16` and all 65536 `bfloat` bit patterns were converted
to `i64`, `u64`, `i128` and `u128` under both GlobalISel and SelectionDAG,
executed natively on aarch64, and compared against a reference computed in
exact rational arithmetic: 1,048,576 conversions, no mismatches.
Every fix here works by removing a target special case so that the generic
expansion runs, and that expansion is what the sweep above exercises. What is
left untested by execution is therefore each target's instruction selection of
the generic nodes, not the saturation logic itself.
I have no AMD hardware, so nothing in this series was executed on an AMDGPU
target; its evidence is `check-llvm` plus legalized MIR carrying the same
smallest/largest `i64` clamps and unordered-NaN compare as the AArch64 lowering
that was executed. If a reviewer can run the AMDGPU cases on hardware, I would
welcome the confirmation.
## AI disclosure
Per the LLVM AI Tool Use Policy: this change was developed with AI assistance.
An AI agent performed the investigation, wrote the patches and test updates, and
ran the validation described above; a second AI agent reviewed the series
against the project's conventions, and its findings were incorporated. All of
it was directed and reviewed by me, and I am responsible for the content.
>From ded1e043929c30eb482dba0d5db220be7c5d3e98 Mon Sep 17 00:00:00 2001
From: Nathaniel McCallum <nathaniel at mccallum.life>
Date: Sun, 9 Aug 2026 13:23:24 -0400
Subject: [PATCH 1/7] [AMDGPU] Add saturating bfloat to i64 conversion tests
(NFC)
The results recorded here are incorrect: the conversion is performed at i32 and
then extended, so a finite bfloat that fits in an i64 but not an i32
saturates to the largest i32 instead of converting exactly. bfloat has the
exponent range of f32, so this is reachable with ordinary values rather than
only at the infinities.
---
llvm/test/CodeGen/AMDGPU/bf16-conversions.ll | 46 ++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
index 4dd33065e20c1..d90541243c26e 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
@@ -673,6 +673,52 @@ entry:
ret void
}
+; FIXME: These record incorrect results. The conversion is performed at i32 and
+; then extended, so a finite bfloat that fits in an i64 but not an i32 saturates
+; to i32::MAX rather than converting exactly.
+define i64 @v_test_bf16_to_i64_sat(bfloat %x) {
+; GCN-LABEL: v_test_bf16_to_i64_sat:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GCN-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: v_test_bf16_to_i64_sat:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX1250-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+ %r = call i64 @llvm.fptosi.sat.i64.bf16(bfloat %x)
+ ret i64 %r
+}
+
+define i64 @v_test_bf16_to_u64_sat(bfloat %x) {
+; GCN-LABEL: v_test_bf16_to_u64_sat:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: v_test_bf16_to_u64_sat:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+ %r = call i64 @llvm.fptoui.sat.i64.bf16(bfloat %x)
+ ret i64 %r
+}
+
declare float @llvm.fabs.f32(float)
declare double @llvm.fabs.f64(double)
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
>From 94e23e854238d97864c413890a594b0beb471bc7 Mon Sep 17 00:00:00 2001
From: Nathaniel McCallum <nathaniel at mccallum.life>
Date: Sun, 9 Aug 2026 13:24:52 -0400
Subject: [PATCH 2/7] [AMDGPU] Don't narrow saturating fp-to-int conversions in
the legalizer
The legalizer narrowed the result of G_FPTOSI_SAT/G_FPTOUI_SAT to i32 when the
source was a 16-bit float, on the grounds that such a source cannot exceed the
range of an i32. That holds for finite values, but a saturating conversion
clamps to the bounds of its result type, so narrowing saturates to the wrong
ones. The narrowed value was also zero-extended rather than sign-extended,
because the generic helper derives signedness from G_FPTOSI alone:
fptosi.sat.i64.f16(-1.0) gave 0x00000000FFFFFFFF, expected -1
fptosi.sat.i64.f16(inf) gave the largest i32, expected the largest i64
Drop the rule and let these lower. The lowering expands the saturation at the
result width and narrows the non-saturating conversion inside it, so the
narrowing is still performed where it is valid.
The equivalent rule on the non-saturating G_FPTOSI/G_FPTOUI builder is correct
and is left alone: out-of-range results are poison there.
---
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 3 +-
llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll | 126 +-
llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll | 1377 +++++++++++++++--
llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll | 145 +-
llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll | 857 ++++++++--
5 files changed, 2182 insertions(+), 326 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 513a6487b39a2..01a90205197c9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1258,8 +1258,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
auto &FPToISat = getActionDefinitionsBuilder({G_FPTOSI_SAT, G_FPTOUI_SAT})
.legalFor({{I32, F32}, {I32, F64}, {I16, F32}})
.legalFor(ST.has16BitInsts(), {{I16, F16}})
- .legalFor(ST.hasVCvtPkIU16F32(), {{V2I16, V2F32}})
- .narrowScalarFor({{I64, F16}}, changeElementSizeTo(0, I32));
+ .legalFor(ST.hasVCvtPkIU16F32(), {{V2I16, V2F32}});
// If available, widen width <16 to i16, intead of i32 so v_cvt_i16/u16_f16 can be used.
if (ST.has16BitInsts())
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
index 66b2ba892182a..3be429ea7dadc 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
@@ -1957,8 +1957,32 @@ define i64 @test_signed_i64_f16(half %f) nounwind {
; GFX7-GI: ; %bb.0:
; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0x2f800000
+; GFX7-GI-NEXT: v_mov_b32_e32 v2, 0xcf800000
+; GFX7-GI-NEXT: v_bfrev_b32_e32 v4, 1
+; GFX7-GI-NEXT: v_trunc_f32_e32 v3, v0
+; GFX7-GI-NEXT: v_mul_f32_e64 v1, |v3|, v1
+; GFX7-GI-NEXT: v_floor_f32_e32 v1, v1
+; GFX7-GI-NEXT: v_fma_f32 v2, v1, v2, |v3|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX7-GI-NEXT: v_ashrrev_i32_e32 v3, 31, v0
+; GFX7-GI-NEXT: v_xor_b32_e32 v2, v2, v3
+; GFX7-GI-NEXT: v_xor_b32_e32 v1, v1, v3
+; GFX7-GI-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
+; GFX7-GI-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
+; GFX7-GI-NEXT: v_mov_b32_e32 v3, 0xdf000000
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v3
+; GFX7-GI-NEXT: v_mov_b32_e32 v3, 0x5effffff
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX7-GI-NEXT: v_bfrev_b32_e32 v4, -2
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v0, v3
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_i64_f16:
@@ -2017,8 +2041,30 @@ define i64 @test_signed_i64_f16(half %f) nounwind {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX12-GI-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-GI-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX12-GI-NEXT: v_trunc_f32_e32 v1, v0
+; GFX12-GI-NEXT: v_ashrrev_i32_e32 v3, 31, v0
+; GFX12-GI-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX12-GI-NEXT: v_floor_f32_e32 v2, v2
+; GFX12-GI-NEXT: v_fma_f32 v1, 0xcf800000, v2, |v1|
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-GI-NEXT: v_xor_b32_e32 v2, v2, v3
+; GFX12-GI-NEXT: v_xor_b32_e32 v1, v1, v3
+; GFX12-GI-NEXT: v_sub_co_u32 v1, vcc_lo, v1, v3
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_sub_co_ci_u32_e64 v2, null, v2, v3, vcc_lo
+; GFX12-GI-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0x80000000, vcc_lo
+; GFX12-GI-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v0
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0x7fffffff, vcc_lo
+; GFX12-GI-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc_lo
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i64 @llvm.fptosi.sat.i64.f16(half %f)
ret i64 %x
@@ -2340,8 +2386,39 @@ define i64 @test_s_signed_i64_f16(half inreg %f) nounwind {
; GFX7-GI: ; %bb.0:
; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v0, s16
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0x2f800000
+; GFX7-GI-NEXT: v_mov_b32_e32 v2, 0xcf800000
+; GFX7-GI-NEXT: v_trunc_f32_e32 v3, v0
+; GFX7-GI-NEXT: v_mul_f32_e64 v1, |v3|, v1
+; GFX7-GI-NEXT: v_floor_f32_e32 v1, v1
+; GFX7-GI-NEXT: v_fma_f32 v2, v1, v2, |v3|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX7-GI-NEXT: v_readfirstlane_b32 s4, v0
+; GFX7-GI-NEXT: s_ashr_i32 s4, s4, 31
+; GFX7-GI-NEXT: v_readfirstlane_b32 s7, v1
+; GFX7-GI-NEXT: v_readfirstlane_b32 s6, v2
+; GFX7-GI-NEXT: s_mov_b32 s5, s4
+; GFX7-GI-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]
+; GFX7-GI-NEXT: s_sub_u32 s6, s6, s4
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0xdf000000
+; GFX7-GI-NEXT: s_subb_u32 s7, s7, s4
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1
+; GFX7-GI-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0x5effffff
+; GFX7-GI-NEXT: s_mov_b32 s4, 0
+; GFX7-GI-NEXT: s_brev_b32 s5, 1
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v0, v1
+; GFX7-GI-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7]
+; GFX7-GI-NEXT: s_or_b64 s[6:7], vcc, vcc
+; GFX7-GI-NEXT: s_mov_b32 s6, -1
+; GFX7-GI-NEXT: s_brev_b32 s7, -2
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; GFX7-GI-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]
+; GFX7-GI-NEXT: s_or_b64 s[6:7], vcc, vcc
+; GFX7-GI-NEXT: s_cselect_b64 s[4:5], 0, s[4:5]
+; GFX7-GI-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, s5
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_i64_f16:
@@ -2383,12 +2460,41 @@ define i64 @test_s_signed_i64_f16(half inreg %f) nounwind {
; GFX12-GI-NEXT: s_wait_samplecnt 0x0
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
-; GFX12-GI-NEXT: s_cvt_f32_f16 s0, s0
-; GFX12-GI-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-GI-NEXT: s_cvt_f32_f16 s6, s0
+; GFX12-GI-NEXT: s_mov_b32 s4, 0
+; GFX12-GI-NEXT: s_brev_b32 s5, 1
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: s_cvt_i32_f32 s0, s0
+; GFX12-GI-NEXT: s_trunc_f32 s0, s6
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-GI-NEXT: s_and_b32 s1, s0, 0x7fffffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_mul_f32 s0, s1, 0x2f800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s2, s0
+; GFX12-GI-NEXT: s_ashr_i32 s0, s6, 31
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s1, s2, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s3, s2
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s2, s1
+; GFX12-GI-NEXT: s_mov_b32 s1, s0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s6, 0xdf000000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_sub_nc_u64 s[0:1], s[2:3], s[0:1]
+; GFX12-GI-NEXT: s_mov_b32 s2, -1
+; GFX12-GI-NEXT: s_brev_b32 s3, -2
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[0:1], s[4:5], s[0:1]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s6, 0x5effffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
+; GFX12-GI-NEXT: s_cmp_u_f32 s6, s6
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i64 @llvm.fptosi.sat.i64.f16(half %f)
ret i64 %x
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
index 78ee5f7356e37..23afc452b40c6 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
@@ -3146,20 +3146,99 @@ define <4 x i64> @test_signed_v4f16_v4i64(<4 x half> %f) {
; GFX7-GI-LABEL: test_signed_v4f16_v4i64:
; GFX7-GI: ; %bb.0:
; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX7-GI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0x2f800000
+; GFX7-GI-NEXT: v_mov_b32_e32 v6, 0xcf800000
+; GFX7-GI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX7-GI-NEXT: v_trunc_f32_e32 v3, v2
+; GFX7-GI-NEXT: v_mul_f32_e64 v4, |v3|, v5
+; GFX7-GI-NEXT: v_floor_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_fma_f32 v3, v4, v6, |v3|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_ashrrev_i32_e32 v8, 31, v2
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v13, v0
+; GFX7-GI-NEXT: v_xor_b32_e32 v3, v3, v8
+; GFX7-GI-NEXT: v_xor_b32_e32 v4, v4, v8
+; GFX7-GI-NEXT: v_sub_i32_e32 v3, vcc, v3, v8
+; GFX7-GI-NEXT: v_subb_u32_e32 v4, vcc, v4, v8, vcc
+; GFX7-GI-NEXT: v_mov_b32_e32 v9, 0xdf000000
+; GFX7-GI-NEXT: v_bfrev_b32_e32 v10, 1
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v2, v9
+; GFX7-GI-NEXT: v_mov_b32_e32 v11, 0x5effffff
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
+; GFX7-GI-NEXT: v_bfrev_b32_e32 v12, -2
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v2, v11
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v3, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; GFX7-GI-NEXT: v_trunc_f32_e32 v2, v13
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v3, 0, vcc
+; GFX7-GI-NEXT: v_mul_f32_e64 v3, |v2|, v5
+; GFX7-GI-NEXT: v_floor_f32_e32 v3, v3
+; GFX7-GI-NEXT: v_fma_f32 v2, v3, v6, |v2|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v8, v4, 0, vcc
+; GFX7-GI-NEXT: v_ashrrev_i32_e32 v4, 31, v13
+; GFX7-GI-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX7-GI-NEXT: v_xor_b32_e32 v2, v2, v4
; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v6, v3
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v3, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v7, 0
+; GFX7-GI-NEXT: v_xor_b32_e32 v3, v3, v4
+; GFX7-GI-NEXT: v_sub_i32_e32 v2, vcc, v2, v4
+; GFX7-GI-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v13, v9
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v13, v11
+; GFX7-GI-NEXT: v_trunc_f32_e32 v4, v1
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v3, v3, v12, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
+; GFX7-GI-NEXT: v_mul_f32_e64 v13, |v4|, v5
+; GFX7-GI-NEXT: v_floor_f32_e32 v13, v13
+; GFX7-GI-NEXT: v_fma_f32 v4, v13, v6, |v4|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v13, v13
+; GFX7-GI-NEXT: v_ashrrev_i32_e32 v14, 31, v1
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-GI-NEXT: v_xor_b32_e32 v4, v4, v14
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX7-GI-NEXT: v_xor_b32_e32 v13, v13, v14
+; GFX7-GI-NEXT: v_sub_i32_e32 v4, vcc, v4, v14
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; GFX7-GI-NEXT: v_subb_u32_e32 v13, vcc, v13, v14, vcc
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v1, v9
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v13, v13, v10, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v1, v11
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v4, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v13, v13, v12, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; GFX7-GI-NEXT: v_trunc_f32_e32 v1, v7
+; GFX7-GI-NEXT: v_mul_f32_e64 v5, |v1|, v5
+; GFX7-GI-NEXT: v_floor_f32_e32 v5, v5
+; GFX7-GI-NEXT: v_fma_f32 v1, v5, v6, |v1|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v6, v5
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v5, v13, 0, vcc
+; GFX7-GI-NEXT: v_ashrrev_i32_e32 v13, 31, v7
+; GFX7-GI-NEXT: v_xor_b32_e32 v1, v1, v13
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX7-GI-NEXT: v_xor_b32_e32 v6, v6, v13
+; GFX7-GI-NEXT: v_sub_i32_e32 v1, vcc, v1, v13
+; GFX7-GI-NEXT: v_subb_u32_e32 v6, vcc, v6, v13, vcc
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v7, v9
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v7, v11
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v9, v6, v12, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v6, v1, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v7, v9, 0, vcc
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, v8
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_v4f16_v4i64:
@@ -3273,15 +3352,100 @@ define <4 x i64> @test_signed_v4f16_v4i64(<4 x half> %f) {
; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v2, v0.l
; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v3, v0.h
; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v4, v1.l
-; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v1, v1.h
-; GFX12-GI-NEXT: v_mov_b32_e32 v5, 0
-; GFX12-GI-NEXT: v_cvt_i32_f32_e32 v0, v2
-; GFX12-GI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; GFX12-GI-NEXT: v_cvt_i32_f32_e32 v4, v4
-; GFX12-GI-NEXT: v_cvt_i32_f32_e32 v6, v1
-; GFX12-GI-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-GI-NEXT: v_mov_b32_e32 v3, 0
-; GFX12-GI-NEXT: v_mov_b32_e32 v7, 0
+; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v6, v1.h
+; GFX12-GI-NEXT: v_trunc_f32_e32 v0, v2
+; GFX12-GI-NEXT: v_trunc_f32_e32 v5, v3
+; GFX12-GI-NEXT: v_ashrrev_i32_e32 v7, 31, v2
+; GFX12-GI-NEXT: v_trunc_f32_e32 v8, v4
+; GFX12-GI-NEXT: v_ashrrev_i32_e32 v11, 31, v3
+; GFX12-GI-NEXT: v_mul_f32_e64 v1, 0x2f800000, |v0|
+; GFX12-GI-NEXT: v_mul_f32_e64 v9, 0x2f800000, |v5|
+; GFX12-GI-NEXT: v_trunc_f32_e32 v10, v6
+; GFX12-GI-NEXT: v_mul_f32_e64 v12, 0x2f800000, |v8|
+; GFX12-GI-NEXT: v_ashrrev_i32_e32 v14, 31, v4
+; GFX12-GI-NEXT: v_floor_f32_e32 v1, v1
+; GFX12-GI-NEXT: v_floor_f32_e32 v9, v9
+; GFX12-GI-NEXT: v_mul_f32_e64 v13, 0x2f800000, |v10|
+; GFX12-GI-NEXT: v_floor_f32_e32 v12, v12
+; GFX12-GI-NEXT: v_fma_f32 v0, 0xcf800000, v1, |v0|
+; GFX12-GI-NEXT: v_fma_f32 v5, 0xcf800000, v9, |v5|
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v9, v9
+; GFX12-GI-NEXT: v_floor_f32_e32 v13, v13
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX12-GI-NEXT: v_xor_b32_e32 v1, v1, v7
+; GFX12-GI-NEXT: v_xor_b32_e32 v9, v9, v11
+; GFX12-GI-NEXT: v_fma_f32 v8, 0xcf800000, v12, |v8|
+; GFX12-GI-NEXT: v_xor_b32_e32 v0, v0, v7
+; GFX12-GI-NEXT: v_xor_b32_e32 v5, v5, v11
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX12-GI-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v7
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v7, vcc_lo
+; GFX12-GI-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v2
+; GFX12-GI-NEXT: v_sub_co_u32 v5, s0, v5, v11
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_sub_co_ci_u32_e64 v7, null, v9, v11, s0
+; GFX12-GI-NEXT: v_cmp_nle_f32_e64 s0, 0xdf000000, v3
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0x80000000, vcc_lo
+; GFX12-GI-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v2
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v9, v12
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v5, 0, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v7, v7, 0x80000000, s0
+; GFX12-GI-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v3
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fffffff, vcc_lo
+; GFX12-GI-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX12-GI-NEXT: v_fma_f32 v2, 0xcf800000, v13, |v10|
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v5, -1, s0
+; GFX12-GI-NEXT: v_ashrrev_i32_e32 v10, 31, v6
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v7, v7, 0x7fffffff, s0
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v11, v2
+; GFX12-GI-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX12-GI-NEXT: v_xor_b32_e32 v3, v8, v14
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v8, v13
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v5, 0, vcc_lo
+; GFX12-GI-NEXT: v_xor_b32_e32 v5, v9, v14
+; GFX12-GI-NEXT: v_xor_b32_e32 v9, v11, v10
+; GFX12-GI-NEXT: v_xor_b32_e32 v8, v8, v10
+; GFX12-GI-NEXT: v_sub_co_u32 v3, s0, v3, v14
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_sub_co_ci_u32_e64 v5, null, v5, v14, s0
+; GFX12-GI-NEXT: v_sub_co_u32 v9, s1, v9, v10
+; GFX12-GI-NEXT: v_cmp_nle_f32_e64 s0, 0xdf000000, v4
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_sub_co_ci_u32_e64 v8, null, v8, v10, s1
+; GFX12-GI-NEXT: v_cmp_nle_f32_e64 s1, 0xdf000000, v6
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v3, 0, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v5, 0x80000000, s0
+; GFX12-GI-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v4
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v9, v9, 0, s1
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v8, v8, 0x80000000, s1
+; GFX12-GI-NEXT: v_cmp_lt_f32_e64 s1, 0x5effffff, v6
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v10, v3, -1, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v5, 0x7fffffff, s0
+; GFX12-GI-NEXT: v_cmp_u_f32_e64 s0, v4, v4
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v9, v9, -1, s1
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v8, v8, 0x7fffffff, s1
+; GFX12-GI-NEXT: v_cmp_u_f32_e64 s1, v6, v6
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v7, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v4, v10, 0, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v5, 0, s0
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v6, v9, 0, s1
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v7, v8, 0, s1
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <4 x i64> @llvm.fptosi.sat.v4f16.v4i64(<4 x half> %f)
ret <4 x i64> %x
@@ -3954,20 +4118,120 @@ define <4 x i64> @test_s_signed_v4f16_v4i64(<4 x half> inreg %f) {
; GFX7-GI-LABEL: test_s_signed_v4f16_v4i64:
; GFX7-GI: ; %bb.0:
; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GI-NEXT: s_lshr_b32 s4, s16, 16
-; GFX7-GI-NEXT: s_lshr_b32 s5, s17, 16
; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v0, s16
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v1, s4
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v3, s17
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v5, s5
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v2, v1
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v4, v3
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v6, v5
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v3, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v7, 0
+; GFX7-GI-NEXT: v_mov_b32_e32 v2, 0x2f800000
+; GFX7-GI-NEXT: v_mov_b32_e32 v4, 0xcf800000
+; GFX7-GI-NEXT: s_lshr_b32 s10, s16, 16
+; GFX7-GI-NEXT: v_trunc_f32_e32 v1, v0
+; GFX7-GI-NEXT: v_mul_f32_e64 v3, |v1|, v2
+; GFX7-GI-NEXT: v_floor_f32_e32 v3, v3
+; GFX7-GI-NEXT: v_fma_f32 v1, v3, v4, |v1|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX7-GI-NEXT: v_readfirstlane_b32 s4, v0
+; GFX7-GI-NEXT: s_ashr_i32 s4, s4, 31
+; GFX7-GI-NEXT: v_readfirstlane_b32 s7, v3
+; GFX7-GI-NEXT: v_readfirstlane_b32 s6, v1
+; GFX7-GI-NEXT: s_mov_b32 s5, s4
+; GFX7-GI-NEXT: s_lshr_b32 s16, s17, 16
+; GFX7-GI-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v5, s10
+; GFX7-GI-NEXT: s_sub_u32 s8, s6, s4
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0xdf000000
+; GFX7-GI-NEXT: s_subb_u32 s9, s7, s4
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1
+; GFX7-GI-NEXT: v_mov_b32_e32 v3, 0x5effffff
+; GFX7-GI-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GFX7-GI-NEXT: s_mov_b32 s6, 0
+; GFX7-GI-NEXT: s_brev_b32 s7, 1
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v0, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[4:5], s[6:7], s[8:9]
+; GFX7-GI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; GFX7-GI-NEXT: v_trunc_f32_e32 v0, v5
+; GFX7-GI-NEXT: v_mul_f32_e64 v6, |v0|, v2
+; GFX7-GI-NEXT: v_floor_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_fma_f32 v0, v6, v4, |v0|
+; GFX7-GI-NEXT: s_mov_b32 s8, -1
+; GFX7-GI-NEXT: s_brev_b32 s9, -2
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX7-GI-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
+; GFX7-GI-NEXT: s_or_b64 s[10:11], vcc, vcc
+; GFX7-GI-NEXT: v_readfirstlane_b32 s10, v5
+; GFX7-GI-NEXT: s_cselect_b64 s[4:5], 0, s[4:5]
+; GFX7-GI-NEXT: s_ashr_i32 s10, s10, 31
+; GFX7-GI-NEXT: v_readfirstlane_b32 s13, v6
+; GFX7-GI-NEXT: v_readfirstlane_b32 s12, v0
+; GFX7-GI-NEXT: s_mov_b32 s11, s10
+; GFX7-GI-NEXT: s_xor_b64 s[12:13], s[12:13], s[10:11]
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v0, s17
+; GFX7-GI-NEXT: s_sub_u32 s12, s12, s10
+; GFX7-GI-NEXT: s_subb_u32 s13, s13, s10
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v5, v1
+; GFX7-GI-NEXT: s_or_b64 s[10:11], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v5, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[10:11], s[6:7], s[12:13]
+; GFX7-GI-NEXT: s_or_b64 s[12:13], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; GFX7-GI-NEXT: v_trunc_f32_e32 v5, v0
+; GFX7-GI-NEXT: v_mul_f32_e64 v6, |v5|, v2
+; GFX7-GI-NEXT: v_floor_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_fma_f32 v5, v6, v4, |v5|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX7-GI-NEXT: s_cselect_b64 s[10:11], s[8:9], s[10:11]
+; GFX7-GI-NEXT: s_or_b64 s[12:13], vcc, vcc
+; GFX7-GI-NEXT: v_readfirstlane_b32 s12, v0
+; GFX7-GI-NEXT: s_cselect_b64 s[10:11], 0, s[10:11]
+; GFX7-GI-NEXT: s_ashr_i32 s12, s12, 31
+; GFX7-GI-NEXT: v_readfirstlane_b32 s15, v6
+; GFX7-GI-NEXT: v_readfirstlane_b32 s14, v5
+; GFX7-GI-NEXT: s_mov_b32 s13, s12
+; GFX7-GI-NEXT: s_xor_b64 s[14:15], s[14:15], s[12:13]
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v5, s16
+; GFX7-GI-NEXT: s_sub_u32 s14, s14, s12
+; GFX7-GI-NEXT: s_subb_u32 s15, s15, s12
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v0, v1
+; GFX7-GI-NEXT: s_or_b64 s[12:13], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v0, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[12:13], s[6:7], s[14:15]
+; GFX7-GI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; GFX7-GI-NEXT: v_trunc_f32_e32 v0, v5
+; GFX7-GI-NEXT: v_mul_f32_e64 v2, |v0|, v2
+; GFX7-GI-NEXT: v_floor_f32_e32 v2, v2
+; GFX7-GI-NEXT: v_fma_f32 v0, v2, v4, |v0|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX7-GI-NEXT: s_cselect_b64 s[12:13], s[8:9], s[12:13]
+; GFX7-GI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; GFX7-GI-NEXT: v_readfirstlane_b32 s14, v5
+; GFX7-GI-NEXT: s_cselect_b64 s[12:13], 0, s[12:13]
+; GFX7-GI-NEXT: s_ashr_i32 s14, s14, 31
+; GFX7-GI-NEXT: v_readfirstlane_b32 s17, v2
+; GFX7-GI-NEXT: v_readfirstlane_b32 s16, v0
+; GFX7-GI-NEXT: s_mov_b32 s15, s14
+; GFX7-GI-NEXT: s_xor_b64 s[16:17], s[16:17], s[14:15]
+; GFX7-GI-NEXT: s_sub_u32 s16, s16, s14
+; GFX7-GI-NEXT: s_subb_u32 s17, s17, s14
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v5, v1
+; GFX7-GI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v5, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[6:7], s[6:7], s[16:17]
+; GFX7-GI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; GFX7-GI-NEXT: s_cselect_b64 s[6:7], s[8:9], s[6:7]
+; GFX7-GI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; GFX7-GI-NEXT: s_cselect_b64 s[6:7], 0, s[6:7]
+; GFX7-GI-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-GI-NEXT: v_mov_b32_e32 v2, s10
+; GFX7-GI-NEXT: v_mov_b32_e32 v3, s11
+; GFX7-GI-NEXT: v_mov_b32_e32 v4, s12
+; GFX7-GI-NEXT: v_mov_b32_e32 v5, s13
+; GFX7-GI-NEXT: v_mov_b32_e32 v6, s6
+; GFX7-GI-NEXT: v_mov_b32_e32 v7, s7
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_v4f16_v4i64:
@@ -4043,20 +4307,125 @@ define <4 x i64> @test_s_signed_v4f16_v4i64(<4 x half> inreg %f) {
; GFX12-GI-NEXT: s_wait_samplecnt 0x0
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
-; GFX12-GI-NEXT: s_cvt_f32_f16 s2, s0
+; GFX12-GI-NEXT: s_cvt_f32_f16 s8, s0
+; GFX12-GI-NEXT: s_mov_b32 s6, 0
+; GFX12-GI-NEXT: s_brev_b32 s7, 1
; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s0, s0
-; GFX12-GI-NEXT: s_cvt_f32_f16 s3, s1
-; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s1, s1
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: s_cvt_i32_f32 s2, s2
-; GFX12-GI-NEXT: s_cvt_i32_f32 s0, s0
-; GFX12-GI-NEXT: s_cvt_i32_f32 s3, s3
-; GFX12-GI-NEXT: s_cvt_i32_f32 s1, s1
+; GFX12-GI-NEXT: s_trunc_f32 s2, s8
+; GFX12-GI-NEXT: s_cvt_f32_f16 s14, s1
+; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s15, s1
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_and_b32 s3, s2, 0x7fffffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_mul_f32 s2, s3, 0x2f800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s4, s2
+; GFX12-GI-NEXT: s_ashr_i32 s2, s8, 31
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s3, s4, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s5, s4
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s4, s3
+; GFX12-GI-NEXT: s_mov_b32 s3, s2
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_xor_b64 s[4:5], s[4:5], s[2:3]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s8, 0xdf000000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_sub_nc_u64 s[2:3], s[4:5], s[2:3]
+; GFX12-GI-NEXT: s_mov_b32 s4, -1
+; GFX12-GI-NEXT: s_brev_b32 s5, -2
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s8, 0x5effffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3]
+; GFX12-GI-NEXT: s_cmp_u_f32 s8, s8
+; GFX12-GI-NEXT: s_trunc_f32 s8, s0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[2:3], 0, s[2:3]
+; GFX12-GI-NEXT: s_and_b32 s9, s8, 0x7fffffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-GI-NEXT: s_mul_f32 s8, s9, 0x2f800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s10, s8
+; GFX12-GI-NEXT: s_ashr_i32 s8, s0, 31
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s9, s10, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s11, s10
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v5, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v6, s1 :: v_dual_mov_b32 v7, 0
+; GFX12-GI-NEXT: s_cvt_u32_f32 s10, s9
+; GFX12-GI-NEXT: s_mov_b32 s9, s8
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_xor_b64 s[10:11], s[10:11], s[8:9]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s0, 0xdf000000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_sub_nc_u64 s[8:9], s[10:11], s[8:9]
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[8:9], s[6:7], s[8:9]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s0, 0x5effffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[8:9], s[4:5], s[8:9]
+; GFX12-GI-NEXT: s_cmp_u_f32 s0, s0
+; GFX12-GI-NEXT: s_trunc_f32 s0, s14
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[8:9], 0, s[8:9]
+; GFX12-GI-NEXT: s_bitset0_b32 s0, 31
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9
+; GFX12-GI-NEXT: s_mul_f32 s10, s0, 0x2f800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s11, s10
+; GFX12-GI-NEXT: s_ashr_i32 s10, s14, 31
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s0, s11, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s13, s11
+; GFX12-GI-NEXT: s_mov_b32 s11, s10
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s12, s0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_xor_b64 s[12:13], s[12:13], s[10:11]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s14, 0xdf000000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_sub_nc_u64 s[10:11], s[12:13], s[10:11]
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[10:11], s[6:7], s[10:11]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s14, 0x5effffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[0:1], s[4:5], s[10:11]
+; GFX12-GI-NEXT: s_cmp_u_f32 s14, s14
+; GFX12-GI-NEXT: s_trunc_f32 s10, s15
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]
+; GFX12-GI-NEXT: s_and_b32 s11, s10, 0x7fffffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s1
+; GFX12-GI-NEXT: s_mul_f32 s10, s11, 0x2f800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s12, s10
+; GFX12-GI-NEXT: s_ashr_i32 s10, s15, 31
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s11, s12, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s13, s12
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s12, s11
+; GFX12-GI-NEXT: s_mov_b32 s11, s10
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_xor_b64 s[12:13], s[12:13], s[10:11]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s15, 0xdf000000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_sub_nc_u64 s[10:11], s[12:13], s[10:11]
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s15, 0x5effffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7]
+; GFX12-GI-NEXT: s_cmp_u_f32 s15, s15
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[4:5], 0, s[4:5]
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <4 x i64> @llvm.fptosi.sat.v4f16.v4i64(<4 x half> %f)
ret <4 x i64> %x
@@ -5161,35 +5530,184 @@ define <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
; GFX7-GI-LABEL: test_signed_v8f16_v8i64:
; GFX7-GI: ; %bb.0:
; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GI-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX7-GI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v8, v0
+; GFX7-GI-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0x2f800000
+; GFX7-GI-NEXT: v_mov_b32_e32 v6, 0xcf800000
+; GFX7-GI-NEXT: v_trunc_f32_e32 v0, v8
+; GFX7-GI-NEXT: v_mul_f32_e64 v4, |v0|, v5
+; GFX7-GI-NEXT: v_floor_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_fma_f32 v0, v4, v6, |v0|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_ashrrev_i32_e32 v9, 31, v8
+; GFX7-GI-NEXT: v_mov_b32_e32 v14, 0x5effffff
+; GFX7-GI-NEXT: v_xor_b32_e32 v0, v0, v9
+; GFX7-GI-NEXT: v_xor_b32_e32 v4, v4, v9
+; GFX7-GI-NEXT: v_sub_i32_e32 v10, vcc, v0, v9
+; GFX7-GI-NEXT: v_subb_u32_e32 v0, vcc, v4, v9, vcc
+; GFX7-GI-NEXT: v_mov_b32_e32 v4, 0xdf000000
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v8, v4
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v9, v10, 0, vcc
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v10, v7
+; GFX7-GI-NEXT: v_cmp_gt_f32_e64 s[4:5], v8, v14
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v7, v9, -1, s[4:5]
+; GFX7-GI-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; GFX7-GI-NEXT: v_trunc_f32_e32 v9, v10
+; GFX7-GI-NEXT: v_mul_f32_e64 v13, |v9|, v5
+; GFX7-GI-NEXT: v_floor_f32_e32 v13, v13
+; GFX7-GI-NEXT: v_fma_f32 v9, v13, v6, |v9|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v9, v9
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v13, v13
; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-GI-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX7-GI-NEXT: v_lshrrev_b32_e32 v8, 16, v3
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v6, v5
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v5, v4
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v4, v1
+; GFX7-GI-NEXT: v_cmp_u_f32_e64 s[6:7], v8, v8
+; GFX7-GI-NEXT: v_ashrrev_i32_e32 v8, 31, v10
+; GFX7-GI-NEXT: v_xor_b32_e32 v9, v9, v8
+; GFX7-GI-NEXT: v_xor_b32_e32 v13, v13, v8
+; GFX7-GI-NEXT: v_sub_i32_e64 v9, s[8:9], v9, v8
+; GFX7-GI-NEXT: v_subb_u32_e64 v8, s[8:9], v13, v8, s[8:9]
+; GFX7-GI-NEXT: v_trunc_f32_e32 v13, v1
+; GFX7-GI-NEXT: v_mul_f32_e64 v15, |v13|, v5
+; GFX7-GI-NEXT: v_floor_f32_e32 v15, v15
+; GFX7-GI-NEXT: v_fma_f32 v13, v15, v6, |v13|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v13, v13
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v15, v15
+; GFX7-GI-NEXT: v_cmp_nge_f32_e64 s[8:9], v10, v4
+; GFX7-GI-NEXT: v_cmp_gt_f32_e64 s[10:11], v10, v14
+; GFX7-GI-NEXT: v_cmp_u_f32_e64 s[12:13], v10, v10
+; GFX7-GI-NEXT: v_ashrrev_i32_e32 v10, 31, v1
+; GFX7-GI-NEXT: v_xor_b32_e32 v13, v13, v10
+; GFX7-GI-NEXT: v_xor_b32_e32 v15, v15, v10
+; GFX7-GI-NEXT: v_sub_i32_e64 v13, s[14:15], v13, v10
+; GFX7-GI-NEXT: v_subb_u32_e64 v10, s[14:15], v15, v10, s[14:15]
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v15, v11
+; GFX7-GI-NEXT: v_cmp_nge_f32_e64 s[14:15], v1, v4
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v11, v13, 0, s[14:15]
+; GFX7-GI-NEXT: v_cmp_gt_f32_e64 s[16:17], v1, v14
+; GFX7-GI-NEXT: v_trunc_f32_e32 v13, v15
+; GFX7-GI-NEXT: v_mul_f32_e64 v16, |v13|, v5
+; GFX7-GI-NEXT: v_floor_f32_e32 v16, v16
+; GFX7-GI-NEXT: v_fma_f32 v13, v16, v6, |v13|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v13, v13
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v16, v16
+; GFX7-GI-NEXT: v_cmp_u_f32_e64 s[18:19], v1, v1
+; GFX7-GI-NEXT: v_ashrrev_i32_e32 v1, 31, v15
+; GFX7-GI-NEXT: v_xor_b32_e32 v13, v13, v1
+; GFX7-GI-NEXT: v_xor_b32_e32 v16, v16, v1
+; GFX7-GI-NEXT: v_sub_i32_e64 v13, s[20:21], v13, v1
+; GFX7-GI-NEXT: v_subb_u32_e64 v16, s[20:21], v16, v1, s[20:21]
; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v1, v2
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v2, v7
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v7, v8
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v6, v6
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v8, v1
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v10, v2
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v12, v3
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v14, v7
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v2, v5
-; GFX7-GI-NEXT: v_mov_b32_e32 v3, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v7, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v9, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v11, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v13, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v15, 0
+; GFX7-GI-NEXT: v_cmp_nge_f32_e64 s[20:21], v15, v4
+; GFX7-GI-NEXT: v_lshrrev_b32_e32 v12, 16, v2
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v13, 0, s[20:21]
+; GFX7-GI-NEXT: v_cmp_gt_f32_e64 s[22:23], v15, v14
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v13, v2, -1, s[22:23]
+; GFX7-GI-NEXT: v_trunc_f32_e32 v2, v1
+; GFX7-GI-NEXT: v_mul_f32_e64 v17, |v2|, v5
+; GFX7-GI-NEXT: v_floor_f32_e32 v17, v17
+; GFX7-GI-NEXT: v_fma_f32 v2, v17, v6, |v2|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v17, v17
+; GFX7-GI-NEXT: v_cmp_u_f32_e64 s[24:25], v15, v15
+; GFX7-GI-NEXT: v_ashrrev_i32_e32 v15, 31, v1
+; GFX7-GI-NEXT: v_xor_b32_e32 v2, v2, v15
+; GFX7-GI-NEXT: v_xor_b32_e32 v17, v17, v15
+; GFX7-GI-NEXT: v_sub_i32_e64 v2, s[26:27], v2, v15
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v12, v12
+; GFX7-GI-NEXT: v_subb_u32_e64 v15, s[26:27], v17, v15, s[26:27]
+; GFX7-GI-NEXT: v_cmp_nge_f32_e64 s[26:27], v1, v4
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[26:27]
+; GFX7-GI-NEXT: v_cmp_gt_f32_e64 s[28:29], v1, v14
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v17, v2, -1, s[28:29]
+; GFX7-GI-NEXT: v_trunc_f32_e32 v2, v12
+; GFX7-GI-NEXT: v_mul_f32_e64 v18, |v2|, v5
+; GFX7-GI-NEXT: v_floor_f32_e32 v18, v18
+; GFX7-GI-NEXT: v_fma_f32 v2, v18, v6, |v2|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v18, v18
+; GFX7-GI-NEXT: v_cmp_u_f32_e64 s[40:41], v1, v1
+; GFX7-GI-NEXT: v_ashrrev_i32_e32 v1, 31, v12
+; GFX7-GI-NEXT: v_xor_b32_e32 v2, v2, v1
+; GFX7-GI-NEXT: v_xor_b32_e32 v18, v18, v1
+; GFX7-GI-NEXT: v_sub_i32_e64 v2, s[42:43], v2, v1
+; GFX7-GI-NEXT: v_subb_u32_e64 v18, s[42:43], v18, v1, s[42:43]
+; GFX7-GI-NEXT: v_cmp_nge_f32_e64 s[42:43], v12, v4
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v2, 0, s[42:43]
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v2, v3
+; GFX7-GI-NEXT: v_cmp_gt_f32_e64 s[44:45], v12, v14
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v19, v1, -1, s[44:45]
+; GFX7-GI-NEXT: v_cmp_u_f32_e64 s[46:47], v12, v12
+; GFX7-GI-NEXT: v_trunc_f32_e32 v1, v2
+; GFX7-GI-NEXT: v_mul_f32_e64 v12, |v1|, v5
+; GFX7-GI-NEXT: v_floor_f32_e32 v12, v12
+; GFX7-GI-NEXT: v_fma_f32 v1, v12, v6, |v1|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v12, v12
+; GFX7-GI-NEXT: v_ashrrev_i32_e32 v20, 31, v2
+; GFX7-GI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX7-GI-NEXT: v_xor_b32_e32 v1, v1, v20
+; GFX7-GI-NEXT: v_xor_b32_e32 v12, v12, v20
+; GFX7-GI-NEXT: v_sub_i32_e64 v1, s[56:57], v1, v20
+; GFX7-GI-NEXT: v_subb_u32_e64 v12, s[56:57], v12, v20, s[56:57]
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v20, v3
+; GFX7-GI-NEXT: v_cmp_nge_f32_e64 s[56:57], v2, v4
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[56:57]
+; GFX7-GI-NEXT: v_cmp_gt_f32_e64 s[58:59], v2, v14
+; GFX7-GI-NEXT: v_trunc_f32_e32 v3, v20
+; GFX7-GI-NEXT: v_mul_f32_e64 v5, |v3|, v5
+; GFX7-GI-NEXT: v_floor_f32_e32 v5, v5
+; GFX7-GI-NEXT: v_fma_f32 v3, v5, v6, |v3|
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v21, v1, -1, s[58:59]
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v3
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v3, v5
+; GFX7-GI-NEXT: v_cmp_u_f32_e64 s[60:61], v2, v2
+; GFX7-GI-NEXT: v_ashrrev_i32_e32 v2, 31, v20
+; GFX7-GI-NEXT: v_xor_b32_e32 v1, v1, v2
+; GFX7-GI-NEXT: v_xor_b32_e32 v3, v3, v2
+; GFX7-GI-NEXT: v_sub_i32_e64 v22, s[62:63], v1, v2
+; GFX7-GI-NEXT: v_bfrev_b32_e32 v24, 1
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v9, v9, 0, s[8:9]
+; GFX7-GI-NEXT: v_subb_u32_e64 v23, s[62:63], v3, v2, s[62:63]
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v0, v0, v24, vcc
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v20, v4
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v9, v9, -1, s[10:11]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v11, v11, -1, s[16:17]
+; GFX7-GI-NEXT: v_bfrev_b32_e32 v25, -2
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v8, v24, s[8:9]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v10, v24, s[14:15]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v6, v16, v24, s[20:21]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v8, v15, v24, s[26:27]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v10, v18, v24, s[42:43]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v12, v12, v24, s[56:57]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v15, v22, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v16, v23, v24, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v20, v14
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v0, v25, s[4:5]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v7, 0, s[6:7]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v2, v25, s[10:11]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v9, 0, s[12:13]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v5, v4, v25, s[16:17]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v11, 0, s[18:19]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v7, v6, v25, s[22:23]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v6, v13, 0, s[24:25]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v9, v8, v25, s[28:29]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v11, v10, v25, s[44:45]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v13, v12, v25, s[58:59]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v14, v15, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e32 v15, v16, v25, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[6:7]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[12:13]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v5, v5, 0, s[18:19]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v7, v7, 0, s[24:25]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v8, v17, 0, s[40:41]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v9, v9, 0, s[40:41]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v10, v19, 0, s[46:47]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v11, v11, 0, s[46:47]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v12, v21, 0, s[60:61]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v13, v13, 0, s[60:61]
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v14, v14, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v15, v15, 0, vcc
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_v8f16_v8i64:
@@ -5374,30 +5892,204 @@ define <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
; GFX12-GI-NEXT: s_wait_samplecnt 0x0
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
-; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v5, v0.h
; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v4, v0.l
-; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v6, v1.l
-; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v1, v1.h
-; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v7, v2.l
-; GFX12-GI-NEXT: v_cvt_i32_f32_e32 v5, v5
+; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v5, v0.h
+; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v7, v1.l
+; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v9, v1.h
+; GFX12-GI-NEXT: v_trunc_f32_e32 v0, v4
+; GFX12-GI-NEXT: v_trunc_f32_e32 v6, v5
+; GFX12-GI-NEXT: v_ashrrev_i32_e32 v11, 31, v4
+; GFX12-GI-NEXT: v_trunc_f32_e32 v10, v7
+; GFX12-GI-NEXT: v_ashrrev_i32_e32 v12, 31, v5
+; GFX12-GI-NEXT: v_mul_f32_e64 v8, 0x2f800000, |v0|
+; GFX12-GI-NEXT: v_mul_f32_e64 v1, 0x2f800000, |v6|
+; GFX12-GI-NEXT: v_trunc_f32_e32 v15, v9
+; GFX12-GI-NEXT: v_mul_f32_e64 v13, 0x2f800000, |v10|
+; GFX12-GI-NEXT: v_ashrrev_i32_e32 v14, 31, v7
+; GFX12-GI-NEXT: v_floor_f32_e32 v8, v8
+; GFX12-GI-NEXT: v_floor_f32_e32 v1, v1
+; GFX12-GI-NEXT: v_floor_f32_e32 v13, v13
+; GFX12-GI-NEXT: v_fma_f32 v0, 0xcf800000, v8, |v0|
+; GFX12-GI-NEXT: v_fma_f32 v6, 0xcf800000, v1, |v6|
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-GI-NEXT: v_fma_f32 v10, 0xcf800000, v13, |v10|
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX12-GI-NEXT: v_xor_b32_e32 v8, v8, v11
+; GFX12-GI-NEXT: v_xor_b32_e32 v1, v1, v12
+; GFX12-GI-NEXT: v_xor_b32_e32 v0, v0, v11
+; GFX12-GI-NEXT: v_xor_b32_e32 v6, v6, v12
+; GFX12-GI-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v11
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_sub_co_ci_u32_e64 v8, null, v8, v11, vcc_lo
+; GFX12-GI-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v4
+; GFX12-GI-NEXT: v_sub_co_u32 v6, s0, v6, v12
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v12, s0
+; GFX12-GI-NEXT: v_cmp_nle_f32_e64 s0, 0xdf000000, v5
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v8, v8, 0x80000000, vcc_lo
+; GFX12-GI-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v4
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v11, v13
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v6, v6, 0, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v12, v1, 0x80000000, s0
+; GFX12-GI-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v5
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v8, 0x7fffffff, vcc_lo
+; GFX12-GI-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v4, v10
+; GFX12-GI-NEXT: v_mul_f32_e64 v10, 0x2f800000, |v15|
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v6, v6, -1, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v8, v12, 0x7fffffff, s0
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
+; GFX12-GI-NEXT: v_xor_b32_e32 v4, v4, v14
+; GFX12-GI-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX12-GI-NEXT: v_floor_f32_e32 v10, v10
+; GFX12-GI-NEXT: v_xor_b32_e32 v5, v11, v14
+; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v11, v2.l
+; GFX12-GI-NEXT: v_sub_co_u32 v4, s0, v4, v14
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v16, v6, 0, vcc_lo
+; GFX12-GI-NEXT: v_fma_f32 v6, 0xcf800000, v10, |v15|
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_sub_co_ci_u32_e64 v5, null, v5, v14, s0
+; GFX12-GI-NEXT: v_cmp_nle_f32_e64 s0, 0xdf000000, v7
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v17, v8, 0, vcc_lo
+; GFX12-GI-NEXT: v_ashrrev_i32_e32 v8, 31, v9
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX12-GI-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v7
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v4, v4, 0, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v5, 0x80000000, s0
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v10, v10
+; GFX12-GI-NEXT: v_trunc_f32_e32 v12, v11
+; GFX12-GI-NEXT: v_xor_b32_e32 v6, v6, v8
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v4, v4, -1, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v5, 0x7fffffff, vcc_lo
+; GFX12-GI-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX12-GI-NEXT: v_xor_b32_e32 v7, v10, v8
+; GFX12-GI-NEXT: v_mul_f32_e64 v10, 0x2f800000, |v12|
+; GFX12-GI-NEXT: v_sub_co_u32 v6, s0, v6, v8
; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v2, v2.h
-; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v9, v3.l
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_sub_co_ci_u32_e64 v7, null, v7, v8, s0
+; GFX12-GI-NEXT: v_floor_f32_e32 v8, v10
+; GFX12-GI-NEXT: v_cmp_nle_f32_e64 s0, 0xdf000000, v9
+; GFX12-GI-NEXT: v_ashrrev_i32_e32 v13, 31, v11
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
+; GFX12-GI-NEXT: v_fma_f32 v10, 0xcf800000, v8, |v12|
+; GFX12-GI-NEXT: v_trunc_f32_e32 v12, v2
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v6, v6, 0, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v7, v7, 0x80000000, s0
+; GFX12-GI-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v9
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v10, v10
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX12-GI-NEXT: v_mul_f32_e64 v14, 0x2f800000, |v12|
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v6, v6, -1, vcc_lo
+; GFX12-GI-NEXT: v_xor_b32_e32 v10, v10, v13
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v7, v7, 0x7fffffff, vcc_lo
+; GFX12-GI-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX12-GI-NEXT: v_xor_b32_e32 v8, v8, v13
+; GFX12-GI-NEXT: v_floor_f32_e32 v9, v14
+; GFX12-GI-NEXT: v_sub_co_u32 v10, s0, v10, v13
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_sub_co_ci_u32_e64 v8, null, v8, v13, s0
+; GFX12-GI-NEXT: v_cmp_nle_f32_e64 s0, 0xdf000000, v11
+; GFX12-GI-NEXT: v_fma_f32 v12, 0xcf800000, v9, |v12|
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc_lo
+; GFX12-GI-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v11
+; GFX12-GI-NEXT: v_ashrrev_i32_e32 v13, 31, v2
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v8, v8, 0x80000000, s0
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v12, v12
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v9, v9
+; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v14, v3.l
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v10, v10, 0, s0
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v15, v8, 0x7fffffff, vcc_lo
+; GFX12-GI-NEXT: v_xor_b32_e32 v8, v12, v13
+; GFX12-GI-NEXT: v_xor_b32_e32 v9, v9, v13
+; GFX12-GI-NEXT: v_trunc_f32_e32 v12, v14
; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v3, v3.h
-; GFX12-GI-NEXT: v_cvt_i32_f32_e32 v0, v4
-; GFX12-GI-NEXT: v_cvt_i32_f32_e32 v4, v6
-; GFX12-GI-NEXT: v_cvt_i32_f32_e32 v6, v1
-; GFX12-GI-NEXT: v_cvt_i32_f32_e32 v8, v7
-; GFX12-GI-NEXT: v_cvt_i32_f32_e32 v10, v2
-; GFX12-GI-NEXT: v_cvt_i32_f32_e32 v12, v9
-; GFX12-GI-NEXT: v_cvt_i32_f32_e32 v14, v3
-; GFX12-GI-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, v5
-; GFX12-GI-NEXT: v_mov_b32_e32 v3, 0
-; GFX12-GI-NEXT: v_mov_b32_e32 v5, 0
-; GFX12-GI-NEXT: v_mov_b32_e32 v7, 0
-; GFX12-GI-NEXT: v_mov_b32_e32 v9, 0
-; GFX12-GI-NEXT: v_mov_b32_e32 v11, 0
-; GFX12-GI-NEXT: v_mov_b32_e32 v13, 0
-; GFX12-GI-NEXT: v_mov_b32_e32 v15, 0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v10, v10, -1, vcc_lo
+; GFX12-GI-NEXT: v_sub_co_u32 v18, vcc_lo, v8, v13
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_sub_co_ci_u32_e64 v9, null, v9, v13, vcc_lo
+; GFX12-GI-NEXT: v_trunc_f32_e32 v13, v3
+; GFX12-GI-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v2
+; GFX12-GI-NEXT: v_mul_f32_e64 v19, 0x2f800000, |v12|
+; GFX12-GI-NEXT: v_cmp_u_f32_e64 s0, v11, v11
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v11, v18, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v18, v9, 0x80000000, vcc_lo
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v8, v10, 0, s0
+; GFX12-GI-NEXT: v_mul_f32_e64 v10, 0x2f800000, |v13|
+; GFX12-GI-NEXT: v_floor_f32_e32 v19, v19
+; GFX12-GI-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v2
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v9, v15, 0, s0
+; GFX12-GI-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; GFX12-GI-NEXT: v_floor_f32_e32 v20, v10
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v10, v11, -1, vcc_lo
+; GFX12-GI-NEXT: v_fma_f32 v11, 0xcf800000, v19, |v12|
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v12, v18, 0x7fffffff, vcc_lo
+; GFX12-GI-NEXT: v_fma_f32 v13, 0xcf800000, v20, |v13|
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v18, v19
+; GFX12-GI-NEXT: v_ashrrev_i32_e32 v19, 31, v3
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GFX12-GI-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v13, v13
+; GFX12-GI-NEXT: v_xor_b32_e32 v2, v11, v15
+; GFX12-GI-NEXT: v_xor_b32_e32 v11, v18, v15
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v18, v20
+; GFX12-GI-NEXT: v_xor_b32_e32 v13, v13, v19
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc_lo
+; GFX12-GI-NEXT: v_sub_co_u32 v2, s0, v2, v15
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_sub_co_ci_u32_e64 v11, null, v11, v15, s0
+; GFX12-GI-NEXT: v_xor_b32_e32 v15, v18, v19
+; GFX12-GI-NEXT: v_sub_co_u32 v13, s1, v13, v19
+; GFX12-GI-NEXT: v_cmp_nle_f32_e64 s0, 0xdf000000, v14
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_sub_co_ci_u32_e64 v15, null, v15, v19, s1
+; GFX12-GI-NEXT: v_cmp_nle_f32_e64 s1, 0xdf000000, v3
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v11, v11, 0x80000000, s0
+; GFX12-GI-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v14
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v13, v13, 0, s1
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v15, v15, 0x80000000, s1
+; GFX12-GI-NEXT: v_cmp_lt_f32_e64 s1, 0x5effffff, v3
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v2, -1, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v18, v11, 0x7fffffff, s0
+; GFX12-GI-NEXT: v_cmp_u_f32_e64 s0, v14, v14
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v11, v12, 0, vcc_lo
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v14, v13, -1, s1
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v15, v15, 0x7fffffff, s1
+; GFX12-GI-NEXT: v_cmp_u_f32_e64 s1, v3, v3
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v12, v2, 0, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v13, v18, 0, s0
+; GFX12-GI-NEXT: v_dual_mov_b32 v2, v16 :: v_dual_mov_b32 v3, v17
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v14, v14, 0, s1
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v15, v15, 0, s1
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <8 x i64> @llvm.fptosi.sat.v8f16.v8i64(<8 x half> %f)
ret <8 x i64> %x
@@ -6560,34 +7252,226 @@ define <8 x i64> @test_s_signed_v8f16_v8i64(<8 x half> inreg %f) {
; GFX7-GI-LABEL: test_s_signed_v8f16_v8i64:
; GFX7-GI: ; %bb.0:
; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GI-NEXT: s_lshr_b32 s4, s16, 16
-; GFX7-GI-NEXT: s_lshr_b32 s5, s17, 16
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v1, s4
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v3, s17
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v5, s5
-; GFX7-GI-NEXT: s_lshr_b32 s6, s18, 16
-; GFX7-GI-NEXT: s_lshr_b32 s7, s19, 16
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v0, s16
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v2, v1
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v4, v3
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v6, v5
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v1, s18
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v3, s6
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v5, s19
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v7, s7
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v8, v1
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v10, v3
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v12, v5
-; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v14, v7
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v3, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v7, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v9, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v11, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v13, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v15, 0
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v4, s16
+; GFX7-GI-NEXT: v_mov_b32_e32 v0, 0x2f800000
+; GFX7-GI-NEXT: s_lshr_b32 s10, s16, 16
+; GFX7-GI-NEXT: s_lshr_b32 s16, s17, 16
+; GFX7-GI-NEXT: v_trunc_f32_e32 v2, v4
+; GFX7-GI-NEXT: v_mul_f32_e64 v1, |v2|, v0
+; GFX7-GI-NEXT: v_floor_f32_e32 v3, v1
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0xcf800000
+; GFX7-GI-NEXT: v_fma_f32 v2, v3, v1, |v2|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX7-GI-NEXT: v_readfirstlane_b32 s4, v4
+; GFX7-GI-NEXT: s_ashr_i32 s4, s4, 31
+; GFX7-GI-NEXT: v_readfirstlane_b32 s7, v3
+; GFX7-GI-NEXT: v_readfirstlane_b32 s6, v2
+; GFX7-GI-NEXT: s_mov_b32 s5, s4
+; GFX7-GI-NEXT: s_lshr_b32 s21, s18, 16
+; GFX7-GI-NEXT: s_lshr_b32 s20, s19, 16
+; GFX7-GI-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v5, s10
+; GFX7-GI-NEXT: s_sub_u32 s8, s6, s4
+; GFX7-GI-NEXT: v_mov_b32_e32 v2, 0xdf000000
+; GFX7-GI-NEXT: s_subb_u32 s9, s7, s4
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v4, v2
+; GFX7-GI-NEXT: v_mov_b32_e32 v3, 0x5effffff
+; GFX7-GI-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GFX7-GI-NEXT: s_mov_b32 s6, 0
+; GFX7-GI-NEXT: s_brev_b32 s7, 1
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[4:5], s[6:7], s[8:9]
+; GFX7-GI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX7-GI-NEXT: v_trunc_f32_e32 v4, v5
+; GFX7-GI-NEXT: v_mul_f32_e64 v6, |v4|, v0
+; GFX7-GI-NEXT: v_floor_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_fma_f32 v4, v6, v1, |v4|
+; GFX7-GI-NEXT: s_mov_b32 s8, -1
+; GFX7-GI-NEXT: s_brev_b32 s9, -2
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
+; GFX7-GI-NEXT: s_or_b64 s[10:11], vcc, vcc
+; GFX7-GI-NEXT: v_readfirstlane_b32 s10, v5
+; GFX7-GI-NEXT: s_cselect_b64 s[4:5], 0, s[4:5]
+; GFX7-GI-NEXT: s_ashr_i32 s10, s10, 31
+; GFX7-GI-NEXT: v_readfirstlane_b32 s13, v6
+; GFX7-GI-NEXT: v_readfirstlane_b32 s12, v4
+; GFX7-GI-NEXT: s_mov_b32 s11, s10
+; GFX7-GI-NEXT: s_xor_b64 s[12:13], s[12:13], s[10:11]
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v4, s17
+; GFX7-GI-NEXT: s_sub_u32 s12, s12, s10
+; GFX7-GI-NEXT: s_subb_u32 s13, s13, s10
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v5, v2
+; GFX7-GI-NEXT: s_or_b64 s[10:11], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v5, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[10:11], s[6:7], s[12:13]
+; GFX7-GI-NEXT: s_or_b64 s[12:13], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; GFX7-GI-NEXT: v_trunc_f32_e32 v5, v4
+; GFX7-GI-NEXT: v_mul_f32_e64 v6, |v5|, v0
+; GFX7-GI-NEXT: v_floor_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_fma_f32 v5, v6, v1, |v5|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX7-GI-NEXT: s_cselect_b64 s[10:11], s[8:9], s[10:11]
+; GFX7-GI-NEXT: s_or_b64 s[12:13], vcc, vcc
+; GFX7-GI-NEXT: v_readfirstlane_b32 s12, v4
+; GFX7-GI-NEXT: s_cselect_b64 s[10:11], 0, s[10:11]
+; GFX7-GI-NEXT: s_ashr_i32 s12, s12, 31
+; GFX7-GI-NEXT: v_readfirstlane_b32 s15, v6
+; GFX7-GI-NEXT: v_readfirstlane_b32 s14, v5
+; GFX7-GI-NEXT: s_mov_b32 s13, s12
+; GFX7-GI-NEXT: s_xor_b64 s[14:15], s[14:15], s[12:13]
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v5, s16
+; GFX7-GI-NEXT: s_sub_u32 s14, s14, s12
+; GFX7-GI-NEXT: s_subb_u32 s15, s15, s12
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v4, v2
+; GFX7-GI-NEXT: s_or_b64 s[12:13], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[12:13], s[6:7], s[14:15]
+; GFX7-GI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX7-GI-NEXT: v_trunc_f32_e32 v4, v5
+; GFX7-GI-NEXT: v_mul_f32_e64 v6, |v4|, v0
+; GFX7-GI-NEXT: v_floor_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_fma_f32 v4, v6, v1, |v4|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: s_cselect_b64 s[12:13], s[8:9], s[12:13]
+; GFX7-GI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; GFX7-GI-NEXT: v_readfirstlane_b32 s14, v5
+; GFX7-GI-NEXT: s_cselect_b64 s[12:13], 0, s[12:13]
+; GFX7-GI-NEXT: s_ashr_i32 s14, s14, 31
+; GFX7-GI-NEXT: v_readfirstlane_b32 s17, v6
+; GFX7-GI-NEXT: v_readfirstlane_b32 s16, v4
+; GFX7-GI-NEXT: s_mov_b32 s15, s14
+; GFX7-GI-NEXT: s_xor_b64 s[16:17], s[16:17], s[14:15]
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v4, s18
+; GFX7-GI-NEXT: s_sub_u32 s16, s16, s14
+; GFX7-GI-NEXT: s_subb_u32 s17, s17, s14
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v5, v2
+; GFX7-GI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v5, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[14:15], s[6:7], s[16:17]
+; GFX7-GI-NEXT: s_or_b64 s[16:17], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; GFX7-GI-NEXT: v_trunc_f32_e32 v5, v4
+; GFX7-GI-NEXT: v_mul_f32_e64 v6, |v5|, v0
+; GFX7-GI-NEXT: v_floor_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_fma_f32 v5, v6, v1, |v5|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX7-GI-NEXT: s_cselect_b64 s[14:15], s[8:9], s[14:15]
+; GFX7-GI-NEXT: s_or_b64 s[16:17], vcc, vcc
+; GFX7-GI-NEXT: v_readfirstlane_b32 s16, v4
+; GFX7-GI-NEXT: s_cselect_b64 s[14:15], 0, s[14:15]
+; GFX7-GI-NEXT: s_ashr_i32 s16, s16, 31
+; GFX7-GI-NEXT: v_readfirstlane_b32 s23, v6
+; GFX7-GI-NEXT: v_readfirstlane_b32 s22, v5
+; GFX7-GI-NEXT: s_mov_b32 s17, s16
+; GFX7-GI-NEXT: s_xor_b64 s[22:23], s[22:23], s[16:17]
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v5, s21
+; GFX7-GI-NEXT: s_sub_u32 s22, s22, s16
+; GFX7-GI-NEXT: s_subb_u32 s23, s23, s16
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v4, v2
+; GFX7-GI-NEXT: s_or_b64 s[16:17], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[16:17], s[6:7], s[22:23]
+; GFX7-GI-NEXT: s_or_b64 s[22:23], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX7-GI-NEXT: v_trunc_f32_e32 v4, v5
+; GFX7-GI-NEXT: v_mul_f32_e64 v6, |v4|, v0
+; GFX7-GI-NEXT: v_floor_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_fma_f32 v4, v6, v1, |v4|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: s_cselect_b64 s[16:17], s[8:9], s[16:17]
+; GFX7-GI-NEXT: s_or_b64 s[22:23], vcc, vcc
+; GFX7-GI-NEXT: v_readfirstlane_b32 s18, v5
+; GFX7-GI-NEXT: s_cselect_b64 s[16:17], 0, s[16:17]
+; GFX7-GI-NEXT: s_ashr_i32 s22, s18, 31
+; GFX7-GI-NEXT: v_readfirstlane_b32 s25, v6
+; GFX7-GI-NEXT: v_readfirstlane_b32 s24, v4
+; GFX7-GI-NEXT: s_mov_b32 s23, s22
+; GFX7-GI-NEXT: s_xor_b64 s[24:25], s[24:25], s[22:23]
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v4, s19
+; GFX7-GI-NEXT: s_sub_u32 s24, s24, s22
+; GFX7-GI-NEXT: s_subb_u32 s25, s25, s22
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v5, v2
+; GFX7-GI-NEXT: s_or_b64 s[22:23], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v5, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[22:23], s[6:7], s[24:25]
+; GFX7-GI-NEXT: s_or_b64 s[24:25], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; GFX7-GI-NEXT: v_trunc_f32_e32 v5, v4
+; GFX7-GI-NEXT: v_mul_f32_e64 v6, |v5|, v0
+; GFX7-GI-NEXT: v_floor_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_fma_f32 v5, v6, v1, |v5|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX7-GI-NEXT: s_cselect_b64 s[22:23], s[8:9], s[22:23]
+; GFX7-GI-NEXT: s_or_b64 s[18:19], vcc, vcc
+; GFX7-GI-NEXT: v_readfirstlane_b32 s21, v4
+; GFX7-GI-NEXT: s_cselect_b64 s[18:19], 0, s[22:23]
+; GFX7-GI-NEXT: s_ashr_i32 s22, s21, 31
+; GFX7-GI-NEXT: v_readfirstlane_b32 s25, v6
+; GFX7-GI-NEXT: v_readfirstlane_b32 s24, v5
+; GFX7-GI-NEXT: s_mov_b32 s23, s22
+; GFX7-GI-NEXT: s_xor_b64 s[24:25], s[24:25], s[22:23]
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v5, s20
+; GFX7-GI-NEXT: s_sub_u32 s24, s24, s22
+; GFX7-GI-NEXT: s_subb_u32 s25, s25, s22
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v4, v2
+; GFX7-GI-NEXT: s_or_b64 s[22:23], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[22:23], s[6:7], s[24:25]
+; GFX7-GI-NEXT: s_or_b64 s[24:25], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX7-GI-NEXT: v_trunc_f32_e32 v4, v5
+; GFX7-GI-NEXT: v_mul_f32_e64 v0, |v4|, v0
+; GFX7-GI-NEXT: v_floor_f32_e32 v0, v0
+; GFX7-GI-NEXT: v_fma_f32 v1, v0, v1, |v4|
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX7-GI-NEXT: s_cselect_b64 s[22:23], s[8:9], s[22:23]
+; GFX7-GI-NEXT: s_or_b64 s[20:21], vcc, vcc
+; GFX7-GI-NEXT: s_cselect_b64 s[20:21], 0, s[22:23]
+; GFX7-GI-NEXT: v_readfirstlane_b32 s22, v5
+; GFX7-GI-NEXT: s_ashr_i32 s22, s22, 31
+; GFX7-GI-NEXT: v_readfirstlane_b32 s25, v0
+; GFX7-GI-NEXT: v_readfirstlane_b32 s24, v1
+; GFX7-GI-NEXT: s_mov_b32 s23, s22
+; GFX7-GI-NEXT: s_xor_b64 s[24:25], s[24:25], s[22:23]
+; GFX7-GI-NEXT: s_sub_u32 s24, s24, s22
+; GFX7-GI-NEXT: s_subb_u32 s25, s25, s22
+; GFX7-GI-NEXT: v_cmp_nge_f32_e32 vcc, v5, v2
+; GFX7-GI-NEXT: s_or_b64 s[22:23], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v5, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[6:7], s[6:7], s[24:25]
+; GFX7-GI-NEXT: s_or_b64 s[22:23], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
+; GFX7-GI-NEXT: s_cselect_b64 s[6:7], s[8:9], s[6:7]
+; GFX7-GI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; GFX7-GI-NEXT: s_cselect_b64 s[6:7], 0, s[6:7]
+; GFX7-GI-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-GI-NEXT: v_mov_b32_e32 v2, s10
+; GFX7-GI-NEXT: v_mov_b32_e32 v3, s11
+; GFX7-GI-NEXT: v_mov_b32_e32 v4, s12
+; GFX7-GI-NEXT: v_mov_b32_e32 v5, s13
+; GFX7-GI-NEXT: v_mov_b32_e32 v6, s14
+; GFX7-GI-NEXT: v_mov_b32_e32 v7, s15
+; GFX7-GI-NEXT: v_mov_b32_e32 v8, s16
+; GFX7-GI-NEXT: v_mov_b32_e32 v9, s17
+; GFX7-GI-NEXT: v_mov_b32_e32 v10, s18
+; GFX7-GI-NEXT: v_mov_b32_e32 v11, s19
+; GFX7-GI-NEXT: v_mov_b32_e32 v12, s20
+; GFX7-GI-NEXT: v_mov_b32_e32 v13, s21
+; GFX7-GI-NEXT: v_mov_b32_e32 v14, s6
+; GFX7-GI-NEXT: v_mov_b32_e32 v15, s7
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_v8f16_v8i64:
@@ -6707,32 +7591,237 @@ define <8 x i64> @test_s_signed_v8f16_v8i64(<8 x half> inreg %f) {
; GFX12-GI-NEXT: s_wait_samplecnt 0x0
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
-; GFX12-GI-NEXT: s_cvt_f32_f16 s4, s0
+; GFX12-GI-NEXT: s_cvt_f32_f16 s10, s0
; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s0, s0
-; GFX12-GI-NEXT: s_cvt_f32_f16 s5, s1
-; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s1, s1
-; GFX12-GI-NEXT: s_cvt_f32_f16 s6, s2
+; GFX12-GI-NEXT: s_cvt_f32_f16 s16, s1
+; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s17, s1
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_trunc_f32 s4, s10
+; GFX12-GI-NEXT: s_cvt_f32_f16 s18, s2
; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s2, s2
-; GFX12-GI-NEXT: s_cvt_f32_f16 s7, s3
-; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s3, s3
+; GFX12-GI-NEXT: s_cvt_f32_f16 s22, s3
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: s_cvt_i32_f32 s4, s4
-; GFX12-GI-NEXT: s_cvt_i32_f32 s0, s0
-; GFX12-GI-NEXT: s_cvt_i32_f32 s5, s5
-; GFX12-GI-NEXT: s_cvt_i32_f32 s1, s1
-; GFX12-GI-NEXT: s_cvt_i32_f32 s6, s6
-; GFX12-GI-NEXT: s_cvt_i32_f32 s2, s2
-; GFX12-GI-NEXT: s_cvt_i32_f32 s7, s7
-; GFX12-GI-NEXT: s_cvt_i32_f32 s3, s3
+; GFX12-GI-NEXT: s_and_b32 s5, s4, 0x7fffffff
+; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s23, s3
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_mul_f32 s4, s5, 0x2f800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s6, s4
+; GFX12-GI-NEXT: s_ashr_i32 s4, s10, 31
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s5, s6, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s7, s6
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s6, s5
+; GFX12-GI-NEXT: s_mov_b32 s5, s4
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_xor_b64 s[8:9], s[6:7], s[4:5]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s10, 0xdf000000
+; GFX12-GI-NEXT: s_mov_b32 s6, 0
+; GFX12-GI-NEXT: s_brev_b32 s7, 1
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_sub_nc_u64 s[4:5], s[8:9], s[4:5]
+; GFX12-GI-NEXT: s_mov_b32 s8, -1
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s10, 0x5effffff
+; GFX12-GI-NEXT: s_brev_b32 s9, -2
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
+; GFX12-GI-NEXT: s_cmp_u_f32 s10, s10
+; GFX12-GI-NEXT: s_trunc_f32 s10, s0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[4:5], 0, s[4:5]
+; GFX12-GI-NEXT: s_and_b32 s11, s10, 0x7fffffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX12-GI-NEXT: s_mul_f32 s10, s11, 0x2f800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s12, s10
+; GFX12-GI-NEXT: s_ashr_i32 s10, s0, 31
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s11, s12, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s13, s12
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s12, s11
+; GFX12-GI-NEXT: s_mov_b32 s11, s10
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_xor_b64 s[12:13], s[12:13], s[10:11]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s0, 0xdf000000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_sub_nc_u64 s[10:11], s[12:13], s[10:11]
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[10:11], s[6:7], s[10:11]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s0, 0x5effffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[10:11], s[8:9], s[10:11]
+; GFX12-GI-NEXT: s_cmp_u_f32 s0, s0
+; GFX12-GI-NEXT: s_trunc_f32 s0, s16
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[10:11], 0, s[10:11]
+; GFX12-GI-NEXT: s_bitset0_b32 s0, 31
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
+; GFX12-GI-NEXT: s_mul_f32 s12, s0, 0x2f800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s13, s12
+; GFX12-GI-NEXT: s_ashr_i32 s12, s16, 31
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s0, s13, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s15, s13
+; GFX12-GI-NEXT: s_mov_b32 s13, s12
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s14, s0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_xor_b64 s[14:15], s[14:15], s[12:13]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s16, 0xdf000000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_sub_nc_u64 s[12:13], s[14:15], s[12:13]
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[12:13], s[6:7], s[12:13]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s16, 0x5effffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[0:1], s[8:9], s[12:13]
+; GFX12-GI-NEXT: s_cmp_u_f32 s16, s16
+; GFX12-GI-NEXT: s_trunc_f32 s12, s17
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]
+; GFX12-GI-NEXT: s_and_b32 s13, s12, 0x7fffffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s1
+; GFX12-GI-NEXT: s_mul_f32 s12, s13, 0x2f800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s14, s12
+; GFX12-GI-NEXT: s_ashr_i32 s12, s17, 31
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s13, s14, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s15, s14
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s14, s13
+; GFX12-GI-NEXT: s_mov_b32 s13, s12
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_xor_b64 s[14:15], s[14:15], s[12:13]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s17, 0xdf000000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_sub_nc_u64 s[12:13], s[14:15], s[12:13]
+; GFX12-GI-NEXT: s_trunc_f32 s14, s18
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[12:13], s[6:7], s[12:13]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s17, 0x5effffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[12:13], s[8:9], s[12:13]
+; GFX12-GI-NEXT: s_cmp_u_f32 s17, s17
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[12:13], 0, s[12:13]
+; GFX12-GI-NEXT: s_and_b32 s15, s14, 0x7fffffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v7, s13
+; GFX12-GI-NEXT: s_mul_f32 s14, s15, 0x2f800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s16, s14
+; GFX12-GI-NEXT: s_ashr_i32 s14, s18, 31
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s15, s16, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s17, s16
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s16, s15
+; GFX12-GI-NEXT: s_mov_b32 s15, s14
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_xor_b64 s[16:17], s[16:17], s[14:15]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s18, 0xdf000000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_sub_nc_u64 s[14:15], s[16:17], s[14:15]
+; GFX12-GI-NEXT: s_trunc_f32 s16, s2
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[14:15], s[6:7], s[14:15]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s18, 0x5effffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[14:15], s[8:9], s[14:15]
+; GFX12-GI-NEXT: s_cmp_u_f32 s18, s18
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[14:15], 0, s[14:15]
+; GFX12-GI-NEXT: s_and_b32 s17, s16, 0x7fffffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v9, s15
+; GFX12-GI-NEXT: s_mul_f32 s16, s17, 0x2f800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s18, s16
+; GFX12-GI-NEXT: s_ashr_i32 s16, s2, 31
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s17, s18, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s19, s18
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s18, s17
+; GFX12-GI-NEXT: s_mov_b32 s17, s16
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_xor_b64 s[18:19], s[18:19], s[16:17]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s2, 0xdf000000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_sub_nc_u64 s[16:17], s[18:19], s[16:17]
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[16:17], s[6:7], s[16:17]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s2, 0x5effffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[16:17], s[8:9], s[16:17]
+; GFX12-GI-NEXT: s_cmp_u_f32 s2, s2
+; GFX12-GI-NEXT: s_trunc_f32 s2, s22
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[16:17], 0, s[16:17]
+; GFX12-GI-NEXT: s_bitset0_b32 s2, 31
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_dual_mov_b32 v10, s16 :: v_dual_mov_b32 v11, s17
+; GFX12-GI-NEXT: s_mul_f32 s18, s2, 0x2f800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s19, s18
+; GFX12-GI-NEXT: s_ashr_i32 s18, s22, 31
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s2, s19, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s21, s19
+; GFX12-GI-NEXT: s_mov_b32 s19, s18
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s20, s2
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_xor_b64 s[20:21], s[20:21], s[18:19]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s22, 0xdf000000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_sub_nc_u64 s[18:19], s[20:21], s[18:19]
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[18:19], s[6:7], s[18:19]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s22, 0x5effffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[2:3], s[8:9], s[18:19]
+; GFX12-GI-NEXT: s_cmp_u_f32 s22, s22
+; GFX12-GI-NEXT: s_trunc_f32 s18, s23
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[2:3], 0, s[2:3]
+; GFX12-GI-NEXT: s_and_b32 s19, s18, 0x7fffffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v13, s3
+; GFX12-GI-NEXT: s_mul_f32 s18, s19, 0x2f800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s20, s18
+; GFX12-GI-NEXT: s_ashr_i32 s18, s23, 31
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s19, s20, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s21, s20
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s20, s19
+; GFX12-GI-NEXT: s_mov_b32 s19, s18
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_xor_b64 s[20:21], s[20:21], s[18:19]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s23, 0xdf000000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_sub_nc_u64 s[18:19], s[20:21], s[18:19]
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[6:7], s[6:7], s[18:19]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s23, 0x5effffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[6:7], s[8:9], s[6:7]
+; GFX12-GI-NEXT: s_cmp_u_f32 s23, s23
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[6:7], 0, s[6:7]
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v6, s1 :: v_dual_mov_b32 v7, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v12, s7 :: v_dual_mov_b32 v13, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v14, s3 :: v_dual_mov_b32 v15, 0
+; GFX12-GI-NEXT: v_dual_mov_b32 v14, s6 :: v_dual_mov_b32 v15, s7
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <8 x i64> @llvm.fptosi.sat.v8f16.v8i64(<8 x half> %f)
ret <8 x i64> %x
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
index 8b6df1ca1e69c..ec58b0090e5a4 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
@@ -1509,13 +1509,33 @@ define i32 @test_unsigned_i32_f16(half %f) nounwind {
}
define i64 @test_unsigned_i64_f16(half %f) nounwind {
-; GFX7-LABEL: test_unsigned_i64_f16:
-; GFX7: ; %bb.0:
-; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX7-NEXT: s_setpc_b64 s[30:31]
+; GFX7-ISEL-LABEL: test_unsigned_i64_f16:
+; GFX7-ISEL: ; %bb.0:
+; GFX7-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX7-ISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-GI-LABEL: test_unsigned_i64_f16:
+; GFX7-GI: ; %bb.0:
+; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0xcf800000
+; GFX7-GI-NEXT: v_trunc_f32_e32 v2, v0
+; GFX7-GI-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; GFX7-GI-NEXT: v_floor_f32_e32 v3, v3
+; GFX7-GI-NEXT: v_fma_f32 v1, v3, v1, v2
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v3
+; GFX7-GI-NEXT: v_mov_b32_e32 v3, 0x5f7fffff
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v0
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v0, v3
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v1, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v2, -1, vcc
+; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_unsigned_i64_f16:
; GFX9: ; %bb.0:
@@ -1573,8 +1593,20 @@ define i64 @test_unsigned_i64_f16(half %f) nounwind {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX12-GI-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-GI-NEXT: v_trunc_f32_e32 v1, v0
+; GFX12-GI-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v0
+; GFX12-GI-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
+; GFX12-GI-NEXT: v_floor_f32_e32 v2, v2
+; GFX12-GI-NEXT: v_fmac_f32_e32 v1, 0xcf800000, v2
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
+; GFX12-GI-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v0
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v1, -1, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v2, -1, vcc_lo
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i64 @llvm.fptoui.sat.i64.f16(half %f)
ret i64 %x
@@ -1852,13 +1884,37 @@ define i32 @test_s_unsigned_i32_f16(half inreg %f) nounwind {
}
define i64 @test_s_unsigned_i64_f16(half inreg %f) nounwind {
-; GFX7-LABEL: test_s_unsigned_i64_f16:
-; GFX7: ; %bb.0:
-; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, s16
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX7-NEXT: s_setpc_b64 s[30:31]
+; GFX7-ISEL-LABEL: test_s_unsigned_i64_f16:
+; GFX7-ISEL: ; %bb.0:
+; GFX7-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v0, s16
+; GFX7-ISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-GI-LABEL: test_s_unsigned_i64_f16:
+; GFX7-GI: ; %bb.0:
+; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v0, s16
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0xcf800000
+; GFX7-GI-NEXT: v_mov_b32_e32 v2, 0x5f7fffff
+; GFX7-GI-NEXT: v_trunc_f32_e32 v3, v0
+; GFX7-GI-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
+; GFX7-GI-NEXT: v_floor_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_fma_f32 v1, v4, v1, v3
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v3, v4
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v0
+; GFX7-GI-NEXT: s_or_b64 s[4:5], vcc, vcc
+; GFX7-GI-NEXT: v_readfirstlane_b32 s5, v3
+; GFX7-GI-NEXT: v_readfirstlane_b32 s4, v1
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; GFX7-GI-NEXT: s_cselect_b64 s[4:5], 0, s[4:5]
+; GFX7-GI-NEXT: s_or_b64 s[6:7], vcc, vcc
+; GFX7-GI-NEXT: s_cselect_b64 s[4:5], -1, s[4:5]
+; GFX7-GI-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_unsigned_i64_f16:
; GFX9: ; %bb.0:
@@ -1876,20 +1932,49 @@ define i64 @test_s_unsigned_i64_f16(half inreg %f) nounwind {
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: test_s_unsigned_i64_f16:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_cvt_f32_f16 s0, s0
-; GFX12-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_cvt_u32_f32 s0, s0
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX12-ISEL-LABEL: test_s_unsigned_i64_f16:
+; GFX12-ISEL: ; %bb.0:
+; GFX12-ISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-ISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-ISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-ISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-ISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-ISEL-NEXT: s_cvt_f32_f16 s0, s0
+; GFX12-ISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s0, s0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GI-LABEL: test_s_unsigned_i64_f16:
+; GFX12-GI: ; %bb.0:
+; GFX12-GI-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GI-NEXT: s_wait_expcnt 0x0
+; GFX12-GI-NEXT: s_wait_samplecnt 0x0
+; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GI-NEXT: s_wait_kmcnt 0x0
+; GFX12-GI-NEXT: s_cvt_f32_f16 s2, s0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_trunc_f32 s0, s2
+; GFX12-GI-NEXT: s_cmp_nge_f32 s2, 0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_mul_f32 s1, s0, 0x2f800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s1, s1
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s0, s1, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s1, s1
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s0, s0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s2, 0x5f7fffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[0:1], -1, s[0:1]
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i64 @llvm.fptoui.sat.i64.f16(half %f)
ret i64 %x
}
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
index 830e14ec13ad1..c1afbd5d2aa8e 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
@@ -2917,20 +2917,63 @@ define <4 x i64> @test_unsigned_v4f16_v4i64(<4 x half> %f) {
; GFX7-GI-LABEL: test_unsigned_v4f16_v4i64:
; GFX7-GI: ; %bb.0:
; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX7-GI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0xcf800000
+; GFX7-GI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v7, v0
+; GFX7-GI-NEXT: v_trunc_f32_e32 v3, v2
+; GFX7-GI-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
+; GFX7-GI-NEXT: v_floor_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_fma_f32 v3, v4, v5, v3
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v2
+; GFX7-GI-NEXT: v_mov_b32_e32 v9, 0x5f7fffff
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v2, v9
+; GFX7-GI-NEXT: v_trunc_f32_e32 v2, v7
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v3, -1, vcc
+; GFX7-GI-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; GFX7-GI-NEXT: v_floor_f32_e32 v3, v3
+; GFX7-GI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX7-GI-NEXT: v_fma_f32 v2, v3, v5, v2
; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v1
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v6, v3
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v3, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v7, 0
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v8, v4, -1, vcc
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v7
+; GFX7-GI-NEXT: v_trunc_f32_e32 v4, v1
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v7, v9
+; GFX7-GI-NEXT: v_mul_f32_e32 v7, 0x2f800000, v4
+; GFX7-GI-NEXT: v_floor_f32_e32 v7, v7
+; GFX7-GI-NEXT: v_fma_f32 v4, v7, v5, v4
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v6, v6
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v3, v3, -1, vcc
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v1
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v1, v9
+; GFX7-GI-NEXT: v_trunc_f32_e32 v1, v6
+; GFX7-GI-NEXT: v_mul_f32_e32 v10, 0x2f800000, v1
+; GFX7-GI-NEXT: v_floor_f32_e32 v10, v10
+; GFX7-GI-NEXT: v_fma_f32 v1, v10, v5, v1
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v10, v10
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v4, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v5, v7, -1, vcc
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v6
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v7, v10, 0, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v6, v9
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v6, v1, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v7, v7, -1, vcc
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, v8
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_unsigned_v4f16_v4i64:
@@ -3044,15 +3087,57 @@ define <4 x i64> @test_unsigned_v4f16_v4i64(<4 x half> %f) {
; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v2, v0.l
; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v3, v0.h
; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v4, v1.l
-; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v1, v1.h
-; GFX12-GI-NEXT: v_mov_b32_e32 v5, 0
-; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v0, v2
-; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v2, v3
-; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
-; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v6, v1
-; GFX12-GI-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-GI-NEXT: v_mov_b32_e32 v3, 0
-; GFX12-GI-NEXT: v_mov_b32_e32 v7, 0
+; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v5, v1.h
+; GFX12-GI-NEXT: v_trunc_f32_e32 v0, v2
+; GFX12-GI-NEXT: v_trunc_f32_e32 v1, v3
+; GFX12-GI-NEXT: v_trunc_f32_e32 v6, v4
+; GFX12-GI-NEXT: v_trunc_f32_e32 v7, v5
+; GFX12-GI-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v2
+; GFX12-GI-NEXT: v_dual_mul_f32 v8, 0x2f800000, v0 :: v_dual_mul_f32 v9, 0x2f800000, v1
+; GFX12-GI-NEXT: v_dual_mul_f32 v10, 0x2f800000, v6 :: v_dual_mul_f32 v11, 0x2f800000, v7
+; GFX12-GI-NEXT: v_cmp_nle_f32_e64 s0, 0, v3
+; GFX12-GI-NEXT: v_floor_f32_e32 v8, v8
+; GFX12-GI-NEXT: v_floor_f32_e32 v9, v9
+; GFX12-GI-NEXT: v_floor_f32_e32 v10, v10
+; GFX12-GI-NEXT: v_floor_f32_e32 v11, v11
+; GFX12-GI-NEXT: v_cmp_nle_f32_e64 s1, 0, v4
+; GFX12-GI-NEXT: v_dual_fmac_f32 v0, 0xcf800000, v8 :: v_dual_fmac_f32 v1, 0xcf800000, v9
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v9, v9
+; GFX12-GI-NEXT: v_dual_fmac_f32 v6, 0xcf800000, v10 :: v_dual_fmac_f32 v7, 0xcf800000, v11
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc_lo
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v10, v10
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo
+; GFX12-GI-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v2
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v1, 0, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v9, v9, 0, s0
+; GFX12-GI-NEXT: v_cmp_nle_f32_e64 s0, 0, v5
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v8, -1, vcc_lo
+; GFX12-GI-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v3
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v3, v7
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v6, v6, 0, s1
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v7, v10, 0, s1
+; GFX12-GI-NEXT: v_cmp_lt_f32_e64 s1, 0x5f7fffff, v4
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v10, v11, 0, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v8, v3, 0, s0
+; GFX12-GI-NEXT: v_cmp_lt_f32_e64 s0, 0x5f7fffff, v5
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v3, v9, -1, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v4, v6, -1, s1
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v7, -1, s1
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v6, v8, -1, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v7, v10, -1, s0
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <4 x i64> @llvm.fptoui.sat.v4f16.v4i64(<4 x half> %f)
ret <4 x i64> %x
@@ -3658,20 +3743,78 @@ define <4 x i64> @test_s_unsigned_v4f16_v4i64(<4 x half> inreg %f) {
; GFX7-GI-LABEL: test_s_unsigned_v4f16_v4i64:
; GFX7-GI: ; %bb.0:
; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GI-NEXT: s_lshr_b32 s4, s16, 16
-; GFX7-GI-NEXT: s_lshr_b32 s5, s17, 16
; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v0, s16
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v1, s4
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v3, s17
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v5, s5
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0xcf800000
+; GFX7-GI-NEXT: s_lshr_b32 s8, s16, 16
+; GFX7-GI-NEXT: s_lshr_b32 s10, s17, 16
+; GFX7-GI-NEXT: v_trunc_f32_e32 v2, v0
+; GFX7-GI-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; GFX7-GI-NEXT: v_floor_f32_e32 v3, v3
+; GFX7-GI-NEXT: v_fma_f32 v2, v3, v1, v2
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v0
+; GFX7-GI-NEXT: s_or_b64 s[6:7], vcc, vcc
+; GFX7-GI-NEXT: v_readfirstlane_b32 s4, v2
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v2, s8
+; GFX7-GI-NEXT: v_readfirstlane_b32 s5, v3
+; GFX7-GI-NEXT: v_mov_b32_e32 v3, 0x5f7fffff
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v0, v3
+; GFX7-GI-NEXT: v_trunc_f32_e32 v0, v2
+; GFX7-GI-NEXT: v_mul_f32_e32 v4, 0x2f800000, v0
+; GFX7-GI-NEXT: v_floor_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_fma_f32 v0, v4, v1, v0
; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v1
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v3
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v6, v5
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v3, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v7, 0
+; GFX7-GI-NEXT: s_cselect_b64 s[4:5], 0, s[4:5]
+; GFX7-GI-NEXT: s_or_b64 s[6:7], vcc, vcc
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_readfirstlane_b32 s6, v0
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v0, s17
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v2
+; GFX7-GI-NEXT: s_cselect_b64 s[4:5], -1, s[4:5]
+; GFX7-GI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v2, v3
+; GFX7-GI-NEXT: v_trunc_f32_e32 v2, v0
+; GFX7-GI-NEXT: v_readfirstlane_b32 s7, v4
+; GFX7-GI-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
+; GFX7-GI-NEXT: v_floor_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_fma_f32 v2, v4, v1, v2
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX7-GI-NEXT: s_cselect_b64 s[6:7], 0, s[6:7]
+; GFX7-GI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_readfirstlane_b32 s8, v2
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v2, s10
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v0
+; GFX7-GI-NEXT: s_cselect_b64 s[6:7], -1, s[6:7]
+; GFX7-GI-NEXT: s_or_b64 s[10:11], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v0, v3
+; GFX7-GI-NEXT: v_trunc_f32_e32 v0, v2
+; GFX7-GI-NEXT: v_readfirstlane_b32 s9, v4
+; GFX7-GI-NEXT: v_mul_f32_e32 v4, 0x2f800000, v0
+; GFX7-GI-NEXT: v_floor_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_fma_f32 v0, v4, v1, v0
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v4
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX7-GI-NEXT: s_cselect_b64 s[8:9], 0, s[8:9]
+; GFX7-GI-NEXT: s_or_b64 s[10:11], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v2
+; GFX7-GI-NEXT: s_cselect_b64 s[8:9], -1, s[8:9]
+; GFX7-GI-NEXT: v_readfirstlane_b32 s11, v1
+; GFX7-GI-NEXT: v_readfirstlane_b32 s10, v0
+; GFX7-GI-NEXT: s_or_b64 s[12:13], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v2, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[10:11], 0, s[10:11]
+; GFX7-GI-NEXT: s_or_b64 s[12:13], vcc, vcc
+; GFX7-GI-NEXT: s_cselect_b64 s[10:11], -1, s[10:11]
+; GFX7-GI-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-GI-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-GI-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-GI-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-GI-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-GI-NEXT: v_mov_b32_e32 v6, s10
+; GFX7-GI-NEXT: v_mov_b32_e32 v7, s11
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_unsigned_v4f16_v4i64:
@@ -3743,19 +3886,67 @@ define <4 x i64> @test_s_unsigned_v4f16_v4i64(<4 x half> inreg %f) {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: s_cvt_f32_f16 s2, s0
-; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s0, s0
-; GFX12-GI-NEXT: s_cvt_f32_f16 s3, s1
-; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s1, s1
+; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s4, s0
+; GFX12-GI-NEXT: s_cvt_f32_f16 s6, s1
+; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s8, s1
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: s_cvt_u32_f32 s2, s2
-; GFX12-GI-NEXT: s_cvt_u32_f32 s0, s0
-; GFX12-GI-NEXT: s_cvt_u32_f32 s3, s3
-; GFX12-GI-NEXT: s_cvt_u32_f32 s1, s1
+; GFX12-GI-NEXT: s_trunc_f32 s3, s2
+; GFX12-GI-NEXT: s_trunc_f32 s5, s4
+; GFX12-GI-NEXT: s_cmp_nge_f32 s2, 0
+; GFX12-GI-NEXT: s_trunc_f32 s7, s6
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_mul_f32 s0, s3, 0x2f800000
+; GFX12-GI-NEXT: s_mul_f32 s1, s5, 0x2f800000
+; GFX12-GI-NEXT: s_trunc_f32 s10, s8
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s0, s0
+; GFX12-GI-NEXT: s_floor_f32 s9, s1
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s3, s0, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s1, s0
+; GFX12-GI-NEXT: s_fmac_f32 s5, s9, 0xcf800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s0, s3
+; GFX12-GI-NEXT: s_mul_f32 s3, s7, 0x2f800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s2, 0x5f7fffff
+; GFX12-GI-NEXT: s_floor_f32 s11, s3
+; GFX12-GI-NEXT: s_cvt_u32_f32 s3, s9
+; GFX12-GI-NEXT: s_cvt_u32_f32 s2, s5
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[0:1], -1, s[0:1]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s4, 0
+; GFX12-GI-NEXT: s_mul_f32 s5, s10, 0x2f800000
+; GFX12-GI-NEXT: s_fmac_f32 s7, s11, 0xcf800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GI-NEXT: s_cselect_b64 s[2:3], 0, s[2:3]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s4, 0x5f7fffff
+; GFX12-GI-NEXT: s_floor_f32 s9, s5
+; GFX12-GI-NEXT: s_cvt_u32_f32 s5, s11
+; GFX12-GI-NEXT: s_cvt_u32_f32 s4, s7
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[2:3], -1, s[2:3]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s6, 0
+; GFX12-GI-NEXT: s_fmac_f32 s10, s9, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s7, s9
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v5, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v6, s1 :: v_dual_mov_b32 v7, 0
+; GFX12-GI-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX12-GI-NEXT: s_cselect_b64 s[4:5], 0, s[4:5]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s6, 0x5f7fffff
+; GFX12-GI-NEXT: s_cvt_u32_f32 s6, s10
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[4:5], -1, s[4:5]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s8, 0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
+; GFX12-GI-NEXT: s_cselect_b64 s[6:7], 0, s[6:7]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s8, 0x5f7fffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[6:7], -1, s[6:7]
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <4 x i64> @llvm.fptoui.sat.v4f16.v4i64(<4 x half> %f)
ret <4 x i64> %x
@@ -4812,35 +5003,119 @@ define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
; GFX7-GI-LABEL: test_unsigned_v8f16_v8i64:
; GFX7-GI: ; %bb.0:
; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GI-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v4, v0
+; GFX7-GI-NEXT: v_mov_b32_e32 v13, 0xcf800000
+; GFX7-GI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v9, v0
+; GFX7-GI-NEXT: v_trunc_f32_e32 v6, v4
+; GFX7-GI-NEXT: v_mul_f32_e32 v7, 0x2f800000, v6
+; GFX7-GI-NEXT: v_floor_f32_e32 v7, v7
+; GFX7-GI-NEXT: v_fma_f32 v6, v7, v13, v6
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v4
+; GFX7-GI-NEXT: v_mov_b32_e32 v14, 0x5f7fffff
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v4, v14
+; GFX7-GI-NEXT: v_trunc_f32_e32 v4, v9
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v0, v6, -1, vcc
+; GFX7-GI-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4
+; GFX7-GI-NEXT: v_floor_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_fma_f32 v4, v6, v13, v4
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX7-GI-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v4, v4
; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-GI-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX7-GI-NEXT: v_lshrrev_b32_e32 v8, 16, v3
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v6, v5
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v5, v4
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v1
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v1, v2
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v2, v7
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v7, v8
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v16, v7, -1, vcc
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v9
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v9, v14
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v17, v4, -1, vcc
+; GFX7-GI-NEXT: v_trunc_f32_e32 v4, v1
+; GFX7-GI-NEXT: v_mul_f32_e32 v7, 0x2f800000, v4
+; GFX7-GI-NEXT: v_floor_f32_e32 v7, v7
+; GFX7-GI-NEXT: v_fma_f32 v4, v7, v13, v4
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v18, v6, -1, vcc
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v6, v7
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v7, v5
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v1
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v5, v6, 0, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v1, v14
+; GFX7-GI-NEXT: v_trunc_f32_e32 v1, v7
+; GFX7-GI-NEXT: v_mul_f32_e32 v6, 0x2f800000, v1
+; GFX7-GI-NEXT: v_floor_f32_e32 v6, v6
+; GFX7-GI-NEXT: v_fma_f32 v1, v6, v13, v1
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v8, v1
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v10, v2
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v12, v3
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v14, v7
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v2, v5
-; GFX7-GI-NEXT: v_mov_b32_e32 v3, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v7, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v9, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v11, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v13, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v15, 0
+; GFX7-GI-NEXT: v_lshrrev_b32_e32 v8, 16, v2
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v4, v4, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v5, v5, -1, vcc
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v7
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v9, v6, 0, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v7, v14
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v6, v1, -1, vcc
+; GFX7-GI-NEXT: v_trunc_f32_e32 v1, v2
+; GFX7-GI-NEXT: v_mul_f32_e32 v7, 0x2f800000, v1
+; GFX7-GI-NEXT: v_floor_f32_e32 v10, v7
+; GFX7-GI-NEXT: v_fma_f32 v1, v10, v13, v1
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v7, v9, -1, vcc
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v9, v10
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v10, v8
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v2
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v2, v14
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v8, v1, -1, vcc
+; GFX7-GI-NEXT: v_trunc_f32_e32 v1, v10
+; GFX7-GI-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
+; GFX7-GI-NEXT: v_floor_f32_e32 v2, v2
+; GFX7-GI-NEXT: v_fma_f32 v1, v2, v13, v1
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX7-GI-NEXT: v_lshrrev_b32_e32 v12, 16, v3
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v9, v9, -1, vcc
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v10
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v10, v14
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v10, v1, -1, vcc
+; GFX7-GI-NEXT: v_trunc_f32_e32 v1, v3
+; GFX7-GI-NEXT: v_mul_f32_e32 v11, 0x2f800000, v1
+; GFX7-GI-NEXT: v_floor_f32_e32 v15, v11
+; GFX7-GI-NEXT: v_fma_f32 v1, v15, v13, v1
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v11, v2, -1, vcc
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v15
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v15, v12
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v3
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v3, v14
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v12, v1, -1, vcc
+; GFX7-GI-NEXT: v_trunc_f32_e32 v1, v15
+; GFX7-GI-NEXT: v_mul_f32_e32 v3, 0x2f800000, v1
+; GFX7-GI-NEXT: v_floor_f32_e32 v3, v3
+; GFX7-GI-NEXT: v_fma_f32 v1, v3, v13, v1
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v13, v2, -1, vcc
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v15
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v2, v3, 0, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v15, v14
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v14, v1, -1, vcc
+; GFX7-GI-NEXT: v_cndmask_b32_e64 v15, v2, -1, vcc
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, v16
+; GFX7-GI-NEXT: v_mov_b32_e32 v2, v17
+; GFX7-GI-NEXT: v_mov_b32_e32 v3, v18
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_unsigned_v8f16_v8i64:
@@ -5020,30 +5295,123 @@ define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
; GFX12-GI-NEXT: s_wait_samplecnt 0x0
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
-; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v5, v0.h
; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v4, v0.l
-; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v6, v1.l
-; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v1, v1.h
-; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v7, v2.l
-; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v0, v0.h
+; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v5, v1.l
+; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v6, v1.h
+; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v14, v2.l
+; GFX12-GI-NEXT: v_trunc_f32_e32 v1, v4
+; GFX12-GI-NEXT: v_trunc_f32_e32 v7, v0
+; GFX12-GI-NEXT: v_trunc_f32_e32 v8, v5
+; GFX12-GI-NEXT: v_trunc_f32_e32 v9, v6
+; GFX12-GI-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v4
+; GFX12-GI-NEXT: v_dual_mul_f32 v10, 0x2f800000, v1 :: v_dual_mul_f32 v11, 0x2f800000, v7
+; GFX12-GI-NEXT: v_dual_mul_f32 v12, 0x2f800000, v8 :: v_dual_mul_f32 v13, 0x2f800000, v9
+; GFX12-GI-NEXT: v_cmp_nle_f32_e64 s0, 0, v0
+; GFX12-GI-NEXT: v_floor_f32_e32 v10, v10
+; GFX12-GI-NEXT: v_floor_f32_e32 v11, v11
+; GFX12-GI-NEXT: v_floor_f32_e32 v12, v12
+; GFX12-GI-NEXT: v_floor_f32_e32 v13, v13
; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v2, v2.h
-; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v9, v3.l
+; GFX12-GI-NEXT: v_fmac_f32_e32 v1, 0xcf800000, v10
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v10, v10
+; GFX12-GI-NEXT: v_dual_fmac_f32 v7, 0xcf800000, v11 :: v_dual_fmac_f32 v8, 0xcf800000, v12
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc_lo
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v12, v12
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
+; GFX12-GI-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v4
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v4, v7, 0, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v7, v11, 0, s0
+; GFX12-GI-NEXT: v_cmp_lt_f32_e64 s0, 0x5f7fffff, v0
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v0, v1, -1, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v1, v10, -1, vcc_lo
+; GFX12-GI-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v5
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v16, v4, -1, s0
+; GFX12-GI-NEXT: v_fmac_f32_e32 v9, 0xcf800000, v13
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v17, v7, -1, s0
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v10, v13
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc_lo
+; GFX12-GI-NEXT: v_trunc_f32_e32 v8, v14
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v7, v12, 0, vcc_lo
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v9, v9
+; GFX12-GI-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v6
+; GFX12-GI-NEXT: v_cmp_lt_f32_e64 s0, 0x5f7fffff, v5
+; GFX12-GI-NEXT: v_mul_f32_e32 v11, 0x2f800000, v8
+; GFX12-GI-NEXT: v_trunc_f32_e32 v12, v2
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc_lo
+; GFX12-GI-NEXT: v_floor_f32_e32 v11, v11
+; GFX12-GI-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v6
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v5, v7, -1, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v4, v4, -1, s0
+; GFX12-GI-NEXT: v_cmp_nle_f32_e64 s0, 0, v2
+; GFX12-GI-NEXT: v_fmac_f32_e32 v8, 0xcf800000, v11
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v7, v10, -1, vcc_lo
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v10, v11
+; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v11, v3.l
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v6, v9, -1, vcc_lo
+; GFX12-GI-NEXT: v_mul_f32_e32 v9, 0x2f800000, v12
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX12-GI-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v14
+; GFX12-GI-NEXT: v_trunc_f32_e32 v13, v11
; GFX12-GI-NEXT: v_cvt_f32_f16_e32 v3, v3.h
-; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v0, v4
-; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v4, v6
-; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v6, v1
-; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v8, v7
-; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v10, v2
-; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v12, v9
-; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v14, v3
-; GFX12-GI-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, v5
-; GFX12-GI-NEXT: v_mov_b32_e32 v3, 0
-; GFX12-GI-NEXT: v_mov_b32_e32 v5, 0
-; GFX12-GI-NEXT: v_mov_b32_e32 v7, 0
-; GFX12-GI-NEXT: v_mov_b32_e32 v9, 0
-; GFX12-GI-NEXT: v_mov_b32_e32 v11, 0
-; GFX12-GI-NEXT: v_mov_b32_e32 v13, 0
-; GFX12-GI-NEXT: v_mov_b32_e32 v15, 0
+; GFX12-GI-NEXT: v_floor_f32_e32 v9, v9
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc_lo
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc_lo
+; GFX12-GI-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v14
+; GFX12-GI-NEXT: v_mul_f32_e32 v14, 0x2f800000, v13
+; GFX12-GI-NEXT: v_trunc_f32_e32 v15, v3
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v18, v9
+; GFX12-GI-NEXT: v_cmp_nle_f32_e64 s1, 0, v3
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v8, v8, -1, vcc_lo
+; GFX12-GI-NEXT: v_floor_f32_e32 v14, v14
+; GFX12-GI-NEXT: v_fmac_f32_e32 v12, 0xcf800000, v9
+; GFX12-GI-NEXT: v_mul_f32_e32 v19, 0x2f800000, v15
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v9, v10, -1, vcc_lo
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v18, v18, 0, s0
+; GFX12-GI-NEXT: v_fmac_f32_e32 v13, 0xcf800000, v14
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v12, v12
+; GFX12-GI-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v2
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v2, v14
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v13, v13
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v10, v12, 0, s0
+; GFX12-GI-NEXT: v_floor_f32_e32 v12, v19
+; GFX12-GI-NEXT: v_cmp_nle_f32_e64 s0, 0, v11
+; GFX12-GI-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v10, v10, -1, vcc_lo
+; GFX12-GI-NEXT: v_fmac_f32_e32 v15, 0xcf800000, v12
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v12, v12
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v13, v13, 0, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX12-GI-NEXT: v_cmp_lt_f32_e64 s0, 0x5f7fffff, v11
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v14, v15
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v15, v12, 0, s1
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v11, v18, -1, vcc_lo
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v12, v13, -1, s0
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v14, v14, 0, s1
+; GFX12-GI-NEXT: v_cmp_lt_f32_e64 s1, 0x5f7fffff, v3
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v13, v2, -1, s0
+; GFX12-GI-NEXT: v_dual_mov_b32 v2, v16 :: v_dual_mov_b32 v3, v17
+; GFX12-GI-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v14, v14, -1, s1
+; GFX12-GI-NEXT: v_cndmask_b32_e64 v15, v15, -1, s1
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <8 x i64> @llvm.fptoui.sat.v8f16.v8i64(<8 x half> %f)
ret <8 x i64> %x
@@ -6086,34 +6454,148 @@ define <8 x i64> @test_s_unsigned_v8f16_v8i64(<8 x half> inreg %f) {
; GFX7-GI-LABEL: test_s_unsigned_v8f16_v8i64:
; GFX7-GI: ; %bb.0:
; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GI-NEXT: s_lshr_b32 s4, s16, 16
-; GFX7-GI-NEXT: s_lshr_b32 s5, s17, 16
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v1, s4
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v3, s17
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v5, s5
-; GFX7-GI-NEXT: s_lshr_b32 s6, s18, 16
-; GFX7-GI-NEXT: s_lshr_b32 s7, s19, 16
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v0, s16
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v1
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v3
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v6, v5
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v1, s18
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v3, s6
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v5, s19
-; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v7, s7
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v2, s16
+; GFX7-GI-NEXT: s_lshr_b32 s8, s16, 16
+; GFX7-GI-NEXT: s_lshr_b32 s10, s17, 16
+; GFX7-GI-NEXT: s_lshr_b32 s14, s18, 16
+; GFX7-GI-NEXT: v_trunc_f32_e32 v1, v2
+; GFX7-GI-NEXT: v_mul_f32_e32 v0, 0x2f800000, v1
+; GFX7-GI-NEXT: v_floor_f32_e32 v3, v0
+; GFX7-GI-NEXT: v_mov_b32_e32 v0, 0xcf800000
+; GFX7-GI-NEXT: v_fma_f32 v1, v3, v0, v1
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX7-GI-NEXT: s_lshr_b32 s20, s19, 16
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v2
+; GFX7-GI-NEXT: v_readfirstlane_b32 s5, v3
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v3, s8
+; GFX7-GI-NEXT: v_readfirstlane_b32 s4, v1
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0x5f7fffff
+; GFX7-GI-NEXT: s_or_b64 s[6:7], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v2, v1
+; GFX7-GI-NEXT: v_trunc_f32_e32 v2, v3
+; GFX7-GI-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
+; GFX7-GI-NEXT: v_floor_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_fma_f32 v2, v4, v0, v2
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX7-GI-NEXT: s_cselect_b64 s[4:5], 0, s[4:5]
+; GFX7-GI-NEXT: s_or_b64 s[6:7], vcc, vcc
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_readfirstlane_b32 s6, v2
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v2, s17
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[4:5], -1, s[4:5]
+; GFX7-GI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v3, v1
+; GFX7-GI-NEXT: v_trunc_f32_e32 v3, v2
+; GFX7-GI-NEXT: v_readfirstlane_b32 s7, v4
+; GFX7-GI-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
+; GFX7-GI-NEXT: v_floor_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_fma_f32 v3, v4, v0, v3
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[6:7], 0, s[6:7]
+; GFX7-GI-NEXT: s_or_b64 s[8:9], vcc, vcc
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_readfirstlane_b32 s8, v3
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v3, s10
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v2
+; GFX7-GI-NEXT: s_cselect_b64 s[6:7], -1, s[6:7]
+; GFX7-GI-NEXT: s_or_b64 s[10:11], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v2, v1
+; GFX7-GI-NEXT: v_trunc_f32_e32 v2, v3
+; GFX7-GI-NEXT: v_readfirstlane_b32 s9, v4
+; GFX7-GI-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
+; GFX7-GI-NEXT: v_floor_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_fma_f32 v2, v4, v0, v2
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX7-GI-NEXT: s_cselect_b64 s[8:9], 0, s[8:9]
+; GFX7-GI-NEXT: s_or_b64 s[10:11], vcc, vcc
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_readfirstlane_b32 s10, v2
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v2, s18
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[8:9], -1, s[8:9]
+; GFX7-GI-NEXT: s_or_b64 s[12:13], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v3, v1
+; GFX7-GI-NEXT: v_trunc_f32_e32 v3, v2
+; GFX7-GI-NEXT: v_readfirstlane_b32 s11, v4
+; GFX7-GI-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
+; GFX7-GI-NEXT: v_floor_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_fma_f32 v3, v4, v0, v3
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[10:11], 0, s[10:11]
+; GFX7-GI-NEXT: s_or_b64 s[12:13], vcc, vcc
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_readfirstlane_b32 s12, v3
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v3, s14
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v2
+; GFX7-GI-NEXT: s_cselect_b64 s[10:11], -1, s[10:11]
+; GFX7-GI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v2, v1
+; GFX7-GI-NEXT: v_trunc_f32_e32 v2, v3
+; GFX7-GI-NEXT: v_readfirstlane_b32 s13, v4
+; GFX7-GI-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
+; GFX7-GI-NEXT: v_floor_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_fma_f32 v2, v4, v0, v2
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX7-GI-NEXT: s_cselect_b64 s[12:13], 0, s[12:13]
+; GFX7-GI-NEXT: s_or_b64 s[14:15], vcc, vcc
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_readfirstlane_b32 s14, v2
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v2, s19
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[12:13], -1, s[12:13]
+; GFX7-GI-NEXT: s_or_b64 s[16:17], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v3, v1
+; GFX7-GI-NEXT: v_trunc_f32_e32 v3, v2
+; GFX7-GI-NEXT: v_readfirstlane_b32 s15, v4
+; GFX7-GI-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
+; GFX7-GI-NEXT: v_floor_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_fma_f32 v3, v4, v0, v3
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[14:15], 0, s[14:15]
+; GFX7-GI-NEXT: s_or_b64 s[16:17], vcc, vcc
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_readfirstlane_b32 s16, v3
+; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v3, s20
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v2
+; GFX7-GI-NEXT: s_cselect_b64 s[14:15], -1, s[14:15]
+; GFX7-GI-NEXT: s_or_b64 s[18:19], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v2, v1
+; GFX7-GI-NEXT: v_trunc_f32_e32 v2, v3
+; GFX7-GI-NEXT: v_readfirstlane_b32 s17, v4
+; GFX7-GI-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
+; GFX7-GI-NEXT: v_floor_f32_e32 v4, v4
+; GFX7-GI-NEXT: v_fma_f32 v0, v4, v0, v2
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v4
; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v8, v1
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v10, v3
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v12, v5
-; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v14, v7
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v3, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v7, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v9, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v11, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v13, 0
-; GFX7-GI-NEXT: v_mov_b32_e32 v15, 0
+; GFX7-GI-NEXT: s_cselect_b64 s[16:17], 0, s[16:17]
+; GFX7-GI-NEXT: s_or_b64 s[18:19], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v3
+; GFX7-GI-NEXT: s_cselect_b64 s[16:17], -1, s[16:17]
+; GFX7-GI-NEXT: v_readfirstlane_b32 s19, v2
+; GFX7-GI-NEXT: v_readfirstlane_b32 s18, v0
+; GFX7-GI-NEXT: s_or_b64 s[20:21], vcc, vcc
+; GFX7-GI-NEXT: v_cmp_gt_f32_e32 vcc, v3, v1
+; GFX7-GI-NEXT: s_cselect_b64 s[18:19], 0, s[18:19]
+; GFX7-GI-NEXT: s_or_b64 s[20:21], vcc, vcc
+; GFX7-GI-NEXT: s_cselect_b64 s[18:19], -1, s[18:19]
+; GFX7-GI-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-GI-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-GI-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-GI-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-GI-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-GI-NEXT: v_mov_b32_e32 v6, s10
+; GFX7-GI-NEXT: v_mov_b32_e32 v7, s11
+; GFX7-GI-NEXT: v_mov_b32_e32 v8, s12
+; GFX7-GI-NEXT: v_mov_b32_e32 v9, s13
+; GFX7-GI-NEXT: v_mov_b32_e32 v10, s14
+; GFX7-GI-NEXT: v_mov_b32_e32 v11, s15
+; GFX7-GI-NEXT: v_mov_b32_e32 v12, s16
+; GFX7-GI-NEXT: v_mov_b32_e32 v13, s17
+; GFX7-GI-NEXT: v_mov_b32_e32 v14, s18
+; GFX7-GI-NEXT: v_mov_b32_e32 v15, s19
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_unsigned_v8f16_v8i64:
@@ -6225,31 +6707,126 @@ define <8 x i64> @test_s_unsigned_v8f16_v8i64(<8 x half> inreg %f) {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: s_cvt_f32_f16 s4, s0
-; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s0, s0
-; GFX12-GI-NEXT: s_cvt_f32_f16 s5, s1
-; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s1, s1
-; GFX12-GI-NEXT: s_cvt_f32_f16 s6, s2
+; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s6, s0
+; GFX12-GI-NEXT: s_cvt_f32_f16 s8, s1
+; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s10, s1
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_trunc_f32 s5, s4
+; GFX12-GI-NEXT: s_trunc_f32 s7, s6
+; GFX12-GI-NEXT: s_cmp_nge_f32 s4, 0
+; GFX12-GI-NEXT: s_trunc_f32 s9, s8
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_mul_f32 s0, s5, 0x2f800000
+; GFX12-GI-NEXT: s_mul_f32 s1, s7, 0x2f800000
+; GFX12-GI-NEXT: s_trunc_f32 s12, s10
+; GFX12-GI-NEXT: s_cvt_f32_f16 s14, s2
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s0, s0
+; GFX12-GI-NEXT: s_floor_f32 s11, s1
; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s2, s2
-; GFX12-GI-NEXT: s_cvt_f32_f16 s7, s3
-; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s3, s3
+; GFX12-GI-NEXT: s_cvt_hi_f32_f16 s17, s3
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: s_cvt_u32_f32 s4, s4
-; GFX12-GI-NEXT: s_cvt_u32_f32 s0, s0
-; GFX12-GI-NEXT: s_cvt_u32_f32 s5, s5
-; GFX12-GI-NEXT: s_cvt_u32_f32 s1, s1
-; GFX12-GI-NEXT: s_cvt_u32_f32 s6, s6
-; GFX12-GI-NEXT: s_cvt_u32_f32 s2, s2
-; GFX12-GI-NEXT: s_cvt_u32_f32 s7, s7
-; GFX12-GI-NEXT: s_cvt_u32_f32 s3, s3
+; GFX12-GI-NEXT: s_fmac_f32 s5, s0, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s1, s0
+; GFX12-GI-NEXT: s_fmac_f32 s7, s11, 0xcf800000
+; GFX12-GI-NEXT: s_trunc_f32 s18, s17
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s0, s5
+; GFX12-GI-NEXT: s_mul_f32 s5, s9, 0x2f800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s4, 0x5f7fffff
+; GFX12-GI-NEXT: s_floor_f32 s13, s5
+; GFX12-GI-NEXT: s_cvt_u32_f32 s5, s11
+; GFX12-GI-NEXT: s_cvt_u32_f32 s4, s7
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[0:1], -1, s[0:1]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s6, 0
+; GFX12-GI-NEXT: s_mul_f32 s7, s12, 0x2f800000
+; GFX12-GI-NEXT: s_fmac_f32 s9, s13, 0xcf800000
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GI-NEXT: s_cselect_b64 s[4:5], 0, s[4:5]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s6, 0x5f7fffff
+; GFX12-GI-NEXT: s_floor_f32 s11, s7
+; GFX12-GI-NEXT: s_cvt_u32_f32 s7, s13
+; GFX12-GI-NEXT: s_cvt_u32_f32 s6, s9
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[4:5], -1, s[4:5]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s8, 0
+; GFX12-GI-NEXT: s_trunc_f32 s13, s14
+; GFX12-GI-NEXT: s_fmac_f32 s12, s11, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s9, s11
+; GFX12-GI-NEXT: s_cselect_b64 s[6:7], 0, s[6:7]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s8, 0x5f7fffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_mul_f32 s15, s13, 0x2f800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s8, s12
+; GFX12-GI-NEXT: s_trunc_f32 s12, s2
+; GFX12-GI-NEXT: s_cselect_b64 s[6:7], -1, s[6:7]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s10, 0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s11, s15
+; GFX12-GI-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
+; GFX12-GI-NEXT: s_cselect_b64 s[8:9], 0, s[8:9]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s10, 0x5f7fffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s13, s11, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s11, s11
+; GFX12-GI-NEXT: v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s7
+; GFX12-GI-NEXT: s_cselect_b64 s[8:9], -1, s[8:9]
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s10, s13
+; GFX12-GI-NEXT: s_cmp_nge_f32 s14, 0
+; GFX12-GI-NEXT: s_mul_f32 s13, s12, 0x2f800000
+; GFX12-GI-NEXT: v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[10:11], 0, s[10:11]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s14, 0x5f7fffff
+; GFX12-GI-NEXT: s_cvt_f32_f16 s14, s3
+; GFX12-GI-NEXT: s_floor_f32 s13, s13
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[10:11], -1, s[10:11]
+; GFX12-GI-NEXT: s_trunc_f32 s15, s14
+; GFX12-GI-NEXT: s_fmac_f32 s12, s13, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s13, s13
+; GFX12-GI-NEXT: s_cmp_nge_f32 s2, 0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_mul_f32 s16, s15, 0x2f800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s12, s12
+; GFX12-GI-NEXT: v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, s11
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s16, s16
+; GFX12-GI-NEXT: s_cselect_b64 s[12:13], 0, s[12:13]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s2, 0x5f7fffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s15, s16, 0xcf800000
+; GFX12-GI-NEXT: s_cselect_b64 s[2:3], -1, s[12:13]
+; GFX12-GI-NEXT: s_cvt_u32_f32 s13, s16
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s12, s15
+; GFX12-GI-NEXT: s_mul_f32 s15, s18, 0x2f800000
+; GFX12-GI-NEXT: s_cmp_nge_f32 s14, 0
+; GFX12-GI-NEXT: v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_floor_f32 s15, s15
+; GFX12-GI-NEXT: s_cselect_b64 s[12:13], 0, s[12:13]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s14, 0x5f7fffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_fmac_f32 s18, s15, 0xcf800000
+; GFX12-GI-NEXT: s_cvt_u32_f32 s15, s15
+; GFX12-GI-NEXT: s_cselect_b64 s[12:13], -1, s[12:13]
+; GFX12-GI-NEXT: s_cmp_nge_f32 s17, 0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cvt_u32_f32 s14, s18
+; GFX12-GI-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[14:15], 0, s[14:15]
+; GFX12-GI-NEXT: s_cmp_gt_f32 s17, 0x5f7fffff
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_cselect_b64 s[14:15], -1, s[14:15]
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v6, s1 :: v_dual_mov_b32 v7, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v12, s7 :: v_dual_mov_b32 v13, 0
-; GFX12-GI-NEXT: v_dual_mov_b32 v14, s3 :: v_dual_mov_b32 v15, 0
+; GFX12-GI-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <8 x i64> @llvm.fptoui.sat.v8f16.v8i64(<8 x half> %f)
ret <8 x i64> %x
>From 9aed6744f01ad0b80b581d2316da473f7869e0c4 Mon Sep 17 00:00:00 2001
From: Nathaniel McCallum <nathaniel at mccallum.life>
Date: Sun, 9 Aug 2026 13:26:25 -0400
Subject: [PATCH 3/7] [AMDGPU] Fix saturation width in LowerFP_TO_INT_SAT
For an i64 destination with a 16-bit float source, the lowering built a node
with an i64 result type but an i32 saturation width. That representation is
legal -- integer type legalization relies on it -- but it does not mean the
same thing as the original conversion: it saturates to the bounds of an i32
and then extends, so values outside the range of an i32 come out wrong.
fptosi.sat.i64.f16(inf) gave the largest i32, expected the largest i64
For bfloat this is not confined to infinities. bfloat has the exponent range of
f32, so ordinary finite values that fit in an i64 were clamped to the largest
i32.
Remove the shortcut and let the generic expansion handle these.
---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 9 -
llvm/test/CodeGen/AMDGPU/bf16-conversions.ll | 98 +-
llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll | 260 +-
llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll | 3227 +++++++++++++++--
llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll | 146 +-
llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll | 1846 ++++++++--
6 files changed, 4767 insertions(+), 819 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 962988ff97e39..5de9b6cbcd5a0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -3935,15 +3935,6 @@ SDValue AMDGPUTargetLowering::LowerFP_TO_INT_SAT(const SDValue Op,
// SatWidth == DstWidth or SatWidth > 32
- // Saturate at i32 for i64 dst and f16/bf16 src (will invoke f16 promotion
- // below)
- if (DstVT == MVT::i64 &&
- (SrcVT == MVT::f16 || SrcVT == MVT::bf16 ||
- (SrcVT == MVT::f32 && Src.getOpcode() == ISD::FP16_TO_FP))) {
- const SDValue Int32VTOp = DAG.getValueType(MVT::i32);
- return DAG.getNode(OpOpcode, DL, DstVT, Src, Int32VTOp);
- }
-
// Promote f16/bf16 src to f32 for i32 conversion
if (DstVT == MVT::i32 && (SrcVT == MVT::f16 || SrcVT == MVT::bf16)) {
SDValue PromotedSrc = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
diff --git a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
index d90541243c26e..ca4498cd1ce5a 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
@@ -673,26 +673,72 @@ entry:
ret void
}
-; FIXME: These record incorrect results. The conversion is performed at i32 and
-; then extended, so a finite bfloat that fits in an i64 but not an i32 saturates
-; to i32::MAX rather than converting exactly.
define i64 @v_test_bf16_to_i64_sat(bfloat %x) {
; GCN-LABEL: v_test_bf16_to_i64_sat:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GCN-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: v_trunc_f32_e32 v1, v0
+; GCN-NEXT: s_mov_b32 s0, 0x2f800000
+; GCN-NEXT: v_mul_f32_e64 v2, |v1|, s0
+; GCN-NEXT: v_floor_f32_e32 v2, v2
+; GCN-NEXT: s_mov_b32 s0, 0xcf800000
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GCN-NEXT: v_fma_f32 v2, v2, s0, |v1|
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v1
+; GCN-NEXT: v_xor_b32_e32 v3, v3, v1
+; GCN-NEXT: s_mov_b32 s0, 0xdf000000
+; GCN-NEXT: v_xor_b32_e32 v2, v2, v1
+; GCN-NEXT: v_sub_co_u32_e32 v2, vcc, v2, v1
+; GCN-NEXT: v_cmp_u_f32_e64 s[2:3], v0, v0
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: v_subb_co_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT: v_cmp_nle_f32_e32 vcc, s0, v0
+; GCN-NEXT: s_mov_b32 s0, 0x5effffff
+; GCN-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, v0
+; GCN-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, s[2:3]
+; GCN-NEXT: v_bfrev_b32_e32 v2, 1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GCN-NEXT: v_bfrev_b32_e32 v2, -2
+; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[2:3]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_test_bf16_to_i64_sat:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1250-NEXT: v_lshlrev_b32_e32 v4, 16, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_trunc_f32_e32 v0, v4
+; GFX1250-NEXT: v_mul_f32_e64 v1, 0x2f800000, |v0|
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX1250-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX1250-NEXT: v_floor_f32_e32 v1, v1
+; GFX1250-NEXT: v_fma_f32 v2, 0xcf800000, v1, |v0|
+; GFX1250-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v3, v1
+; GFX1250-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v4
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX1250-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_bitop2_b32 v3, v3, v0 bitop3:0x14
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_xor_b32_e32 v2, v2, v0
+; GFX1250-NEXT: v_sub_nc_u64_e32 v[0:1], v[2:3], v[0:1]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo
+; GFX1250-NEXT: v_cndmask_b32_e64 v1, v1, 0x80000000, vcc_lo
+; GFX1250-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v4
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc_lo
+; GFX1250-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fffffff, vcc_lo
+; GFX1250-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo
+; GFX1250-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%r = call i64 @llvm.fptosi.sat.i64.bf16(bfloat %x)
ret i64 %r
@@ -703,17 +749,43 @@ define i64 @v_test_bf16_to_u64_sat(bfloat %x) {
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: v_trunc_f32_e32 v1, v0
+; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
+; GCN-NEXT: v_floor_f32_e32 v2, v2
+; GCN-NEXT: v_fmamk_f32 v1, v2, 0xcf800000, v1
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
+; GCN-NEXT: v_cmp_nle_f32_e32 vcc, 0, v0
+; GCN-NEXT: s_mov_b32 s0, 0x5f7fffff
+; GCN-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, v0
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v1, v1, -1, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[0:1]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_test_bf16_to_u64_sat:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_trunc_f32_e32 v1, v0
+; GFX1250-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_floor_f32_e32 v2, v2
+; GFX1250-NEXT: v_fmamk_f32 v1, v2, 0xcf800000, v1
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX1250-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_cndmask_b32_e64 v3, v1, 0, vcc_lo
+; GFX1250-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v0
+; GFX1250-NEXT: v_cndmask_b32_e64 v1, v2, -1, vcc_lo
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, v3, -1, vcc_lo
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%r = call i64 @llvm.fptoui.sat.i64.bf16(bfloat %x)
ret i64 %r
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
index 3be429ea7dadc..65dc2bf68d28b 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
@@ -1949,8 +1949,21 @@ define i64 @test_signed_i64_f16(half %f) nounwind {
; GFX7-ISEL: ; %bb.0:
; GFX7-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX7-ISEL-NEXT: s_mov_b32 s4, 0xdf000000
+; GFX7-ISEL-NEXT: s_mov_b32 s5, 0x5effffff
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v1, v0
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s4, v0
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s5, v0
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v1, 1
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v2, -2
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[6:7]
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_signed_i64_f16:
@@ -1989,24 +2002,84 @@ define i64 @test_signed_i64_f16(half %f) nounwind {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX9-NEXT: s_mov_b32 s4, 0x2f800000
+; GFX9-NEXT: s_mov_b32 s5, 0xcf800000
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mul_f32_e64 v2, |v1|, s4
+; GFX9-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GFX9-NEXT: v_fma_f32 v2, v2, s5, |v1|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v1
+; GFX9-NEXT: v_xor_b32_e32 v3, v3, v1
+; GFX9-NEXT: s_mov_b32 s4, 0xdf000000
+; GFX9-NEXT: v_xor_b32_e32 v2, v2, v1
+; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, v2, v1
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v3, v1, vcc
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s4, v0
+; GFX9-NEXT: s_mov_b32 s4, 0x5effffff
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s4, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, s[6:7]
+; GFX9-NEXT: v_bfrev_b32_e32 v2, 1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT: v_bfrev_b32_e32 v2, -2
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[6:7]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_signed_i64_f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-FAKE16-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: v_fma_f32 v3, 0xcf800000, v2, |v1|
+; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v1, 31, v1
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, v2, v1
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v3, v3, v1
+; GFX11-FAKE16-NEXT: v_sub_co_u32 v3, vcc_lo, v3, v1
+; GFX11-FAKE16-NEXT: v_sub_co_ci_u32_e64 v1, null, v2, v1, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v3, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x80000000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fffffff, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: test_signed_i64_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-TRUE16-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: v_fma_f32 v3, 0xcf800000, v2, |v1|
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v1
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v2, v2, v1
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v3, v3, v1
+; GFX11-TRUE16-NEXT: v_sub_co_u32 v3, vcc_lo, v3, v1
+; GFX11-TRUE16-NEXT: v_sub_co_ci_u32_e64 v1, null, v2, v1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v3, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x80000000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fffffff, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_signed_i64_f16:
@@ -2017,8 +2090,30 @@ define i64 @test_signed_i64_f16(half %f) nounwind {
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v1, v0
+; GFX12-FAKE16-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v2, v2
+; GFX12-FAKE16-NEXT: v_fma_f32 v3, 0xcf800000, v2, |v1|
+; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v1, 31, v1
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v2, v2, v1
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v3, v3, v1
+; GFX12-FAKE16-NEXT: v_sub_co_u32 v3, vcc_lo, v3, v1
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_sub_co_ci_u32_e64 v1, null, v2, v1, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v3, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x80000000, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc_lo
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fffffff, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_signed_i64_f16:
@@ -2029,8 +2124,30 @@ define i64 @test_signed_i64_f16(half %f) nounwind {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v1, v0
+; GFX12-TRUE16-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v2, v2
+; GFX12-TRUE16-NEXT: v_fma_f32 v3, 0xcf800000, v2, |v1|
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v1
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v2, v2, v1
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v3, v3, v1
+; GFX12-TRUE16-NEXT: v_sub_co_u32 v3, vcc_lo, v3, v1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_sub_co_ci_u32_e64 v1, null, v2, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, v3, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x80000000, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fffffff, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_i64_f16:
@@ -2378,8 +2495,21 @@ define i64 @test_s_signed_i64_f16(half inreg %f) nounwind {
; GFX7-ISEL: ; %bb.0:
; GFX7-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v0, s16
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX7-ISEL-NEXT: s_mov_b32 s4, 0xdf000000
+; GFX7-ISEL-NEXT: s_mov_b32 s5, 0x5effffff
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v1, v0
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s4, v0
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s5, v0
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v1, 1
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v2, -2
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[6:7]
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_s_signed_i64_f16:
@@ -2425,16 +2555,77 @@ define i64 @test_s_signed_i64_f16(half inreg %f) nounwind {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s16
-; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX9-NEXT: s_mov_b32 s4, 0x2f800000
+; GFX9-NEXT: s_mov_b32 s5, 0xcf800000
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mul_f32_e64 v2, |v1|, s4
+; GFX9-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GFX9-NEXT: v_fma_f32 v2, v2, s5, |v1|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s4, v1
+; GFX9-NEXT: s_ashr_i32 s4, s4, 31
+; GFX9-NEXT: v_readfirstlane_b32 s7, v3
+; GFX9-NEXT: v_readfirstlane_b32 s6, v2
+; GFX9-NEXT: s_mov_b32 s5, s4
+; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]
+; GFX9-NEXT: s_sub_u32 s6, s6, s4
+; GFX9-NEXT: s_subb_u32 s10, s7, s4
+; GFX9-NEXT: s_mov_b32 s4, 0xdf000000
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s4, v0
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_mov_b32 s4, 0x5effffff
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s4, v0
+; GFX9-NEXT: s_cselect_b32 s8, 0, s6
+; GFX9-NEXT: s_and_b64 s[6:7], s[4:5], exec
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX9-NEXT: s_cselect_b32 s11, -1, s8
+; GFX9-NEXT: s_and_b64 s[8:9], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s11, 0, s11
+; GFX9-NEXT: s_and_b64 s[8:9], vcc, exec
+; GFX9-NEXT: s_cselect_b32 s8, 0x80000000, s10
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX9-NEXT: s_cselect_b32 s8, 0x7fffffff, s8
+; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s4, 0, s8
+; GFX9-NEXT: v_mov_b32_e32 v0, s11
+; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_signed_i64_f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s0
-; GFX11-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX11-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX11-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX11-NEXT: v_cmp_u_f32_e64 s1, v0, v0
+; GFX11-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX11-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11-NEXT: v_floor_f32_e32 v2, v2
+; GFX11-NEXT: s_ashr_i32 s4, s0, 31
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v0
+; GFX11-NEXT: s_mov_b32 s5, s4
+; GFX11-NEXT: v_fma_f32 v3, 0xcf800000, v2, |v1|
+; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-NEXT: v_readfirstlane_b32 s3, v2
+; GFX11-NEXT: v_readfirstlane_b32 s2, v3
+; GFX11-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
+; GFX11-NEXT: s_sub_u32 s2, s2, s4
+; GFX11-NEXT: s_subb_u32 s3, s3, s4
+; GFX11-NEXT: s_and_b32 s4, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 0, s2
+; GFX11-NEXT: s_and_b32 s4, s0, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, -1, s2
+; GFX11-NEXT: s_and_b32 s4, s1, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 0, s2
+; GFX11-NEXT: s_and_b32 s4, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s3, 0x80000000, s3
+; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-NEXT: s_cselect_b32 s0, 0x7fffffff, s3
+; GFX11-NEXT: s_and_b32 s1, s1, exec_lo
+; GFX11-NEXT: s_cselect_b32 s0, 0, s0
+; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_signed_i64_f16:
@@ -2444,11 +2635,38 @@ define i64 @test_s_signed_i64_f16(half inreg %f) nounwind {
; GFX12-ISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-ISEL-NEXT: s_cvt_f32_f16 s0, s0
+; GFX12-ISEL-NEXT: s_cvt_f32_f16 s4, s0
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s0, s0
+; GFX12-ISEL-NEXT: s_trunc_f32 s0, s4
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_and_b32 s1, s0, 0x7fffffff
+; GFX12-ISEL-NEXT: s_ashr_i32 s0, s0, 31
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_mul_f32 s2, s1, 0x2f800000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_floor_f32 s2, s2
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s1, s2, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s3, s2
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s2, s1
+; GFX12-ISEL-NEXT: s_mov_b32 s1, s0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1]
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s4, 0xdf000000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_sub_nc_u64 s[0:1], s[2:3], s[0:1]
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s0, 0, s0
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, 0x80000000, s1
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s4, 0x5effffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, 0x7fffffff, s1
+; GFX12-ISEL-NEXT: s_cselect_b32 s0, -1, s0
+; GFX12-ISEL-NEXT: s_cmp_u_f32 s4, s4
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: s_ashr_i32 s1, s0, 31
+; GFX12-ISEL-NEXT: s_cselect_b32 s0, 0, s0
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, 0, s1
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
index 23afc452b40c6..88064f54b4f8f 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
@@ -3127,20 +3127,60 @@ define <4 x i64> @test_signed_v4f16_v4i64(<4 x half> %f) {
; GFX7-ISEL-LABEL: test_signed_v4f16_v4i64:
; GFX7-ISEL: ; %bb.0:
; GFX7-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v4, v2
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX7-ISEL-NEXT: s_mov_b32 s8, 0xdf000000
+; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX7-ISEL-NEXT: s_mov_b32 s9, 0x5effffff
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v3, v2
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s8, v2
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s9, v2
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v2, v2
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v5, 31, v3
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0, vcc
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v7, 1
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v9, v4
; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v6, v4
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v4, v1
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc
+; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v8, -2
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s8, v3
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v6, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[4:5]
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v5, 31, v2
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s9, v3
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v3, v3
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v4, v2, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v2, v9
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, v8, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v5, v3, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s8, v9
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s9, v9
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v9, v9
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v9, v6
; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v10, 31, v9
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s8, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, v8, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s9, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v9, v9, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v6, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v6, v9, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v7, v7, 0, s[6:7]
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_signed_v4f16_v4i64:
@@ -3244,56 +3284,280 @@ define <4 x i64> @test_signed_v4f16_v4i64(<4 x half> %f) {
; GFX9-LABEL: test_signed_v4f16_v4i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX9-NEXT: v_cvt_i32_f32_e32 v6, v3
-; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX9-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX9-NEXT: s_mov_b32 s8, 0x2f800000
+; GFX9-NEXT: s_mov_b32 s9, 0xcf800000
+; GFX9-NEXT: s_mov_b32 s10, 0xdf000000
+; GFX9-NEXT: v_trunc_f32_e32 v3, v2
+; GFX9-NEXT: v_mul_f32_e64 v4, |v3|, s8
+; GFX9-NEXT: v_floor_f32_e32 v4, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v4
+; GFX9-NEXT: v_fma_f32 v4, v4, s9, |v3|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v3
+; GFX9-NEXT: v_xor_b32_e32 v5, v5, v3
+; GFX9-NEXT: s_mov_b32 s11, 0x5effffff
+; GFX9-NEXT: v_xor_b32_e32 v4, v4, v3
+; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v4, v3
+; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v5, v3, vcc
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s10, v2
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s11, v2
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v2, v2
+; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v4, 0, s[6:7]
+; GFX9-NEXT: v_trunc_f32_e32 v4, v2
+; GFX9-NEXT: v_mul_f32_e64 v5, |v4|, s8
+; GFX9-NEXT: v_floor_f32_e32 v5, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v5
+; GFX9-NEXT: v_fma_f32 v5, v5, s9, |v4|
+; GFX9-NEXT: v_bfrev_b32_e32 v7, 1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX9-NEXT: v_bfrev_b32_e32 v10, -2
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v10, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v3, 0, s[6:7]
+; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v4
+; GFX9-NEXT: v_xor_b32_e32 v5, v5, v3
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_xor_b32_e32 v4, v6, v3
+; GFX9-NEXT: v_sub_co_u32_e32 v5, vcc, v5, v3
+; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v4, v3, vcc
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s10, v2
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s11, v2
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v2, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc
+; GFX9-NEXT: v_trunc_f32_e32 v3, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v5, 0, vcc
+; GFX9-NEXT: v_mul_f32_e64 v5, |v3|, s8
+; GFX9-NEXT: v_floor_f32_e32 v5, v5
+; GFX9-NEXT: v_fma_f32 v6, v5, s9, |v3|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v11, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v10, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v2, 0, s[6:7]
+; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v3
+; GFX9-NEXT: v_xor_b32_e32 v6, v6, v2
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_xor_b32_e32 v3, v11, v2
+; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, v6, v2
+; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v2, vcc
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s10, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
+; GFX9-NEXT: v_trunc_f32_e32 v6, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[6:7]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s11, v0
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc
+; GFX9-NEXT: v_mul_f32_e64 v3, |v6|, s8
+; GFX9-NEXT: v_floor_f32_e32 v3, v3
+; GFX9-NEXT: v_fma_f32 v11, v3, s9, |v6|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GFX9-NEXT: v_cvt_u32_f32_e32 v12, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v10, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[6:7]
+; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v6
+; GFX9-NEXT: v_xor_b32_e32 v11, v11, v0
+; GFX9-NEXT: v_xor_b32_e32 v6, v12, v0
+; GFX9-NEXT: v_sub_co_u32_e32 v11, vcc, v11, v0
+; GFX9-NEXT: v_subb_co_u32_e32 v0, vcc, v6, v0, vcc
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s10, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v11, 0, vcc
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s11, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, -1, s[4:5]
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v1, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v10, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v0, 0, s[6:7]
+; GFX9-NEXT: v_mov_b32_e32 v0, v8
+; GFX9-NEXT: v_mov_b32_e32 v1, v9
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_signed_v4f16_v4i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v6, v3
-; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v4, v2
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v3
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v2, v2
+; GFX11-FAKE16-NEXT: v_mul_f32_e64 v0, 0x2f800000, |v4|
+; GFX11-FAKE16-NEXT: v_mul_f32_e64 v8, 0x2f800000, |v5|
+; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v1, 31, v4
+; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v11, 31, v5
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v6
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v8, v8
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v10, v7
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, 0x5effffff, v6
+; GFX11-FAKE16-NEXT: v_mul_f32_e64 v12, 0x2f800000, |v9|
+; GFX11-FAKE16-NEXT: v_fma_f32 v4, 0xcf800000, v0, |v4|
+; GFX11-FAKE16-NEXT: v_fma_f32 v5, 0xcf800000, v8, |v5|
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX11-FAKE16-NEXT: v_mul_f32_e64 v13, 0x2f800000, |v10|
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v8, v8, v11
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v12, v12
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v4, v4, v1
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v5, v5, v11
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v13, v13
+; GFX11-FAKE16-NEXT: v_fma_f32 v14, 0xcf800000, v12, |v9|
+; GFX11-FAKE16-NEXT: v_sub_co_u32 v4, vcc_lo, v4, v1
+; GFX11-FAKE16-NEXT: v_sub_co_ci_u32_e64 v0, null, v0, v1, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v2
+; GFX11-FAKE16-NEXT: v_sub_co_u32 v1, s0, v5, v11
+; GFX11-FAKE16-NEXT: v_sub_co_ci_u32_e64 v5, null, v8, v11, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x80000000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v3
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v2
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v14, v14
+; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v9, 31, v9
+; GFX11-FAKE16-NEXT: v_fma_f32 v11, 0xcf800000, v13, |v10|
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, 0x80000000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fffffff, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, -1, s0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
+; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v10, 31, v10
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v1, -1, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v2, 0, s1
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v2, v12
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v4, 0, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v5, 0x7fffffff, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v8, 0, s0
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v5, v14, v9
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v8, v11
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, v2, v9
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v11, v13
+; GFX11-FAKE16-NEXT: v_sub_co_u32 v5, vcc_lo, v5, v9
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v8, v8, v10
+; GFX11-FAKE16-NEXT: v_sub_co_ci_u32_e64 v2, null, v2, v9, vcc_lo
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v9, v11, v10
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v6
+; GFX11-FAKE16-NEXT: v_sub_co_u32 v8, s1, v8, v10
+; GFX11-FAKE16-NEXT: v_sub_co_ci_u32_e64 v9, null, v9, v10, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e64 s1, 0xdf000000, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, 0x80000000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, v5, -1, s2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v8, 0, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v9, 0x80000000, s1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, v2, 0x7fffffff, s2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, v5, -1, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v8, 0x7fffffff, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v3, 0, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v10, 0, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v6, 0, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, v9, 0, s2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, 0, s2
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: test_signed_v4f16_v4i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v6, v3
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v4, v2
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v3
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v2, v2
+; GFX11-TRUE16-NEXT: v_mul_f32_e64 v0, 0x2f800000, |v4|
+; GFX11-TRUE16-NEXT: v_mul_f32_e64 v8, 0x2f800000, |v5|
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v4
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v11, 31, v5
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v6
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v8, v8
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v10, v7
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, 0x5effffff, v6
+; GFX11-TRUE16-NEXT: v_mul_f32_e64 v12, 0x2f800000, |v9|
+; GFX11-TRUE16-NEXT: v_fma_f32 v4, 0xcf800000, v0, |v4|
+; GFX11-TRUE16-NEXT: v_fma_f32 v5, 0xcf800000, v8, |v5|
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX11-TRUE16-NEXT: v_mul_f32_e64 v13, 0x2f800000, |v10|
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v8, v8, v11
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v12, v12
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v4, v4, v1
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v5, v5, v11
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v13, v13
+; GFX11-TRUE16-NEXT: v_fma_f32 v14, 0xcf800000, v12, |v9|
+; GFX11-TRUE16-NEXT: v_sub_co_u32 v4, vcc_lo, v4, v1
+; GFX11-TRUE16-NEXT: v_sub_co_ci_u32_e64 v0, null, v0, v1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v2
+; GFX11-TRUE16-NEXT: v_sub_co_u32 v1, s0, v5, v11
+; GFX11-TRUE16-NEXT: v_sub_co_ci_u32_e64 v5, null, v8, v11, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x80000000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v3
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v2
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v14, v14
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v9, 31, v9
+; GFX11-TRUE16-NEXT: v_fma_f32 v11, 0xcf800000, v13, |v10|
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v5, 0x80000000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fffffff, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, v4, -1, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v10, 31, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, v1, -1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v2, 0, s1
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v4, 0, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, v5, 0x7fffffff, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, v8, 0, s0
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v5, v14, v9
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v11
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v2, v2, v9
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v11, v13
+; GFX11-TRUE16-NEXT: v_sub_co_u32 v5, vcc_lo, v5, v9
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v8, v8, v10
+; GFX11-TRUE16-NEXT: v_sub_co_ci_u32_e64 v2, null, v2, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v9, v11, v10
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v6
+; GFX11-TRUE16-NEXT: v_sub_co_u32 v8, s1, v8, v10
+; GFX11-TRUE16-NEXT: v_sub_co_ci_u32_e64 v9, null, v9, v10, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e64 s1, 0xdf000000, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, 0x80000000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, v5, -1, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v8, 0, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, v9, 0x80000000, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v2, 0x7fffffff, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, v5, -1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, v8, 0x7fffffff, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v3, 0, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v10, 0, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, v6, 0, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v9, 0, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, v7, 0, s2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_signed_v4f16_v4i64:
@@ -3303,20 +3567,105 @@ define <4 x i64> @test_signed_v4f16_v4i64(<4 x half> %f) {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v6, v3
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v4, v2
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v5, v3
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v0
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v1
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v2, v2
+; GFX12-FAKE16-NEXT: v_mul_f32_e64 v0, 0x2f800000, |v4|
+; GFX12-FAKE16-NEXT: v_mul_f32_e64 v8, 0x2f800000, |v5|
+; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v1, 31, v4
+; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v11, 31, v5
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v9, v6
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v0, v0
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v8, v8
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v10, v7
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, 0x5effffff, v6
+; GFX12-FAKE16-NEXT: v_mul_f32_e64 v12, 0x2f800000, |v9|
+; GFX12-FAKE16-NEXT: v_fma_f32 v4, 0xcf800000, v0, |v4|
+; GFX12-FAKE16-NEXT: v_fma_f32 v5, 0xcf800000, v8, |v5|
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX12-FAKE16-NEXT: v_mul_f32_e64 v13, 0x2f800000, |v10|
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v8, v8, v11
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v12, v12
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v4, v4, v1
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v5, v5, v11
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v13, v13
+; GFX12-FAKE16-NEXT: v_fma_f32 v14, 0xcf800000, v12, |v9|
+; GFX12-FAKE16-NEXT: v_sub_co_u32 v4, vcc_lo, v4, v1
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_sub_co_ci_u32_e64 v0, null, v0, v1, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v2
+; GFX12-FAKE16-NEXT: v_sub_co_u32 v1, s0, v5, v11
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_sub_co_ci_u32_e64 v5, null, v8, v11, s0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x80000000, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v3
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v2
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v14, v14
+; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v9, 31, v9
+; GFX12-FAKE16-NEXT: v_fma_f32 v11, 0xcf800000, v13, |v10|
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, 0x80000000, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v3
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fffffff, s0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, -1, s0
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
+; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v10, 31, v10
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v1, -1, vcc_lo
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v2, 0, s1
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v2, v12
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v4, 0, s1
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v5, 0x7fffffff, vcc_lo
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v8, 0, s0
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v5, v14, v9
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v8, v11
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v2, v2, v9
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v11, v13
+; GFX12-FAKE16-NEXT: v_sub_co_u32 v5, vcc_lo, v5, v9
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v8, v8, v10
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_sub_co_ci_u32_e64 v2, null, v2, v9, vcc_lo
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v9, v11, v10
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v6
+; GFX12-FAKE16-NEXT: v_sub_co_u32 v8, s1, v8, v10
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_sub_co_ci_u32_e64 v9, null, v9, v10, s1
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e64 s1, 0xdf000000, v7
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, 0x80000000, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v7
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v10, v5, -1, s2
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v5, v8, 0, s1
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v9, 0x80000000, s1
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v6, v2, 0x7fffffff, s2
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v9, v5, -1, vcc_lo
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v7, v8, 0x7fffffff, vcc_lo
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v5, v3, 0, s0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v10, 0, s1
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v6, 0, s1
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v6, v9, 0, s2
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, 0, s2
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_signed_v4f16_v4i64:
@@ -3326,20 +3675,105 @@ define <4 x i64> @test_signed_v4f16_v4i64(<4 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v6, v3
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v1.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v4, v2
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v5, v3
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v0.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v2, v2
+; GFX12-TRUE16-NEXT: v_mul_f32_e64 v0, 0x2f800000, |v4|
+; GFX12-TRUE16-NEXT: v_mul_f32_e64 v8, 0x2f800000, |v5|
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v4
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v11, 31, v5
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v9, v6
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v0, v0
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v8, v8
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v10, v7
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, 0x5effffff, v6
+; GFX12-TRUE16-NEXT: v_mul_f32_e64 v12, 0x2f800000, |v9|
+; GFX12-TRUE16-NEXT: v_fma_f32 v4, 0xcf800000, v0, |v4|
+; GFX12-TRUE16-NEXT: v_fma_f32 v5, 0xcf800000, v8, |v5|
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX12-TRUE16-NEXT: v_mul_f32_e64 v13, 0x2f800000, |v10|
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v8, v8, v11
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v12, v12
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v4, v4, v1
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v5, v5, v11
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v13, v13
+; GFX12-TRUE16-NEXT: v_fma_f32 v14, 0xcf800000, v12, |v9|
+; GFX12-TRUE16-NEXT: v_sub_co_u32 v4, vcc_lo, v4, v1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_sub_co_ci_u32_e64 v0, null, v0, v1, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v2
+; GFX12-TRUE16-NEXT: v_sub_co_u32 v1, s0, v5, v11
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_sub_co_ci_u32_e64 v5, null, v8, v11, s0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x80000000, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v3
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v2
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v14, v14
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v9, 31, v9
+; GFX12-TRUE16-NEXT: v_fma_f32 v11, 0xcf800000, v13, |v10|
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v5, 0x80000000, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v3
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fffffff, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v4, v4, -1, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v10, 31, v10
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v8, v1, -1, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, v2, 0, s1
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v12
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, v4, 0, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v3, v5, 0x7fffffff, vcc_lo
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v4, v8, 0, s0
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v5, v14, v9
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v11
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v2, v2, v9
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v11, v13
+; GFX12-TRUE16-NEXT: v_sub_co_u32 v5, vcc_lo, v5, v9
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v8, v8, v10
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_sub_co_ci_u32_e64 v2, null, v2, v9, vcc_lo
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v9, v11, v10
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v6
+; GFX12-TRUE16-NEXT: v_sub_co_u32 v8, s1, v8, v10
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_sub_co_ci_u32_e64 v9, null, v9, v10, s1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e64 s1, 0xdf000000, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, 0x80000000, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v10, v5, -1, s2
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v8, 0, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v8, v9, 0x80000000, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v2, 0x7fffffff, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v9, v5, -1, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v7, v8, 0x7fffffff, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v3, 0, s0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, v10, 0, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v3, v6, 0, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v9, 0, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v7, v7, 0, s2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_v4f16_v4i64:
@@ -4099,20 +4533,60 @@ define <4 x i64> @test_s_signed_v4f16_v4i64(<4 x half> inreg %f) {
; GFX7-ISEL-LABEL: test_s_signed_v4f16_v4i64:
; GFX7-ISEL: ; %bb.0:
; GFX7-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-ISEL-NEXT: s_lshr_b32 s4, s17, 16
-; GFX7-ISEL-NEXT: s_lshr_b32 s5, s16, 16
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v0, s5
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v1, s4
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v3, s16
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v4, s17
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v2, v0
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v6, v1
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v0, v3
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v4, v4
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v0, s16
+; GFX7-ISEL-NEXT: s_mov_b32 s8, 0xdf000000
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v3, s17
+; GFX7-ISEL-NEXT: s_mov_b32 s11, 0x5effffff
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v1, v0
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s8, v0
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s11, v0
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v7, 1
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v1, v2, v7, vcc
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
+; GFX7-ISEL-NEXT: s_lshr_b32 s10, s16, 16
+; GFX7-ISEL-NEXT: s_lshr_b32 s9, s17, 16
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v6, s10
+; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v8, -2
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s8, v3
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v9, s9
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[4:5]
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v5, 31, v2
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s11, v3
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v3, v3
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v4, v2, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v2, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, v8, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v5, v3, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s8, v6
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s11, v6
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v6, v6
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v6, v9
; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v10, 31, v6
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s8, v9
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, v8, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s11, v9
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v6, v6, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v9, v9
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v7, v7, 0, s[6:7]
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_s_signed_v4f16_v4i64:
@@ -4237,39 +4711,274 @@ define <4 x i64> @test_s_signed_v4f16_v4i64(<4 x half> inreg %f) {
; GFX9-LABEL: test_s_signed_v4f16_v4i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s16
+; GFX9-NEXT: s_mov_b32 s10, 0x2f800000
+; GFX9-NEXT: s_mov_b32 s11, 0xcf800000
+; GFX9-NEXT: s_mov_b32 s13, 0xdf000000
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mul_f32_e64 v2, |v1|, s10
+; GFX9-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GFX9-NEXT: v_fma_f32 v2, v2, s11, |v1|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s6, v1
+; GFX9-NEXT: s_ashr_i32 s6, s6, 31
+; GFX9-NEXT: v_readfirstlane_b32 s5, v3
+; GFX9-NEXT: v_readfirstlane_b32 s4, v2
+; GFX9-NEXT: s_mov_b32 s7, s6
+; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
+; GFX9-NEXT: s_sub_u32 s7, s4, s6
+; GFX9-NEXT: s_subb_u32 s12, s5, s6
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s13, v0
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_mov_b32 s14, 0x5effffff
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s14, v0
+; GFX9-NEXT: s_cselect_b32 s8, 0, s7
+; GFX9-NEXT: s_and_b64 s[6:7], s[4:5], exec
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s17
+; GFX9-NEXT: s_cselect_b32 s15, -1, s8
+; GFX9-NEXT: s_and_b64 s[8:9], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s15, 0, s15
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mul_f32_e64 v2, |v1|, s10
+; GFX9-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-NEXT: v_fma_f32 v3, v2, s11, |v1|
+; GFX9-NEXT: s_and_b64 s[8:9], vcc, exec
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: s_cselect_b32 s8, 0x80000000, s12
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX9-NEXT: s_cselect_b32 s8, 0x7fffffff, s8
+; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], exec
+; GFX9-NEXT: v_readfirstlane_b32 s6, v1
+; GFX9-NEXT: s_cselect_b32 s12, 0, s8
+; GFX9-NEXT: s_ashr_i32 s6, s6, 31
+; GFX9-NEXT: v_readfirstlane_b32 s4, v3
+; GFX9-NEXT: v_readfirstlane_b32 s5, v2
+; GFX9-NEXT: s_mov_b32 s7, s6
+; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
+; GFX9-NEXT: s_sub_u32 s7, s4, s6
+; GFX9-NEXT: s_subb_u32 s18, s5, s6
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s13, v0
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s14, v0
+; GFX9-NEXT: s_cselect_b32 s8, 0, s7
+; GFX9-NEXT: s_and_b64 s[6:7], s[4:5], exec
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX9-NEXT: s_cselect_b32 s19, -1, s8
+; GFX9-NEXT: s_and_b64 s[8:9], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s19, 0, s19
+; GFX9-NEXT: s_and_b64 s[8:9], vcc, exec
+; GFX9-NEXT: s_cselect_b32 s8, 0x80000000, s18
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX9-NEXT: s_cselect_b32 s8, 0x7fffffff, s8
+; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s18, 0, s8
; GFX9-NEXT: s_lshr_b32 s4, s16, 16
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v4, s19
+; GFX9-NEXT: v_mov_b32_e32 v5, s18
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mul_f32_e64 v2, |v1|, s10
+; GFX9-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-NEXT: v_fma_f32 v3, v2, s11, |v1|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s6, v1
+; GFX9-NEXT: s_ashr_i32 s6, s6, 31
+; GFX9-NEXT: v_readfirstlane_b32 s4, v3
+; GFX9-NEXT: v_readfirstlane_b32 s5, v2
+; GFX9-NEXT: s_mov_b32 s7, s6
+; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
+; GFX9-NEXT: s_sub_u32 s7, s4, s6
+; GFX9-NEXT: s_subb_u32 s16, s5, s6
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s13, v0
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s14, v0
+; GFX9-NEXT: s_cselect_b32 s8, 0, s7
+; GFX9-NEXT: s_and_b64 s[6:7], s[4:5], exec
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX9-NEXT: s_cselect_b32 s20, -1, s8
+; GFX9-NEXT: s_and_b64 s[8:9], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s20, 0, s20
+; GFX9-NEXT: s_and_b64 s[8:9], vcc, exec
+; GFX9-NEXT: s_cselect_b32 s8, 0x80000000, s16
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX9-NEXT: s_cselect_b32 s8, 0x7fffffff, s8
+; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s16, 0, s8
; GFX9-NEXT: s_lshr_b32 s4, s17, 16
-; GFX9-NEXT: v_cvt_f32_f16_e32 v1, s4
-; GFX9-NEXT: v_cvt_f32_f16_e32 v3, s16
-; GFX9-NEXT: v_cvt_f32_f16_e32 v4, s17
-; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v0
-; GFX9-NEXT: v_cvt_i32_f32_e32 v6, v1
-; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v3
-; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v4
-; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX9-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s4
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mul_f32_e64 v2, |v1|, s10
+; GFX9-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-NEXT: v_fma_f32 v3, v2, s11, |v1|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s6, v1
+; GFX9-NEXT: s_ashr_i32 s6, s6, 31
+; GFX9-NEXT: v_readfirstlane_b32 s4, v3
+; GFX9-NEXT: v_readfirstlane_b32 s5, v2
+; GFX9-NEXT: s_mov_b32 s7, s6
+; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
+; GFX9-NEXT: s_sub_u32 s7, s4, s6
+; GFX9-NEXT: s_subb_u32 s10, s5, s6
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s13, v0
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s14, v0
+; GFX9-NEXT: s_cselect_b32 s8, 0, s7
+; GFX9-NEXT: s_and_b64 s[6:7], s[4:5], exec
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX9-NEXT: s_cselect_b32 s11, -1, s8
+; GFX9-NEXT: s_and_b64 s[8:9], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s11, 0, s11
+; GFX9-NEXT: s_and_b64 s[8:9], vcc, exec
+; GFX9-NEXT: s_cselect_b32 s8, 0x80000000, s10
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX9-NEXT: s_cselect_b32 s8, 0x7fffffff, s8
+; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s4, 0, s8
+; GFX9-NEXT: v_mov_b32_e32 v0, s15
+; GFX9-NEXT: v_mov_b32_e32 v1, s12
+; GFX9-NEXT: v_mov_b32_e32 v2, s20
+; GFX9-NEXT: v_mov_b32_e32 v3, s16
+; GFX9-NEXT: v_mov_b32_e32 v6, s11
+; GFX9-NEXT: v_mov_b32_e32 v7, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_signed_v4f16_v4i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-NEXT: s_lshr_b32 s3, s1, 16
; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v1, s1
-; GFX11-NEXT: v_cvt_f32_f16_e32 v2, s2
-; GFX11-NEXT: v_cvt_f32_f16_e32 v3, s3
-; GFX11-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX11-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX11-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX11-NEXT: v_cvt_i32_f32_e32 v6, v3
-; GFX11-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX11-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX11-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX11-NEXT: v_cvt_f32_f16_e32 v2, s1
+; GFX11-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-NEXT: v_trunc_f32_e32 v4, v2
+; GFX11-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX11-NEXT: v_cmp_lt_f32_e64 s2, 0x5effffff, v0
+; GFX11-NEXT: v_cmp_u_f32_e64 s3, v0, v0
+; GFX11-NEXT: v_mul_f32_e64 v3, 0x2f800000, |v1|
+; GFX11-NEXT: v_readfirstlane_b32 s4, v1
+; GFX11-NEXT: v_mul_f32_e64 v5, 0x2f800000, |v4|
+; GFX11-NEXT: v_readfirstlane_b32 s10, v4
+; GFX11-NEXT: v_floor_f32_e32 v3, v3
+; GFX11-NEXT: s_ashr_i32 s4, s4, 31
+; GFX11-NEXT: v_floor_f32_e32 v5, v5
+; GFX11-NEXT: s_mov_b32 s5, s4
+; GFX11-NEXT: v_fma_f32 v6, 0xcf800000, v3, |v1|
+; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v3
+; GFX11-NEXT: v_fma_f32 v3, 0xcf800000, v5, |v4|
+; GFX11-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX11-NEXT: v_cvt_u32_f32_e32 v1, v6
+; GFX11-NEXT: v_readfirstlane_b32 s7, v0
+; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v3
+; GFX11-NEXT: v_readfirstlane_b32 s9, v5
+; GFX11-NEXT: v_readfirstlane_b32 s6, v1
+; GFX11-NEXT: v_readfirstlane_b32 s8, v0
+; GFX11-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]
+; GFX11-NEXT: s_sub_u32 s5, s6, s4
+; GFX11-NEXT: s_subb_u32 s4, s7, s4
+; GFX11-NEXT: s_and_b32 s6, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s5, 0, s5
+; GFX11-NEXT: s_and_b32 s6, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s5, -1, s5
+; GFX11-NEXT: s_and_b32 s6, s3, exec_lo
+; GFX11-NEXT: s_cselect_b32 s11, 0, s5
+; GFX11-NEXT: s_and_b32 s5, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s4, 0x80000000, s4
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 0x7fffffff, s4
+; GFX11-NEXT: s_and_b32 s3, s3, exec_lo
+; GFX11-NEXT: s_cselect_b32 s12, 0, s2
+; GFX11-NEXT: s_ashr_i32 s4, s10, 31
+; GFX11-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v2
+; GFX11-NEXT: s_mov_b32 s5, s4
+; GFX11-NEXT: v_cmp_lt_f32_e64 s2, 0x5effffff, v2
+; GFX11-NEXT: s_xor_b64 s[6:7], s[8:9], s[4:5]
+; GFX11-NEXT: v_cmp_u_f32_e64 s3, v2, v2
+; GFX11-NEXT: s_sub_u32 s5, s6, s4
+; GFX11-NEXT: s_subb_u32 s4, s7, s4
+; GFX11-NEXT: s_and_b32 s6, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s5, 0, s5
+; GFX11-NEXT: s_and_b32 s6, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s5, -1, s5
+; GFX11-NEXT: s_and_b32 s6, s3, exec_lo
+; GFX11-NEXT: s_cselect_b32 s8, 0, s5
+; GFX11-NEXT: s_and_b32 s5, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s4, 0x80000000, s4
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 0x7fffffff, s4
+; GFX11-NEXT: s_and_b32 s3, s3, exec_lo
+; GFX11-NEXT: s_cselect_b32 s9, 0, s2
+; GFX11-NEXT: s_lshr_b32 s0, s0, 16
+; GFX11-NEXT: v_mov_b32_e32 v5, s9
+; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s0
+; GFX11-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX11-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX11-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11-NEXT: v_floor_f32_e32 v2, v2
+; GFX11-NEXT: s_ashr_i32 s4, s0, 31
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v0
+; GFX11-NEXT: s_mov_b32 s5, s4
+; GFX11-NEXT: v_fma_f32 v3, 0xcf800000, v2, |v1|
+; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-NEXT: v_readfirstlane_b32 s3, v2
+; GFX11-NEXT: v_readfirstlane_b32 s2, v3
+; GFX11-NEXT: s_xor_b64 s[6:7], s[2:3], s[4:5]
+; GFX11-NEXT: v_cmp_u_f32_e64 s2, v0, v0
+; GFX11-NEXT: s_sub_u32 s3, s6, s4
+; GFX11-NEXT: s_subb_u32 s4, s7, s4
+; GFX11-NEXT: s_and_b32 s5, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s3, 0, s3
+; GFX11-NEXT: s_and_b32 s5, s0, exec_lo
+; GFX11-NEXT: s_cselect_b32 s3, -1, s3
+; GFX11-NEXT: s_and_b32 s5, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s6, 0, s3
+; GFX11-NEXT: s_and_b32 s3, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s3, 0x80000000, s4
+; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-NEXT: s_cselect_b32 s0, 0x7fffffff, s3
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s7, 0, s0
+; GFX11-NEXT: s_lshr_b32 s0, s1, 16
+; GFX11-NEXT: v_mov_b32_e32 v4, s8
+; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s0
+; GFX11-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX11-NEXT: v_cmp_u_f32_e64 s1, v0, v0
+; GFX11-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX11-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11-NEXT: v_floor_f32_e32 v2, v2
+; GFX11-NEXT: s_ashr_i32 s4, s0, 31
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v0
+; GFX11-NEXT: s_mov_b32 s5, s4
+; GFX11-NEXT: v_mov_b32_e32 v0, s11
+; GFX11-NEXT: v_fma_f32 v3, 0xcf800000, v2, |v1|
+; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX11-NEXT: v_mov_b32_e32 v1, s12
+; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-NEXT: v_readfirstlane_b32 s3, v2
+; GFX11-NEXT: v_mov_b32_e32 v2, s6
+; GFX11-NEXT: v_readfirstlane_b32 s2, v3
+; GFX11-NEXT: v_mov_b32_e32 v3, s7
+; GFX11-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
+; GFX11-NEXT: s_sub_u32 s2, s2, s4
+; GFX11-NEXT: s_subb_u32 s3, s3, s4
+; GFX11-NEXT: s_and_b32 s4, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 0, s2
+; GFX11-NEXT: s_and_b32 s4, s0, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, -1, s2
+; GFX11-NEXT: s_and_b32 s4, s1, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 0, s2
+; GFX11-NEXT: s_and_b32 s4, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s3, 0x80000000, s3
+; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-NEXT: s_cselect_b32 s0, 0x7fffffff, s3
+; GFX11-NEXT: s_and_b32 s1, s1, exec_lo
+; GFX11-NEXT: s_cselect_b32 s0, 0, s0
+; GFX11-NEXT: v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v7, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_signed_v4f16_v4i64:
@@ -4279,25 +4988,134 @@ define <4 x i64> @test_s_signed_v4f16_v4i64(<4 x half> inreg %f) {
; GFX12-ISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s2, s0
-; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s3, s1
+; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s6, s0
+; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s7, s1
; GFX12-ISEL-NEXT: s_cvt_f32_f16 s0, s0
-; GFX12-ISEL-NEXT: s_cvt_f32_f16 s1, s1
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s2, s2
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s3, s3
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s0, s0
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s1, s1
+; GFX12-ISEL-NEXT: s_trunc_f32 s2, s6
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_and_b32 s3, s2, 0x7fffffff
+; GFX12-ISEL-NEXT: s_ashr_i32 s2, s2, 31
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_mul_f32 s4, s3, 0x2f800000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_floor_f32 s4, s4
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s3, s4, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s5, s4
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s4, s3
+; GFX12-ISEL-NEXT: s_mov_b32 s3, s2
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_xor_b64 s[4:5], s[4:5], s[2:3]
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s6, 0xdf000000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_sub_nc_u64 s[2:3], s[4:5], s[2:3]
+; GFX12-ISEL-NEXT: s_trunc_f32 s4, s7
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s2, 0, s2
+; GFX12-ISEL-NEXT: s_cselect_b32 s3, 0x80000000, s3
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s6, 0x5effffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s3, 0x7fffffff, s3
+; GFX12-ISEL-NEXT: s_cselect_b32 s2, -1, s2
+; GFX12-ISEL-NEXT: s_cmp_u_f32 s6, s6
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s6, 0, s2
+; GFX12-ISEL-NEXT: s_cselect_b32 s8, 0, s3
+; GFX12-ISEL-NEXT: s_and_b32 s3, s4, 0x7fffffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s8
+; GFX12-ISEL-NEXT: s_mul_f32 s2, s3, 0x2f800000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_floor_f32 s5, s2
+; GFX12-ISEL-NEXT: s_ashr_i32 s2, s4, 31
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s3, s5, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s5, s5
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s4, s3
+; GFX12-ISEL-NEXT: s_mov_b32 s3, s2
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_xor_b64 s[4:5], s[4:5], s[2:3]
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s7, 0xdf000000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_sub_nc_u64 s[2:3], s[4:5], s[2:3]
+; GFX12-ISEL-NEXT: s_trunc_f32 s4, s0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s2, 0, s2
+; GFX12-ISEL-NEXT: s_cselect_b32 s3, 0x80000000, s3
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s7, 0x5effffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s3, 0x7fffffff, s3
+; GFX12-ISEL-NEXT: s_cselect_b32 s2, -1, s2
+; GFX12-ISEL-NEXT: s_cmp_u_f32 s7, s7
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s7, 0, s2
+; GFX12-ISEL-NEXT: s_cselect_b32 s9, 0, s3
+; GFX12-ISEL-NEXT: s_and_b32 s3, s4, 0x7fffffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX12-ISEL-NEXT: s_mul_f32 s2, s3, 0x2f800000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_floor_f32 s5, s2
+; GFX12-ISEL-NEXT: s_ashr_i32 s2, s4, 31
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s3, s5, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s5, s5
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s4, s3
+; GFX12-ISEL-NEXT: s_mov_b32 s3, s2
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_xor_b64 s[4:5], s[4:5], s[2:3]
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s0, 0xdf000000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_sub_nc_u64 s[2:3], s[4:5], s[2:3]
+; GFX12-ISEL-NEXT: s_cvt_f32_f16 s4, s1
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s2, 0, s2
+; GFX12-ISEL-NEXT: s_cselect_b32 s3, 0x80000000, s3
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s0, 0x5effffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, 0x7fffffff, s3
+; GFX12-ISEL-NEXT: s_cselect_b32 s2, -1, s2
+; GFX12-ISEL-NEXT: s_cmp_u_f32 s0, s0
+; GFX12-ISEL-NEXT: s_trunc_f32 s0, s4
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s5, 0, s2
+; GFX12-ISEL-NEXT: s_cselect_b32 s10, 0, s1
+; GFX12-ISEL-NEXT: s_and_b32 s1, s0, 0x7fffffff
+; GFX12-ISEL-NEXT: s_ashr_i32 s0, s0, 31
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_mul_f32 s2, s1, 0x2f800000
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v6, s7 :: v_dual_mov_b32 v1, s10
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: s_ashr_i32 s4, s2, 31
-; GFX12-ISEL-NEXT: s_ashr_i32 s5, s3, 31
-; GFX12-ISEL-NEXT: s_ashr_i32 s6, s0, 31
-; GFX12-ISEL-NEXT: s_ashr_i32 s7, s1, 31
+; GFX12-ISEL-NEXT: s_floor_f32 s2, s2
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s6
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s4
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v5, s7
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v7, s5
+; GFX12-ISEL-NEXT: s_fmac_f32 s1, s2, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s3, s2
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s2, s1
+; GFX12-ISEL-NEXT: s_mov_b32 s1, s0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1]
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s4, 0xdf000000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_sub_nc_u64 s[0:1], s[2:3], s[0:1]
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s0, 0, s0
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, 0x80000000, s1
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s4, 0x5effffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, 0x7fffffff, s1
+; GFX12-ISEL-NEXT: s_cselect_b32 s0, -1, s0
+; GFX12-ISEL-NEXT: s_cmp_u_f32 s4, s4
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s0, 0, s0
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, 0, s1
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v0, s5 :: v_dual_mov_b32 v5, s1
+; GFX12-ISEL-NEXT: v_mov_b32_e32 v4, s0
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_v4f16_v4i64:
@@ -5495,36 +6313,110 @@ define <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
; GFX7-ISEL-LABEL: test_signed_v8f16_v8i64:
; GFX7-ISEL: ; %bb.0:
; GFX7-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v7, v7
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v6, v6
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v5, v5
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v4, v4
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v4, v0
+; GFX7-ISEL-NEXT: s_mov_b32 s8, 0xdf000000
+; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v11, 16, v0
+; GFX7-ISEL-NEXT: s_mov_b32 s9, 0x5effffff
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v5, v4
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s8, v4
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s9, v4
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v4, v4
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v8, 31, v5
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v5, 0, vcc
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v15, 1
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v4, v5
+; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v10, 16, v3
+; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v1, v8, v15, vcc
+; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v16, -2
; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v16, v7
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v6, v6
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v10, v5
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v14, v4
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v8, v2
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v12, v3
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v17, 31, v16
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v11, 31, v10
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v15, 31, v14
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v9, 31, v8
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v13, 31, v12
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v2, v16
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v3, v17
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, v16, s[4:5]
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v8, 31, v4
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s8, v5
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s9, v5
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v5, v5
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v9, v2
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v5, v8, v15, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v4, v4, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v5, v5, v16, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v5, v5, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s8, v2
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s9, v2
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v2, v2
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v12, 31, v9
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v11, v11
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v8, v9, 0, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v9, v12, v15, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s8, v3
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v8, v8, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v9, v9, v16, s[4:5]
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v13, 31, v2
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s9, v3
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v7, v7
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v9, v9, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v3, v3
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v12, v2, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v2, v11
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v3, v13, v15, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, v16, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v13, v3, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s8, v11
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s9, v11
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v11, v11
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v11, v7
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v17, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v3, v3, v15, vcc
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v18, v10
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, v16, s[4:5]
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v14, 31, v11
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s8, v7
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v11, v11, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s9, v7
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v7, v7
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v7, v14, v15, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v6, v11, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v11, v17
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v7, v7, v16, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v7, v7, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s8, v17
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s9, v17
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v17, v17
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v17, v18
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v14, 31, v11
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v11, v11, 0, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v10, v11, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v11, v14, v15, vcc
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v19, 31, v17
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s8, v18
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v11, v11, v16, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v14, v17, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s9, v18
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v15, v19, v15, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v11, v11, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v14, v14, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v18, v18
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v15, v15, v16, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v15, v15, 0, s[6:7]
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_signed_v8f16_v8i64:
@@ -5713,30 +6605,182 @@ define <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
; GFX9-LABEL: test_signed_v8f16_v8i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX9-NEXT: v_cvt_i32_f32_e32 v16, v4
-; GFX9-NEXT: v_cvt_i32_f32_e32 v6, v5
-; GFX9-NEXT: v_cvt_i32_f32_e32 v10, v7
-; GFX9-NEXT: v_cvt_i32_f32_e32 v14, v8
-; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX9-NEXT: v_cvt_i32_f32_e32 v8, v2
-; GFX9-NEXT: v_cvt_i32_f32_e32 v12, v3
-; GFX9-NEXT: v_ashrrev_i32_e32 v17, 31, v16
-; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX9-NEXT: v_ashrrev_i32_e32 v11, 31, v10
-; GFX9-NEXT: v_ashrrev_i32_e32 v15, 31, v14
-; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX9-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX9-NEXT: v_ashrrev_i32_e32 v9, 31, v8
-; GFX9-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; GFX9-NEXT: v_mov_b32_e32 v7, v0
+; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v7
+; GFX9-NEXT: v_mov_b32_e32 v6, v1
+; GFX9-NEXT: s_mov_b32 s8, 0x2f800000
+; GFX9-NEXT: s_mov_b32 s9, 0xcf800000
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mul_f32_e64 v4, |v1|, s8
+; GFX9-NEXT: v_floor_f32_e32 v4, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v4
+; GFX9-NEXT: v_fma_f32 v4, v4, s9, |v1|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v1
+; GFX9-NEXT: v_xor_b32_e32 v5, v5, v1
+; GFX9-NEXT: s_mov_b32 s10, 0xdf000000
+; GFX9-NEXT: v_xor_b32_e32 v4, v4, v1
+; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v4, v1
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v5, v1, vcc
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s10, v0
+; GFX9-NEXT: s_mov_b32 s11, 0x5effffff
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s11, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, -1, s[4:5]
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[6:7]
+; GFX9-NEXT: v_cvt_f32_f16_e32 v4, v6
+; GFX9-NEXT: v_bfrev_b32_e32 v15, 1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc
+; GFX9-NEXT: v_bfrev_b32_e32 v18, -2
+; GFX9-NEXT: v_trunc_f32_e32 v5, v4
+; GFX9-NEXT: v_mul_f32_e64 v8, |v5|, s8
+; GFX9-NEXT: v_floor_f32_e32 v8, v8
+; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v8
+; GFX9-NEXT: v_fma_f32 v8, v8, s9, |v5|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX9-NEXT: v_ashrrev_i32_e32 v5, 31, v5
+; GFX9-NEXT: v_xor_b32_e32 v9, v9, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v18, s[4:5]
+; GFX9-NEXT: v_xor_b32_e32 v8, v8, v5
+; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v8, v5
+; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v9, v5, vcc
+; GFX9-NEXT: v_cvt_f32_f16_e32 v9, v2
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s10, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s11, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, -1, s[4:5]
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v4, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v8, 0, s[6:7]
+; GFX9-NEXT: v_trunc_f32_e32 v8, v9
+; GFX9-NEXT: v_mul_f32_e64 v10, |v8|, s8
+; GFX9-NEXT: v_floor_f32_e32 v10, v10
+; GFX9-NEXT: v_cvt_u32_f32_e32 v11, v10
+; GFX9-NEXT: v_fma_f32 v10, v10, s9, |v8|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v10, v10
+; GFX9-NEXT: v_ashrrev_i32_e32 v8, 31, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v15, vcc
+; GFX9-NEXT: v_xor_b32_e32 v11, v11, v8
+; GFX9-NEXT: v_xor_b32_e32 v10, v10, v8
+; GFX9-NEXT: v_sub_co_u32_e32 v10, vcc, v10, v8
+; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, v11, v8, vcc
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s10, v9
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v10, 0, vcc
+; GFX9-NEXT: v_cvt_f32_f16_e32 v10, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, v18, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, 0, s[6:7]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s11, v9
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v9, v9
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v11, v15, vcc
+; GFX9-NEXT: v_trunc_f32_e32 v11, v10
+; GFX9-NEXT: v_mul_f32_e64 v12, |v11|, s8
+; GFX9-NEXT: v_floor_f32_e32 v12, v12
+; GFX9-NEXT: v_cvt_u32_f32_e32 v13, v12
+; GFX9-NEXT: v_fma_f32 v12, v12, s9, |v11|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v12, v12
+; GFX9-NEXT: v_ashrrev_i32_e32 v11, 31, v11
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_xor_b32_e32 v13, v13, v11
+; GFX9-NEXT: v_xor_b32_e32 v12, v12, v11
+; GFX9-NEXT: v_sub_co_u32_e32 v12, vcc, v12, v11
+; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, v13, v11, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v9, v18, s[4:5]
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s10, v10
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v9, 0, s[6:7]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s11, v10
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v10, v10
+; GFX9-NEXT: v_cndmask_b32_e32 v10, v11, v15, vcc
+; GFX9-NEXT: v_trunc_f32_e32 v11, v7
+; GFX9-NEXT: v_mul_f32_e64 v13, |v11|, s8
+; GFX9-NEXT: v_floor_f32_e32 v13, v13
+; GFX9-NEXT: v_fma_f32 v14, v13, s9, |v11|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v14, v14
+; GFX9-NEXT: v_cvt_u32_f32_e32 v16, v13
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v18, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v13, v10, 0, s[6:7]
+; GFX9-NEXT: v_ashrrev_i32_e32 v10, 31, v11
+; GFX9-NEXT: v_xor_b32_e32 v14, v14, v10
+; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, 0, vcc
+; GFX9-NEXT: v_xor_b32_e32 v11, v16, v10
+; GFX9-NEXT: v_sub_co_u32_e32 v14, vcc, v14, v10
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, v11, v10, vcc
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s10, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v14, 0, vcc
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s11, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, -1, s[4:5]
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v7, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v10, v15, vcc
+; GFX9-NEXT: v_trunc_f32_e32 v10, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v16, v11, 0, s[6:7]
+; GFX9-NEXT: v_mul_f32_e64 v11, |v10|, s8
+; GFX9-NEXT: v_floor_f32_e32 v11, v11
+; GFX9-NEXT: v_fma_f32 v14, v11, s9, |v10|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GFX9-NEXT: v_cvt_u32_f32_e32 v14, v14
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v18, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v17, v7, 0, s[6:7]
+; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v10
+; GFX9-NEXT: v_xor_b32_e32 v10, v11, v7
+; GFX9-NEXT: v_xor_b32_e32 v11, v14, v7
+; GFX9-NEXT: v_sub_co_u32_e32 v11, vcc, v11, v7
+; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v10, v7, vcc
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s10, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v11, 0, vcc
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s11, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, -1, s[4:5]
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v6, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v10, 0, s[6:7]
+; GFX9-NEXT: v_trunc_f32_e32 v10, v2
+; GFX9-NEXT: v_mul_f32_e64 v11, |v10|, s8
+; GFX9-NEXT: v_floor_f32_e32 v11, v11
+; GFX9-NEXT: v_fma_f32 v14, v11, s9, |v10|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v14, v14
+; GFX9-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GFX9-NEXT: v_ashrrev_i32_e32 v10, 31, v10
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_xor_b32_e32 v14, v14, v10
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc
+; GFX9-NEXT: v_xor_b32_e32 v11, v11, v10
+; GFX9-NEXT: v_sub_co_u32_e32 v14, vcc, v14, v10
+; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, v11, v10, vcc
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s10, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v18, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v14, 0, vcc
+; GFX9-NEXT: v_trunc_f32_e32 v14, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, 0, s[6:7]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s11, v2
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v2, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v15, vcc
+; GFX9-NEXT: v_mul_f32_e64 v11, |v14|, s8
+; GFX9-NEXT: v_floor_f32_e32 v11, v11
+; GFX9-NEXT: v_fma_f32 v19, v11, s9, |v14|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v19, v19
+; GFX9-NEXT: v_cvt_u32_f32_e32 v20, v11
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v18, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v2, 0, s[6:7]
+; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v14
+; GFX9-NEXT: v_xor_b32_e32 v19, v19, v2
+; GFX9-NEXT: v_xor_b32_e32 v14, v20, v2
+; GFX9-NEXT: v_sub_co_u32_e32 v19, vcc, v19, v2
+; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v14, v2, vcc
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s10, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v14, v19, 0, vcc
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s11, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v15, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v14, v14, -1, s[4:5]
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v3, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v18, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v15, v2, 0, s[6:7]
; GFX9-NEXT: v_mov_b32_e32 v2, v16
; GFX9-NEXT: v_mov_b32_e32 v3, v17
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -5744,69 +6788,357 @@ define <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
; GFX11-FAKE16-LABEL: test_signed_v8f16_v8i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v2
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v10, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v4
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v5
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v7
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v10
+; GFX11-FAKE16-NEXT: v_mul_f32_e64 v9, 0x2f800000, |v6|
+; GFX11-FAKE16-NEXT: v_mul_f32_e64 v13, 0x2f800000, |v8|
+; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v14, 31, v6
+; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v16, 31, v8
+; GFX11-FAKE16-NEXT: v_mul_f32_e64 v15, 0x2f800000, |v11|
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v9, v9
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v13, v13
+; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v18, 31, v11
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v4
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, v5
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v8, v6
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v15, v15
+; GFX11-FAKE16-NEXT: v_fma_f32 v6, 0xcf800000, v9, |v6|
+; GFX11-FAKE16-NEXT: v_fma_f32 v8, 0xcf800000, v13, |v8|
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v9, v9
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v13, v13
+; GFX11-FAKE16-NEXT: v_fma_f32 v11, 0xcf800000, v15, |v11|
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v9, v9, v14
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v13, v13, v16
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v6, v6, v14
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v8, v8, v16
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v19, v15
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_sub_co_u32 v6, vcc_lo, v6, v14
+; GFX11-FAKE16-NEXT: v_sub_co_ci_u32_e64 v9, null, v9, v14, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v4
+; GFX11-FAKE16-NEXT: v_sub_co_u32 v8, s0, v8, v16
+; GFX11-FAKE16-NEXT: v_sub_co_ci_u32_e64 v13, null, v13, v16, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, v9, 0x80000000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v5
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v16, v4
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v7
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v6, v5
-; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v10, v8
-; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v17, 31, v16
-; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v14, v4
-; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v8, v2
-; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v12, v3
-; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v11, 31, v10
-; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v15, 31, v14
-; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v9, 31, v8
-; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v13, 31, v12
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, v16 :: v_dual_mov_b32 v3, v17
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, -1, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v9, 0x7fffffff, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, v13, 0x80000000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v5, v11, v18
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v16, v6, 0, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, -1, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v4, 0, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, v9, 0x7fffffff, s0
+; GFX11-FAKE16-NEXT: v_mul_f32_e64 v9, 0x2f800000, |v12|
+; GFX11-FAKE16-NEXT: v_sub_co_u32 v5, s0, v5, v18
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v8, v19, v18
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v9, v9
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, 0x5effffff, v0
+; GFX11-FAKE16-NEXT: v_sub_co_ci_u32_e64 v8, null, v8, v18, s0
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e64 s0, 0xdf000000, v7
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v14, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v5, 0, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v6, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_fma_f32 v6, 0xcf800000, v9, |v12|
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, 0x80000000, s0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v0
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v12, 31, v12
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, -1, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v13, v8, 0x7fffffff, vcc_lo
+; GFX11-FAKE16-NEXT: v_mul_f32_e64 v15, 0x2f800000, |v7|
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v6, v6, v12
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v11, 0, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, v13, 0, s0
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v11, v14, v12
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v13, v15
+; GFX11-FAKE16-NEXT: v_sub_co_u32 v6, vcc_lo, v6, v12
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v10
+; GFX11-FAKE16-NEXT: v_sub_co_ci_u32_e64 v11, null, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT: v_fma_f32 v12, 0xcf800000, v13, |v7|
+; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v7, 31, v7
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v10
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v13, v13
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v14, v1
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v12, v12
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, 0x80000000, vcc_lo
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v13, v13, v7
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v12, v12, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, -1, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, 0x7fffffff, s0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
+; GFX11-FAKE16-NEXT: v_sub_co_u32 v12, vcc_lo, v12, v7
+; GFX11-FAKE16-NEXT: v_sub_co_ci_u32_e64 v7, null, v13, v7, vcc_lo
+; GFX11-FAKE16-NEXT: v_mul_f32_e64 v13, 0x2f800000, |v14|
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v15, v12, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, v6, 0, s0
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v6, v13
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v13, v11, 0, s0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, v15, -1, s1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v0, v0
+; GFX11-FAKE16-NEXT: v_fma_f32 v15, 0xcf800000, v6, |v14|
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v7, 0x80000000, vcc_lo
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v11
+; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v11, 31, v14
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v10, 0, s0
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v10, v15
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v14, v7
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v15, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fffffff, s1
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v3, v10, v11
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v6, v6, v11
+; GFX11-FAKE16-NEXT: v_mul_f32_e64 v10, 0x2f800000, |v14|
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v18, v15
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, 0x5effffff, v7
+; GFX11-FAKE16-NEXT: v_sub_co_u32 v3, vcc_lo, v3, v11
+; GFX11-FAKE16-NEXT: v_sub_co_ci_u32_e64 v6, null, v6, v11, vcc_lo
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v10, v10
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v1
+; GFX11-FAKE16-NEXT: v_mul_f32_e64 v19, 0x2f800000, |v18|
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v3, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v0, 0, s0
+; GFX11-FAKE16-NEXT: v_fma_f32 v0, 0xcf800000, v10, |v14|
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v1
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v19, v19
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v20, v6, 0x80000000, vcc_lo
+; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v14, 31, v14
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, -1, s0
+; GFX11-FAKE16-NEXT: v_fma_f32 v21, 0xcf800000, v19, |v18|
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v10, v10
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v14
+; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v18, 31, v18
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v19, v19
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, v11, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v11, v21
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v10, v10, v14
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v20, 0x7fffffff, s0
+; GFX11-FAKE16-NEXT: v_sub_co_u32 v0, s0, v0, v14
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v11, v11, v18
+; GFX11-FAKE16-NEXT: v_sub_co_ci_u32_e64 v10, null, v10, v14, s0
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v14, v19, v18
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e64 s0, 0xdf000000, v7
+; GFX11-FAKE16-NEXT: v_sub_co_u32 v11, s1, v11, v18
+; GFX11-FAKE16-NEXT: v_sub_co_ci_u32_e64 v14, null, v14, v18, s1
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e64 s1, 0xdf000000, v15
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, v10, 0x80000000, s0
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v15
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, 0, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, 0x80000000, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, -1, s2
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v18, v10, 0x7fffffff, s2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v11, -1, s0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v15, v14, 0x7fffffff, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v1, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, v0, 0, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v18, 0, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v19, 0, s2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v15, v15, 0, s2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: test_signed_v8f16_v8i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v2.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v10, v3.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v4
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v5
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v10
+; GFX11-TRUE16-NEXT: v_mul_f32_e64 v9, 0x2f800000, |v6|
+; GFX11-TRUE16-NEXT: v_mul_f32_e64 v13, 0x2f800000, |v8|
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v14, 31, v6
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v16, 31, v8
+; GFX11-TRUE16-NEXT: v_mul_f32_e64 v15, 0x2f800000, |v11|
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v9, v9
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v13, v13
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v18, 31, v11
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v4.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v5.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v6.l
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v15, v15
+; GFX11-TRUE16-NEXT: v_fma_f32 v6, 0xcf800000, v9, |v6|
+; GFX11-TRUE16-NEXT: v_fma_f32 v8, 0xcf800000, v13, |v8|
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v9, v9
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v13, v13
+; GFX11-TRUE16-NEXT: v_fma_f32 v11, 0xcf800000, v15, |v11|
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v9, v9, v14
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v13, v13, v16
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v6, v6, v14
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v8, v8, v16
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v19, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_sub_co_u32 v6, vcc_lo, v6, v14
+; GFX11-TRUE16-NEXT: v_sub_co_ci_u32_e64 v9, null, v9, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v4
+; GFX11-TRUE16-NEXT: v_sub_co_u32 v8, s0, v8, v16
+; GFX11-TRUE16-NEXT: v_sub_co_ci_u32_e64 v13, null, v13, v16, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, v9, 0x80000000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v5
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v16, v4
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v7.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v6, v5
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v10, v8
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v17, 31, v16
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v14, v4
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v8, v2
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v12, v3
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v11, 31, v10
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v15, 31, v14
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v9, 31, v8
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v13, 31, v12
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v16 :: v_dual_mov_b32 v3, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v6, -1, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, v9, 0x7fffffff, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, v13, 0x80000000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v5, v11, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v16, v6, 0, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, v8, -1, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v17, v4, 0, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v9, 0x7fffffff, s0
+; GFX11-TRUE16-NEXT: v_mul_f32_e64 v9, 0x2f800000, |v12|
+; GFX11-TRUE16-NEXT: v_sub_co_u32 v5, s0, v5, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v8, v19, v18
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v9, v9
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, 0x5effffff, v0
+; GFX11-TRUE16-NEXT: v_sub_co_ci_u32_e64 v8, null, v8, v18, s0
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e64 s0, 0xdf000000, v7
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v14, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, v5, 0, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v6, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_fma_f32 v6, 0xcf800000, v9, |v12|
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, v8, 0x80000000, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v0
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v12, 31, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, -1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, v8, 0x7fffffff, vcc_lo
+; GFX11-TRUE16-NEXT: v_mul_f32_e64 v15, 0x2f800000, |v7|
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v6, v6, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, v11, 0, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, v13, 0, s0
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v11, v14, v12
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v13, v15
+; GFX11-TRUE16-NEXT: v_sub_co_u32 v6, vcc_lo, v6, v12
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v10
+; GFX11-TRUE16-NEXT: v_sub_co_ci_u32_e64 v11, null, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_fma_f32 v12, 0xcf800000, v13, |v7|
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v7, 31, v7
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v10
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v13, v13
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v14, v1
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v12, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, 0x80000000, vcc_lo
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v13, v13, v7
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v12, v12, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v6, -1, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, 0x7fffffff, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
+; GFX11-TRUE16-NEXT: v_sub_co_u32 v12, vcc_lo, v12, v7
+; GFX11-TRUE16-NEXT: v_sub_co_ci_u32_e64 v7, null, v13, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_mul_f32_e64 v13, 0x2f800000, |v14|
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v15, v12, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, v6, 0, s0
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v6, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, v11, 0, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, v15, -1, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v0, v0
+; GFX11-TRUE16-NEXT: v_fma_f32 v15, 0xcf800000, v6, |v14|
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v7, 0x80000000, vcc_lo
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v11.l
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v11, 31, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v10, 0, s0
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v10, v15
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v14, v7
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v15, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fffffff, s1
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v3, v10, v11
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v6, v6, v11
+; GFX11-TRUE16-NEXT: v_mul_f32_e64 v10, 0x2f800000, |v14|
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v18, v15
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, 0x5effffff, v7
+; GFX11-TRUE16-NEXT: v_sub_co_u32 v3, vcc_lo, v3, v11
+; GFX11-TRUE16-NEXT: v_sub_co_ci_u32_e64 v6, null, v6, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v10, v10
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v1
+; GFX11-TRUE16-NEXT: v_mul_f32_e64 v19, 0x2f800000, |v18|
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, v3, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, v0, 0, s0
+; GFX11-TRUE16-NEXT: v_fma_f32 v0, 0xcf800000, v10, |v14|
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v1
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v19, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v20, v6, 0x80000000, vcc_lo
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v14, 31, v14
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, -1, s0
+; GFX11-TRUE16-NEXT: v_fma_f32 v21, 0xcf800000, v19, |v18|
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v10, v10
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v0, v0, v14
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v18, 31, v18
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v19, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v11, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v11, v21
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v10, v10, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v20, 0x7fffffff, s0
+; GFX11-TRUE16-NEXT: v_sub_co_u32 v0, s0, v0, v14
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v11, v11, v18
+; GFX11-TRUE16-NEXT: v_sub_co_ci_u32_e64 v10, null, v10, v14, s0
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v14, v19, v18
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e64 s0, 0xdf000000, v7
+; GFX11-TRUE16-NEXT: v_sub_co_u32 v11, s1, v11, v18
+; GFX11-TRUE16-NEXT: v_sub_co_ci_u32_e64 v14, null, v14, v18, s1
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e64 s1, 0xdf000000, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, v10, 0x80000000, s0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, 0, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v14, v14, 0x80000000, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, -1, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v18, v10, 0x7fffffff, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v19, v11, -1, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v15, v14, 0x7fffffff, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, v1, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, v0, 0, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, v18, 0, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v14, v19, 0, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v15, v15, 0, s2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_signed_v8f16_v8i64:
@@ -5816,35 +7148,205 @@ define <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v0
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v2
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v10, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v6, v4
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v8, v5
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v11, v7
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v12, v10
+; GFX12-FAKE16-NEXT: v_mul_f32_e64 v9, 0x2f800000, |v6|
+; GFX12-FAKE16-NEXT: v_mul_f32_e64 v13, 0x2f800000, |v8|
+; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v14, 31, v6
+; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v16, 31, v8
+; GFX12-FAKE16-NEXT: v_mul_f32_e64 v15, 0x2f800000, |v11|
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v9, v9
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v13, v13
+; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v18, 31, v11
; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v4
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, v5
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v8, v6
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v15, v15
+; GFX12-FAKE16-NEXT: v_fma_f32 v6, 0xcf800000, v9, |v6|
+; GFX12-FAKE16-NEXT: v_fma_f32 v8, 0xcf800000, v13, |v8|
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v9, v9
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v13, v13
+; GFX12-FAKE16-NEXT: v_fma_f32 v11, 0xcf800000, v15, |v11|
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v9, v9, v14
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v13, v13, v16
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v6, v6, v14
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v8, v8, v16
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v19, v15
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX12-FAKE16-NEXT: v_sub_co_u32 v6, vcc_lo, v6, v14
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_sub_co_ci_u32_e64 v9, null, v9, v14, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v4
+; GFX12-FAKE16-NEXT: v_sub_co_u32 v8, s0, v8, v16
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_sub_co_ci_u32_e64 v13, null, v13, v16, s0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v4
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v9, v9, 0x80000000, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v5
; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v16, v4
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v7
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v6, v5
-; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v10, v8
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v17, 31, v16
-; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v14, v4
-; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v8, v2
-; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v12, v3
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v11, 31, v10
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v15, 31, v14
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v9, 31, v8
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v13, 31, v12
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v2, v16 :: v_dual_mov_b32 v3, v17
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, -1, s0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v9, 0x7fffffff, s0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v5
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v9, v13, 0x80000000, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v5, v11, v18
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v16, v6, 0, s1
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, -1, s0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v17, v4, 0, s1
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v6, v9, 0x7fffffff, s0
+; GFX12-FAKE16-NEXT: v_mul_f32_e64 v9, 0x2f800000, |v12|
+; GFX12-FAKE16-NEXT: v_sub_co_u32 v5, s0, v5, v18
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v8, v19, v18
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v9, v9
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, 0x5effffff, v0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_sub_co_ci_u32_e64 v8, null, v8, v18, s0
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e64 s0, 0xdf000000, v7
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v14, v9
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v5, 0, s0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v5, v6, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_fma_f32 v6, 0xcf800000, v9, |v12|
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v7
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, 0x80000000, s0
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v7, v0
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v12, 31, v12
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, -1, vcc_lo
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v13, v8, 0x7fffffff, vcc_lo
+; GFX12-FAKE16-NEXT: v_mul_f32_e64 v15, 0x2f800000, |v7|
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v6, v6, v12
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v11, 0, s0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v9, v13, 0, s0
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v11, v14, v12
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v13, v15
+; GFX12-FAKE16-NEXT: v_sub_co_u32 v6, vcc_lo, v6, v12
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v10
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_sub_co_ci_u32_e64 v11, null, v11, v12, vcc_lo
+; GFX12-FAKE16-NEXT: v_fma_f32 v12, 0xcf800000, v13, |v7|
+; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v7, 31, v7
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v10
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v13, v13
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v14, v1
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v12, v12
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, 0x80000000, vcc_lo
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v13, v13, v7
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v12, v12, v7
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, -1, s0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, 0x7fffffff, s0
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
+; GFX12-FAKE16-NEXT: v_sub_co_u32 v12, vcc_lo, v12, v7
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_sub_co_ci_u32_e64 v7, null, v13, v7, vcc_lo
+; GFX12-FAKE16-NEXT: v_mul_f32_e64 v13, 0x2f800000, |v14|
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v15, v12, 0, vcc_lo
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v12, v6, 0, s0
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v6, v13
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v13, v11, 0, s0
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v10, v15, -1, s1
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v0, v0
+; GFX12-FAKE16-NEXT: v_fma_f32 v15, 0xcf800000, v6, |v14|
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v7, 0x80000000, vcc_lo
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v11
+; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v11, 31, v14
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v10, 0, s0
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v10, v15
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v14, v7
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v15, v3
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fffffff, s1
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v3, v10, v11
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v6, v6, v11
+; GFX12-FAKE16-NEXT: v_mul_f32_e64 v10, 0x2f800000, |v14|
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v18, v15
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, 0x5effffff, v7
+; GFX12-FAKE16-NEXT: v_sub_co_u32 v3, vcc_lo, v3, v11
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_sub_co_ci_u32_e64 v6, null, v6, v11, vcc_lo
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v10, v10
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v1
+; GFX12-FAKE16-NEXT: v_mul_f32_e64 v19, 0x2f800000, |v18|
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v3, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v0, 0, s0
+; GFX12-FAKE16-NEXT: v_fma_f32 v0, 0xcf800000, v10, |v14|
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v1
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v19, v19
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v20, v6, 0x80000000, vcc_lo
+; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v14, 31, v14
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, -1, s0
+; GFX12-FAKE16-NEXT: v_fma_f32 v21, 0xcf800000, v19, |v18|
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v10, v10
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v14
+; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v18, 31, v18
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v19, v19
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v6, v11, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v11, v21
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v10, v10, v14
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v20, 0x7fffffff, s0
+; GFX12-FAKE16-NEXT: v_sub_co_u32 v0, s0, v0, v14
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v11, v11, v18
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_sub_co_ci_u32_e64 v10, null, v10, v14, s0
+; GFX12-FAKE16-NEXT: v_xor_b32_e32 v14, v19, v18
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e64 s0, 0xdf000000, v7
+; GFX12-FAKE16-NEXT: v_sub_co_u32 v11, s1, v11, v18
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_sub_co_ci_u32_e64 v14, null, v14, v18, s1
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e64 s1, 0xdf000000, v15
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0, s0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v10, v10, 0x80000000, s0
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v15
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, 0, s1
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, 0x80000000, s1
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, -1, s2
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v18, v10, 0x7fffffff, s2
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v19, v11, -1, s0
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v15, v14, 0x7fffffff, s0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v7, v1, 0, vcc_lo
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v10, v0, 0, s1
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v18, 0, s1
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v14, v19, 0, s2
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v15, v15, 0, s2
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_signed_v8f16_v8i64:
@@ -5854,35 +7356,205 @@ define <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v2.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v10, v3.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v6, v4
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v8, v5
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v11, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v12, v10
+; GFX12-TRUE16-NEXT: v_mul_f32_e64 v9, 0x2f800000, |v6|
+; GFX12-TRUE16-NEXT: v_mul_f32_e64 v13, 0x2f800000, |v8|
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v14, 31, v6
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v16, 31, v8
+; GFX12-TRUE16-NEXT: v_mul_f32_e64 v15, 0x2f800000, |v11|
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v9, v9
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v13, v13
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v18, 31, v11
; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v4.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v5.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v6.l
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v15, v15
+; GFX12-TRUE16-NEXT: v_fma_f32 v6, 0xcf800000, v9, |v6|
+; GFX12-TRUE16-NEXT: v_fma_f32 v8, 0xcf800000, v13, |v8|
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v9, v9
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v13, v13
+; GFX12-TRUE16-NEXT: v_fma_f32 v11, 0xcf800000, v15, |v11|
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v9, v9, v14
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v13, v13, v16
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v6, v6, v14
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v8, v8, v16
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v19, v15
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX12-TRUE16-NEXT: v_sub_co_u32 v6, vcc_lo, v6, v14
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_sub_co_ci_u32_e64 v9, null, v9, v14, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v4
+; GFX12-TRUE16-NEXT: v_sub_co_u32 v8, s0, v8, v16
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_sub_co_ci_u32_e64 v13, null, v13, v16, s0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v9, v9, 0x80000000, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v5
; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v16, v4
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v7.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v6, v5
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v10, v8
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v17, 31, v16
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v14, v4
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v8, v2
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v12, v3
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v11, 31, v10
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v15, 31, v14
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v9, 31, v8
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v13, 31, v12
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v16 :: v_dual_mov_b32 v3, v17
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v6, -1, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v4, v9, 0x7fffffff, s0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v5
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v9, v13, 0x80000000, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v5, v11, v18
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v16, v6, 0, s1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v8, v8, -1, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v17, v4, 0, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v9, 0x7fffffff, s0
+; GFX12-TRUE16-NEXT: v_mul_f32_e64 v9, 0x2f800000, |v12|
+; GFX12-TRUE16-NEXT: v_sub_co_u32 v5, s0, v5, v18
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v4, v8, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v8, v19, v18
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v9, v9
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, 0x5effffff, v0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_sub_co_ci_u32_e64 v8, null, v8, v18, s0
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e64 s0, 0xdf000000, v7
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v14, v9
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v11, v5, 0, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v6, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_fma_f32 v6, 0xcf800000, v9, |v12|
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v8, v8, 0x80000000, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v7, v0
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v12, 31, v12
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, -1, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v13, v8, 0x7fffffff, vcc_lo
+; GFX12-TRUE16-NEXT: v_mul_f32_e64 v15, 0x2f800000, |v7|
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v6, v6, v12
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v8, v11, 0, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v9, v13, 0, s0
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v11, v14, v12
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v13, v15
+; GFX12-TRUE16-NEXT: v_sub_co_u32 v6, vcc_lo, v6, v12
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v10
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_sub_co_ci_u32_e64 v11, null, v11, v12, vcc_lo
+; GFX12-TRUE16-NEXT: v_fma_f32 v12, 0xcf800000, v13, |v7|
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v7, 31, v7
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v10
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v13, v13
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v14, v1
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v12, v12
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, 0x80000000, vcc_lo
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v13, v13, v7
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v12, v12, v7
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v6, -1, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, 0x7fffffff, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
+; GFX12-TRUE16-NEXT: v_sub_co_u32 v12, vcc_lo, v12, v7
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_sub_co_ci_u32_e64 v7, null, v13, v7, vcc_lo
+; GFX12-TRUE16-NEXT: v_mul_f32_e64 v13, 0x2f800000, |v14|
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v15, v12, 0, vcc_lo
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v12, v6, 0, s0
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v6, v13
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v13, v11, 0, s0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v10, v15, -1, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v0, v0
+; GFX12-TRUE16-NEXT: v_fma_f32 v15, 0xcf800000, v6, |v14|
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, v7, 0x80000000, vcc_lo
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v11.l
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v11, 31, v14
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, v10, 0, s0
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v10, v15
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v14, v7
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v15, v3.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fffffff, s1
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v3, v10, v11
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v6, v6, v11
+; GFX12-TRUE16-NEXT: v_mul_f32_e64 v10, 0x2f800000, |v14|
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v18, v15
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, 0x5effffff, v7
+; GFX12-TRUE16-NEXT: v_sub_co_u32 v3, vcc_lo, v3, v11
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_sub_co_ci_u32_e64 v6, null, v6, v11, vcc_lo
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v10, v10
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v1
+; GFX12-TRUE16-NEXT: v_mul_f32_e64 v19, 0x2f800000, |v18|
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v11, v3, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v3, v0, 0, s0
+; GFX12-TRUE16-NEXT: v_fma_f32 v0, 0xcf800000, v10, |v14|
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v1
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v19, v19
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v20, v6, 0x80000000, vcc_lo
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v14, 31, v14
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, -1, s0
+; GFX12-TRUE16-NEXT: v_fma_f32 v21, 0xcf800000, v19, |v18|
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v10, v10
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v0, v0, v14
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v18, 31, v18
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v19, v19
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v11, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v11, v21
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v10, v10, v14
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, v20, 0x7fffffff, s0
+; GFX12-TRUE16-NEXT: v_sub_co_u32 v0, s0, v0, v14
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v11, v11, v18
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_sub_co_ci_u32_e64 v10, null, v10, v14, s0
+; GFX12-TRUE16-NEXT: v_xor_b32_e32 v14, v19, v18
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e64 s0, 0xdf000000, v7
+; GFX12-TRUE16-NEXT: v_sub_co_u32 v11, s1, v11, v18
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_sub_co_ci_u32_e64 v14, null, v14, v18, s1
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e64 s1, 0xdf000000, v15
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v10, v10, 0x80000000, s0
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v15
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, 0, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v14, v14, 0x80000000, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, -1, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v18, v10, 0x7fffffff, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v19, v11, -1, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v15, v14, 0x7fffffff, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v7, v1, 0, vcc_lo
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v10, v0, 0, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v11, v18, 0, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v14, v19, 0, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v15, v15, 0, s2
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_v8f16_v8i64:
@@ -7219,34 +8891,110 @@ define <8 x i64> @test_s_signed_v8f16_v8i64(<8 x half> inreg %f) {
; GFX7-ISEL-LABEL: test_s_signed_v8f16_v8i64:
; GFX7-ISEL: ; %bb.0:
; GFX7-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-ISEL-NEXT: s_lshr_b32 s6, s17, 16
-; GFX7-ISEL-NEXT: s_lshr_b32 s7, s16, 16
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v0, s7
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v1, s6
-; GFX7-ISEL-NEXT: s_lshr_b32 s4, s19, 16
-; GFX7-ISEL-NEXT: s_lshr_b32 s5, s18, 16
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v3, s5
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v4, s4
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v2, v0
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v6, v1
; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v0, s16
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v1, s17
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v5, s18
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v9, s19
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v10, v3
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v14, v4
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v8, v5
-; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v12, v9
+; GFX7-ISEL-NEXT: s_mov_b32 s12, 0xdf000000
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v3, s17
+; GFX7-ISEL-NEXT: s_mov_b32 s13, 0x5effffff
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v1, v0
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s12, v0
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s13, v0
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v15, 1
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v1, v2, v15, vcc
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v6, s18
+; GFX7-ISEL-NEXT: v_bfrev_b32_e32 v16, -2
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s12, v3
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, v16, s[4:5]
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v5, 31, v2
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s13, v3
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v3, v3
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v4, v2, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v2, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v3, v5, v15, vcc
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v7, s19
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, v16, s[4:5]
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s12, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v5, v3, 0, s[6:7]
; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v11, 31, v10
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v15, 31, v14
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v9, 31, v8
-; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s13, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v6, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v8, v2, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v2, v7
+; GFX7-ISEL-NEXT: s_lshr_b32 s11, s16, 16
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v3, v3, v15, vcc
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v6, s11
+; GFX7-ISEL-NEXT: s_lshr_b32 s10, s17, 16
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, v16, s[4:5]
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s12, v7
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v9, v3, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s13, v7
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v7, v7
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v7, s10
+; GFX7-ISEL-NEXT: s_lshr_b32 s9, s18, 16
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v12, v2, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v2, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v3, v3, v15, vcc
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v11, s9
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, v16, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v13, v3, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s12, v6
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s13, v6
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v6, v6
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v14, v11
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v3, v3, v15, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, v16, s[4:5]
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v10, 31, v6
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s12, v7
+; GFX7-ISEL-NEXT: s_lshr_b32 s8, s19, 16
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s13, v7
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v7, v7
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v7, v10, v15, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s12, v11
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v17, 31, v14
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v10, v14, 0, vcc
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v14, s8
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v6, v6, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v7, v7, v16, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v18, v14
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v7, v7, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s13, v11
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v11, v11
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v11, v17, v15, vcc
+; GFX7-ISEL-NEXT: v_ashrrev_i32_e32 v17, 31, v18
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, s12, v14
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v10, v10, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v11, v11, v16, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v18, v18, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], s13, v14
+; GFX7-ISEL-NEXT: v_cndmask_b32_e32 v15, v17, v15, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v11, v11, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v18, v18, -1, s[4:5]
+; GFX7-ISEL-NEXT: v_cmp_u_f32_e64 s[6:7], v14, v14
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v15, v15, v16, s[4:5]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v14, v18, 0, s[6:7]
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v15, v15, 0, s[6:7]
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_s_signed_v8f16_v8i64:
@@ -7477,67 +9225,531 @@ define <8 x i64> @test_s_signed_v8f16_v8i64(<8 x half> inreg %f) {
; GFX9-LABEL: test_s_signed_v8f16_v8i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s16
+; GFX9-NEXT: s_mov_b32 s9, 0x2f800000
+; GFX9-NEXT: s_mov_b32 s10, 0xcf800000
+; GFX9-NEXT: s_mov_b32 s11, 0xdf000000
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mul_f32_e64 v2, |v1|, s9
+; GFX9-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-NEXT: v_fma_f32 v3, v2, s10, |v1|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s6, v1
+; GFX9-NEXT: s_ashr_i32 s6, s6, 31
+; GFX9-NEXT: v_readfirstlane_b32 s4, v3
+; GFX9-NEXT: v_readfirstlane_b32 s5, v2
+; GFX9-NEXT: s_mov_b32 s7, s6
+; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
+; GFX9-NEXT: s_sub_u32 s7, s4, s6
+; GFX9-NEXT: s_subb_u32 s13, s5, s6
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s11, v0
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_mov_b32 s12, 0x5effffff
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s12, v0
+; GFX9-NEXT: s_cselect_b32 s8, 0, s7
+; GFX9-NEXT: s_and_b64 s[6:7], s[4:5], exec
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s17
+; GFX9-NEXT: s_cselect_b32 s8, -1, s8
+; GFX9-NEXT: s_and_b64 s[14:15], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s8, 0, s8
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mul_f32_e64 v2, |v1|, s9
+; GFX9-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-NEXT: v_fma_f32 v3, v2, s10, |v1|
+; GFX9-NEXT: s_and_b64 s[14:15], vcc, exec
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: s_cselect_b32 s13, 0x80000000, s13
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX9-NEXT: s_cselect_b32 s13, 0x7fffffff, s13
+; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], exec
+; GFX9-NEXT: v_readfirstlane_b32 s6, v1
+; GFX9-NEXT: s_cselect_b32 s13, 0, s13
+; GFX9-NEXT: s_ashr_i32 s6, s6, 31
+; GFX9-NEXT: v_readfirstlane_b32 s4, v3
+; GFX9-NEXT: v_readfirstlane_b32 s5, v2
+; GFX9-NEXT: s_mov_b32 s7, s6
+; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
+; GFX9-NEXT: s_sub_u32 s7, s4, s6
+; GFX9-NEXT: s_subb_u32 s22, s5, s6
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s11, v0
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s12, v0
+; GFX9-NEXT: s_cselect_b32 s14, 0, s7
+; GFX9-NEXT: s_and_b64 s[6:7], s[4:5], exec
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s18
+; GFX9-NEXT: s_cselect_b32 s20, -1, s14
+; GFX9-NEXT: s_and_b64 s[14:15], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s14, 0, s20
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mul_f32_e64 v2, |v1|, s9
+; GFX9-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-NEXT: v_fma_f32 v3, v2, s10, |v1|
+; GFX9-NEXT: s_and_b64 s[20:21], vcc, exec
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: s_cselect_b32 s15, 0x80000000, s22
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX9-NEXT: s_cselect_b32 s15, 0x7fffffff, s15
+; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], exec
+; GFX9-NEXT: v_readfirstlane_b32 s6, v1
+; GFX9-NEXT: s_cselect_b32 s15, 0, s15
+; GFX9-NEXT: s_ashr_i32 s6, s6, 31
+; GFX9-NEXT: v_readfirstlane_b32 s4, v3
+; GFX9-NEXT: v_readfirstlane_b32 s5, v2
+; GFX9-NEXT: s_mov_b32 s7, s6
+; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
+; GFX9-NEXT: s_sub_u32 s7, s4, s6
+; GFX9-NEXT: s_subb_u32 s22, s5, s6
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s11, v0
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s12, v0
+; GFX9-NEXT: s_cselect_b32 s20, 0, s7
+; GFX9-NEXT: s_and_b64 s[6:7], s[4:5], exec
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s19
+; GFX9-NEXT: s_cselect_b32 s23, -1, s20
+; GFX9-NEXT: s_and_b64 s[20:21], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s23, 0, s23
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mul_f32_e64 v2, |v1|, s9
+; GFX9-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-NEXT: v_fma_f32 v3, v2, s10, |v1|
+; GFX9-NEXT: s_and_b64 s[20:21], vcc, exec
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: s_cselect_b32 s20, 0x80000000, s22
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX9-NEXT: s_cselect_b32 s20, 0x7fffffff, s20
+; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], exec
+; GFX9-NEXT: v_readfirstlane_b32 s6, v1
+; GFX9-NEXT: s_cselect_b32 s22, 0, s20
+; GFX9-NEXT: s_ashr_i32 s6, s6, 31
+; GFX9-NEXT: v_readfirstlane_b32 s4, v3
+; GFX9-NEXT: v_readfirstlane_b32 s5, v2
+; GFX9-NEXT: s_mov_b32 s7, s6
+; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
+; GFX9-NEXT: s_sub_u32 s7, s4, s6
+; GFX9-NEXT: s_subb_u32 s24, s5, s6
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s11, v0
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s12, v0
+; GFX9-NEXT: s_cselect_b32 s20, 0, s7
+; GFX9-NEXT: s_and_b64 s[6:7], s[4:5], exec
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX9-NEXT: s_cselect_b32 s25, -1, s20
+; GFX9-NEXT: s_and_b64 s[20:21], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s25, 0, s25
+; GFX9-NEXT: s_and_b64 s[20:21], vcc, exec
+; GFX9-NEXT: s_cselect_b32 s20, 0x80000000, s24
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX9-NEXT: s_cselect_b32 s20, 0x7fffffff, s20
+; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s24, 0, s20
; GFX9-NEXT: s_lshr_b32 s4, s16, 16
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v4, s14
+; GFX9-NEXT: v_mov_b32_e32 v5, s15
+; GFX9-NEXT: v_mov_b32_e32 v8, s23
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mul_f32_e64 v2, |v1|, s9
+; GFX9-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-NEXT: v_fma_f32 v3, v2, s10, |v1|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s6, v1
+; GFX9-NEXT: s_ashr_i32 s6, s6, 31
+; GFX9-NEXT: v_readfirstlane_b32 s4, v3
+; GFX9-NEXT: v_readfirstlane_b32 s5, v2
+; GFX9-NEXT: s_mov_b32 s7, s6
+; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
+; GFX9-NEXT: s_sub_u32 s7, s4, s6
+; GFX9-NEXT: s_subb_u32 s16, s5, s6
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s11, v0
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s12, v0
+; GFX9-NEXT: s_cselect_b32 s20, 0, s7
+; GFX9-NEXT: s_and_b64 s[6:7], s[4:5], exec
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX9-NEXT: s_cselect_b32 s26, -1, s20
+; GFX9-NEXT: s_and_b64 s[20:21], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s26, 0, s26
+; GFX9-NEXT: s_and_b64 s[20:21], vcc, exec
+; GFX9-NEXT: s_cselect_b32 s16, 0x80000000, s16
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX9-NEXT: s_cselect_b32 s16, 0x7fffffff, s16
+; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s20, 0, s16
; GFX9-NEXT: s_lshr_b32 s4, s17, 16
-; GFX9-NEXT: v_cvt_f32_f16_e32 v1, s4
+; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v9, s22
+; GFX9-NEXT: v_mov_b32_e32 v12, s25
+; GFX9-NEXT: v_mov_b32_e32 v13, s24
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mul_f32_e64 v2, |v1|, s9
+; GFX9-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-NEXT: v_fma_f32 v3, v2, s10, |v1|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s6, v1
+; GFX9-NEXT: s_ashr_i32 s6, s6, 31
+; GFX9-NEXT: v_readfirstlane_b32 s4, v3
+; GFX9-NEXT: v_readfirstlane_b32 s5, v2
+; GFX9-NEXT: s_mov_b32 s7, s6
+; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
+; GFX9-NEXT: s_sub_u32 s7, s4, s6
+; GFX9-NEXT: s_subb_u32 s21, s5, s6
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s11, v0
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s12, v0
+; GFX9-NEXT: s_cselect_b32 s16, 0, s7
+; GFX9-NEXT: s_and_b64 s[6:7], s[4:5], exec
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX9-NEXT: s_cselect_b32 s27, -1, s16
+; GFX9-NEXT: s_and_b64 s[16:17], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s27, 0, s27
+; GFX9-NEXT: s_and_b64 s[16:17], vcc, exec
+; GFX9-NEXT: s_cselect_b32 s16, 0x80000000, s21
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX9-NEXT: s_cselect_b32 s16, 0x7fffffff, s16
+; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s21, 0, s16
; GFX9-NEXT: s_lshr_b32 s4, s18, 16
-; GFX9-NEXT: v_cvt_f32_f16_e32 v3, s4
+; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v6, s27
+; GFX9-NEXT: v_mov_b32_e32 v7, s21
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mul_f32_e64 v2, |v1|, s9
+; GFX9-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-NEXT: v_fma_f32 v3, v2, s10, |v1|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s6, v1
+; GFX9-NEXT: s_ashr_i32 s6, s6, 31
+; GFX9-NEXT: v_readfirstlane_b32 s4, v3
+; GFX9-NEXT: v_readfirstlane_b32 s5, v2
+; GFX9-NEXT: s_mov_b32 s7, s6
+; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
+; GFX9-NEXT: s_sub_u32 s7, s4, s6
+; GFX9-NEXT: s_subb_u32 s18, s5, s6
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s11, v0
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s12, v0
+; GFX9-NEXT: s_cselect_b32 s16, 0, s7
+; GFX9-NEXT: s_and_b64 s[6:7], s[4:5], exec
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX9-NEXT: s_cselect_b32 s28, -1, s16
+; GFX9-NEXT: s_and_b64 s[16:17], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s28, 0, s28
+; GFX9-NEXT: s_and_b64 s[16:17], vcc, exec
+; GFX9-NEXT: s_cselect_b32 s16, 0x80000000, s18
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX9-NEXT: s_cselect_b32 s16, 0x7fffffff, s16
+; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s16, 0, s16
; GFX9-NEXT: s_lshr_b32 s4, s19, 16
-; GFX9-NEXT: v_cvt_f32_f16_e32 v4, s4
-; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v0
-; GFX9-NEXT: v_cvt_i32_f32_e32 v6, v1
-; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s16
-; GFX9-NEXT: v_cvt_f32_f16_e32 v1, s17
-; GFX9-NEXT: v_cvt_f32_f16_e32 v5, s18
-; GFX9-NEXT: v_cvt_f32_f16_e32 v9, s19
-; GFX9-NEXT: v_cvt_i32_f32_e32 v10, v3
-; GFX9-NEXT: v_cvt_i32_f32_e32 v14, v4
-; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX9-NEXT: v_cvt_i32_f32_e32 v8, v5
-; GFX9-NEXT: v_cvt_i32_f32_e32 v12, v9
-; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX9-NEXT: v_ashrrev_i32_e32 v11, 31, v10
-; GFX9-NEXT: v_ashrrev_i32_e32 v15, 31, v14
-; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX9-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX9-NEXT: v_ashrrev_i32_e32 v9, 31, v8
-; GFX9-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v10, s28
+; GFX9-NEXT: v_mov_b32_e32 v11, s16
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mul_f32_e64 v2, |v1|, s9
+; GFX9-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-NEXT: v_fma_f32 v3, v2, s10, |v1|
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s6, v1
+; GFX9-NEXT: s_ashr_i32 s6, s6, 31
+; GFX9-NEXT: v_readfirstlane_b32 s4, v3
+; GFX9-NEXT: v_readfirstlane_b32 s5, v2
+; GFX9-NEXT: s_mov_b32 s7, s6
+; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
+; GFX9-NEXT: s_sub_u32 s7, s4, s6
+; GFX9-NEXT: s_subb_u32 s9, s5, s6
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, s11, v0
+; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s12, v0
+; GFX9-NEXT: s_cselect_b32 s10, 0, s7
+; GFX9-NEXT: s_and_b64 s[6:7], s[4:5], exec
+; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], v0, v0
+; GFX9-NEXT: s_cselect_b32 s12, -1, s10
+; GFX9-NEXT: s_and_b64 s[10:11], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s12, 0, s12
+; GFX9-NEXT: s_and_b64 s[10:11], vcc, exec
+; GFX9-NEXT: s_cselect_b32 s9, 0x80000000, s9
+; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX9-NEXT: s_cselect_b32 s9, 0x7fffffff, s9
+; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], exec
+; GFX9-NEXT: s_cselect_b32 s4, 0, s9
+; GFX9-NEXT: v_mov_b32_e32 v0, s8
+; GFX9-NEXT: v_mov_b32_e32 v1, s13
+; GFX9-NEXT: v_mov_b32_e32 v2, s26
+; GFX9-NEXT: v_mov_b32_e32 v3, s20
+; GFX9-NEXT: v_mov_b32_e32 v14, s12
+; GFX9-NEXT: v_mov_b32_e32 v15, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_signed_v8f16_v8i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: s_lshr_b32 s4, s0, 16
-; GFX11-NEXT: s_lshr_b32 s5, s1, 16
-; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s4
-; GFX11-NEXT: v_cvt_f32_f16_e32 v1, s5
-; GFX11-NEXT: s_lshr_b32 s4, s2, 16
-; GFX11-NEXT: v_cvt_f32_f16_e32 v4, s1
-; GFX11-NEXT: v_cvt_f32_f16_e32 v3, s4
-; GFX11-NEXT: s_lshr_b32 s4, s3, 16
-; GFX11-NEXT: v_cvt_i32_f32_e32 v2, v0
-; GFX11-NEXT: v_cvt_i32_f32_e32 v6, v1
-; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s4
-; GFX11-NEXT: v_cvt_f32_f16_e32 v1, s0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v5, s2
-; GFX11-NEXT: v_cvt_f32_f16_e32 v9, s3
-; GFX11-NEXT: v_cvt_i32_f32_e32 v10, v3
-; GFX11-NEXT: v_cvt_i32_f32_e32 v14, v0
-; GFX11-NEXT: v_cvt_i32_f32_e32 v0, v1
-; GFX11-NEXT: v_cvt_i32_f32_e32 v4, v4
-; GFX11-NEXT: v_cvt_i32_f32_e32 v8, v5
-; GFX11-NEXT: v_cvt_i32_f32_e32 v12, v9
-; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX11-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX11-NEXT: v_ashrrev_i32_e32 v11, 31, v10
-; GFX11-NEXT: v_ashrrev_i32_e32 v15, 31, v14
-; GFX11-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX11-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX11-NEXT: v_ashrrev_i32_e32 v9, 31, v8
-; GFX11-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s0
+; GFX11-NEXT: v_cvt_f32_f16_e32 v2, s1
+; GFX11-NEXT: v_cvt_f32_f16_e32 v3, s2
+; GFX11-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX11-NEXT: v_cmp_lt_f32_e64 s4, 0x5effffff, v0
+; GFX11-NEXT: v_cmp_u_f32_e64 s5, v0, v0
+; GFX11-NEXT: v_trunc_f32_e32 v5, v2
+; GFX11-NEXT: v_mul_f32_e64 v4, 0x2f800000, |v1|
+; GFX11-NEXT: v_readfirstlane_b32 s7, v1
+; GFX11-NEXT: v_trunc_f32_e32 v6, v3
+; GFX11-NEXT: v_cmp_nle_f32_e64 s6, 0xdf000000, v2
+; GFX11-NEXT: v_readfirstlane_b32 s14, v5
+; GFX11-NEXT: v_floor_f32_e32 v0, v4
+; GFX11-NEXT: v_mul_f32_e64 v4, 0x2f800000, |v5|
+; GFX11-NEXT: s_ashr_i32 s8, s7, 31
+; GFX11-NEXT: v_mul_f32_e64 v7, 0x2f800000, |v6|
+; GFX11-NEXT: s_mov_b32 s9, s8
+; GFX11-NEXT: v_fma_f32 v1, 0xcf800000, v0, |v1|
+; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-NEXT: v_floor_f32_e32 v4, v4
+; GFX11-NEXT: v_floor_f32_e32 v7, v7
+; GFX11-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX11-NEXT: v_readfirstlane_b32 s11, v0
+; GFX11-NEXT: v_fma_f32 v5, 0xcf800000, v4, |v5|
+; GFX11-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX11-NEXT: v_readfirstlane_b32 s10, v1
+; GFX11-NEXT: v_fma_f32 v1, 0xcf800000, v7, |v6|
+; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v5
+; GFX11-NEXT: v_readfirstlane_b32 s13, v4
+; GFX11-NEXT: s_xor_b64 s[10:11], s[10:11], s[8:9]
+; GFX11-NEXT: v_readfirstlane_b32 s12, v0
+; GFX11-NEXT: s_sub_u32 s7, s10, s8
+; GFX11-NEXT: s_subb_u32 s8, s11, s8
+; GFX11-NEXT: s_and_b32 s9, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s7, 0, s7
+; GFX11-NEXT: s_and_b32 s9, s4, exec_lo
+; GFX11-NEXT: s_cselect_b32 s7, -1, s7
+; GFX11-NEXT: s_and_b32 s9, s5, exec_lo
+; GFX11-NEXT: s_cselect_b32 s7, 0, s7
+; GFX11-NEXT: s_and_b32 s9, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s8, 0x80000000, s8
+; GFX11-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX11-NEXT: s_cselect_b32 s4, 0x7fffffff, s8
+; GFX11-NEXT: s_and_b32 s5, s5, exec_lo
+; GFX11-NEXT: s_cselect_b32 s8, 0, s4
+; GFX11-NEXT: s_ashr_i32 s10, s14, 31
+; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v2
+; GFX11-NEXT: s_mov_b32 s11, s10
+; GFX11-NEXT: v_cmp_u_f32_e64 s4, v2, v2
+; GFX11-NEXT: s_xor_b64 s[12:13], s[12:13], s[10:11]
+; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v1
+; GFX11-NEXT: s_sub_u32 s5, s12, s10
+; GFX11-NEXT: s_subb_u32 s10, s13, s10
+; GFX11-NEXT: s_and_b32 s9, s6, exec_lo
+; GFX11-NEXT: s_cselect_b32 s5, 0, s5
+; GFX11-NEXT: s_and_b32 s9, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s5, -1, s5
+; GFX11-NEXT: s_and_b32 s9, s4, exec_lo
+; GFX11-NEXT: s_cselect_b32 s9, 0, s5
+; GFX11-NEXT: s_and_b32 s5, s6, exec_lo
+; GFX11-NEXT: s_cselect_b32 s5, 0x80000000, s10
+; GFX11-NEXT: s_and_b32 s6, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s5, 0x7fffffff, s5
+; GFX11-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX11-NEXT: v_cvt_u32_f32_e32 v1, v7
+; GFX11-NEXT: v_readfirstlane_b32 s4, v0
+; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s3
+; GFX11-NEXT: v_readfirstlane_b32 s10, v6
+; GFX11-NEXT: s_cselect_b32 s6, 0, s5
+; GFX11-NEXT: v_readfirstlane_b32 s5, v1
+; GFX11-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v3
+; GFX11-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-NEXT: s_ashr_i32 s10, s10, 31
+; GFX11-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s6
+; GFX11-NEXT: s_mov_b32 s11, s10
+; GFX11-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX11-NEXT: s_xor_b64 s[4:5], s[4:5], s[10:11]
+; GFX11-NEXT: s_sub_u32 s11, s4, s10
+; GFX11-NEXT: s_subb_u32 s12, s5, s10
+; GFX11-NEXT: v_floor_f32_e32 v2, v2
+; GFX11-NEXT: v_cmp_lt_f32_e64 s4, 0x5effffff, v3
+; GFX11-NEXT: s_and_b32 s5, vcc_lo, exec_lo
+; GFX11-NEXT: v_cmp_u_f32_e64 s5, v3, v3
+; GFX11-NEXT: s_cselect_b32 s10, 0, s11
+; GFX11-NEXT: v_fma_f32 v3, 0xcf800000, v2, |v1|
+; GFX11-NEXT: s_and_b32 s11, s4, exec_lo
+; GFX11-NEXT: s_cselect_b32 s10, -1, s10
+; GFX11-NEXT: s_and_b32 s11, s5, exec_lo
+; GFX11-NEXT: s_cselect_b32 s10, 0, s10
+; GFX11-NEXT: s_and_b32 s11, vcc_lo, exec_lo
+; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX11-NEXT: s_cselect_b32 s11, 0x80000000, s12
+; GFX11-NEXT: v_readfirstlane_b32 s12, v1
+; GFX11-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX11-NEXT: s_cselect_b32 s4, 0x7fffffff, s11
+; GFX11-NEXT: s_and_b32 s5, s5, exec_lo
+; GFX11-NEXT: s_cselect_b32 s11, 0, s4
+; GFX11-NEXT: v_readfirstlane_b32 s4, v3
+; GFX11-NEXT: v_readfirstlane_b32 s5, v2
+; GFX11-NEXT: s_ashr_i32 s12, s12, 31
+; GFX11-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX11-NEXT: s_mov_b32 s13, s12
+; GFX11-NEXT: v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, s11
+; GFX11-NEXT: s_xor_b64 s[4:5], s[4:5], s[12:13]
+; GFX11-NEXT: s_sub_u32 s13, s4, s12
+; GFX11-NEXT: v_cmp_lt_f32_e64 s4, 0x5effffff, v0
+; GFX11-NEXT: s_subb_u32 s12, s5, s12
+; GFX11-NEXT: v_cmp_u_f32_e64 s5, v0, v0
+; GFX11-NEXT: s_and_b32 s14, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s13, 0, s13
+; GFX11-NEXT: s_and_b32 s14, s4, exec_lo
+; GFX11-NEXT: s_cselect_b32 s13, -1, s13
+; GFX11-NEXT: s_and_b32 s14, s5, exec_lo
+; GFX11-NEXT: s_cselect_b32 s16, 0, s13
+; GFX11-NEXT: s_and_b32 s13, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s12, 0x80000000, s12
+; GFX11-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX11-NEXT: s_cselect_b32 s4, 0x7fffffff, s12
+; GFX11-NEXT: s_and_b32 s5, s5, exec_lo
+; GFX11-NEXT: s_cselect_b32 s17, 0, s4
+; GFX11-NEXT: s_lshr_b32 s0, s0, 16
+; GFX11-NEXT: v_mov_b32_e32 v13, s17
+; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s0
+; GFX11-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX11-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX11-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11-NEXT: v_floor_f32_e32 v2, v2
+; GFX11-NEXT: s_ashr_i32 s12, s0, 31
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v0
+; GFX11-NEXT: s_mov_b32 s13, s12
+; GFX11-NEXT: v_fma_f32 v3, 0xcf800000, v2, |v1|
+; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-NEXT: v_readfirstlane_b32 s5, v2
+; GFX11-NEXT: v_readfirstlane_b32 s4, v3
+; GFX11-NEXT: s_xor_b64 s[14:15], s[4:5], s[12:13]
+; GFX11-NEXT: v_cmp_u_f32_e64 s4, v0, v0
+; GFX11-NEXT: s_sub_u32 s5, s14, s12
+; GFX11-NEXT: s_subb_u32 s12, s15, s12
+; GFX11-NEXT: s_and_b32 s13, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s5, 0, s5
+; GFX11-NEXT: s_and_b32 s13, s0, exec_lo
+; GFX11-NEXT: s_cselect_b32 s5, -1, s5
+; GFX11-NEXT: s_and_b32 s13, s4, exec_lo
+; GFX11-NEXT: s_cselect_b32 s14, 0, s5
+; GFX11-NEXT: s_and_b32 s5, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s5, 0x80000000, s12
+; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-NEXT: s_cselect_b32 s0, 0x7fffffff, s5
+; GFX11-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX11-NEXT: s_cselect_b32 s15, 0, s0
+; GFX11-NEXT: s_lshr_b32 s0, s1, 16
+; GFX11-NEXT: v_mov_b32_e32 v12, s16
+; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s0
+; GFX11-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX11-NEXT: v_cmp_u_f32_e64 s1, v0, v0
+; GFX11-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX11-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11-NEXT: v_floor_f32_e32 v2, v2
+; GFX11-NEXT: s_ashr_i32 s12, s0, 31
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v0
+; GFX11-NEXT: s_mov_b32 s13, s12
+; GFX11-NEXT: v_fma_f32 v3, 0xcf800000, v2, |v1|
+; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-NEXT: v_readfirstlane_b32 s5, v2
+; GFX11-NEXT: v_readfirstlane_b32 s4, v3
+; GFX11-NEXT: s_xor_b64 s[4:5], s[4:5], s[12:13]
+; GFX11-NEXT: s_sub_u32 s4, s4, s12
+; GFX11-NEXT: s_subb_u32 s5, s5, s12
+; GFX11-NEXT: s_and_b32 s12, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s4, 0, s4
+; GFX11-NEXT: s_and_b32 s12, s0, exec_lo
+; GFX11-NEXT: s_cselect_b32 s4, -1, s4
+; GFX11-NEXT: s_and_b32 s12, s1, exec_lo
+; GFX11-NEXT: s_cselect_b32 s18, 0, s4
+; GFX11-NEXT: s_and_b32 s4, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s4, 0x80000000, s5
+; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-NEXT: s_cselect_b32 s0, 0x7fffffff, s4
+; GFX11-NEXT: s_and_b32 s1, s1, exec_lo
+; GFX11-NEXT: s_cselect_b32 s19, 0, s0
+; GFX11-NEXT: s_lshr_b32 s0, s2, 16
+; GFX11-NEXT: v_mov_b32_e32 v7, s19
+; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s0
+; GFX11-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX11-NEXT: v_cmp_u_f32_e64 s1, v0, v0
+; GFX11-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX11-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11-NEXT: v_floor_f32_e32 v2, v2
+; GFX11-NEXT: s_ashr_i32 s12, s0, 31
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v0
+; GFX11-NEXT: s_mov_b32 s13, s12
+; GFX11-NEXT: v_fma_f32 v3, 0xcf800000, v2, |v1|
+; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-NEXT: v_readfirstlane_b32 s5, v2
+; GFX11-NEXT: v_readfirstlane_b32 s4, v3
+; GFX11-NEXT: s_xor_b64 s[4:5], s[4:5], s[12:13]
+; GFX11-NEXT: s_sub_u32 s2, s4, s12
+; GFX11-NEXT: s_subb_u32 s4, s5, s12
+; GFX11-NEXT: s_and_b32 s5, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 0, s2
+; GFX11-NEXT: s_and_b32 s5, s0, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, -1, s2
+; GFX11-NEXT: s_and_b32 s5, s1, exec_lo
+; GFX11-NEXT: s_cselect_b32 s12, 0, s2
+; GFX11-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 0x80000000, s4
+; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-NEXT: s_cselect_b32 s0, 0x7fffffff, s2
+; GFX11-NEXT: s_and_b32 s1, s1, exec_lo
+; GFX11-NEXT: s_cselect_b32 s13, 0, s0
+; GFX11-NEXT: s_lshr_b32 s0, s3, 16
+; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v11, s13
+; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s0
+; GFX11-NEXT: v_mov_b32_e32 v10, s12
+; GFX11-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
+; GFX11-NEXT: v_cmp_u_f32_e64 s1, v0, v0
+; GFX11-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX11-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11-NEXT: v_floor_f32_e32 v2, v2
+; GFX11-NEXT: s_ashr_i32 s4, s0, 31
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x5effffff, v0
+; GFX11-NEXT: s_mov_b32 s5, s4
+; GFX11-NEXT: v_mov_b32_e32 v0, s7
+; GFX11-NEXT: v_fma_f32 v3, 0xcf800000, v2, |v1|
+; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX11-NEXT: v_mov_b32_e32 v1, s8
+; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-NEXT: v_readfirstlane_b32 s3, v2
+; GFX11-NEXT: v_mov_b32_e32 v2, s14
+; GFX11-NEXT: v_readfirstlane_b32 s2, v3
+; GFX11-NEXT: v_mov_b32_e32 v3, s15
+; GFX11-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
+; GFX11-NEXT: s_sub_u32 s2, s2, s4
+; GFX11-NEXT: s_subb_u32 s3, s3, s4
+; GFX11-NEXT: s_and_b32 s4, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 0, s2
+; GFX11-NEXT: s_and_b32 s4, s0, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, -1, s2
+; GFX11-NEXT: s_and_b32 s4, s1, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 0, s2
+; GFX11-NEXT: s_and_b32 s4, vcc_lo, exec_lo
+; GFX11-NEXT: s_cselect_b32 s3, 0x80000000, s3
+; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-NEXT: s_cselect_b32 s0, 0x7fffffff, s3
+; GFX11-NEXT: s_and_b32 s1, s1, exec_lo
+; GFX11-NEXT: s_cselect_b32 s0, 0, s0
+; GFX11-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v15, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_signed_v8f16_v8i64:
@@ -7547,41 +9759,258 @@ define <8 x i64> @test_s_signed_v8f16_v8i64(<8 x half> inreg %f) {
; GFX12-ISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s4, s0
-; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s5, s1
-; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s6, s2
-; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s7, s3
+; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s8, s0
+; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s10, s1
+; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s11, s2
+; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s13, s3
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_trunc_f32 s4, s8
; GFX12-ISEL-NEXT: s_cvt_f32_f16 s0, s0
-; GFX12-ISEL-NEXT: s_cvt_f32_f16 s1, s1
; GFX12-ISEL-NEXT: s_cvt_f32_f16 s2, s2
-; GFX12-ISEL-NEXT: s_cvt_f32_f16 s3, s3
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s4, s4
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s5, s5
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s6, s6
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s7, s7
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s0, s0
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s1, s1
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s2, s2
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s3, s3
+; GFX12-ISEL-NEXT: s_and_b32 s5, s4, 0x7fffffff
+; GFX12-ISEL-NEXT: s_ashr_i32 s4, s4, 31
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_mul_f32 s6, s5, 0x2f800000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_floor_f32 s6, s6
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s5, s6, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s7, s6
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s6, s5
+; GFX12-ISEL-NEXT: s_mov_b32 s5, s4
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s8, 0xdf000000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_sub_nc_u64 s[4:5], s[6:7], s[4:5]
+; GFX12-ISEL-NEXT: s_trunc_f32 s6, s10
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s4, 0, s4
+; GFX12-ISEL-NEXT: s_cselect_b32 s5, 0x80000000, s5
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s8, 0x5effffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s5, 0x7fffffff, s5
+; GFX12-ISEL-NEXT: s_cselect_b32 s4, -1, s4
+; GFX12-ISEL-NEXT: s_cmp_u_f32 s8, s8
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s4, 0, s4
+; GFX12-ISEL-NEXT: s_cselect_b32 s5, 0, s5
+; GFX12-ISEL-NEXT: s_and_b32 s7, s6, 0x7fffffff
+; GFX12-ISEL-NEXT: s_ashr_i32 s6, s6, 31
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_mul_f32 s8, s7, 0x2f800000
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_floor_f32 s8, s8
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s7, s8, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s9, s8
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s8, s7
+; GFX12-ISEL-NEXT: s_mov_b32 s7, s6
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_xor_b64 s[8:9], s[8:9], s[6:7]
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s10, 0xdf000000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_sub_nc_u64 s[6:7], s[8:9], s[6:7]
+; GFX12-ISEL-NEXT: s_trunc_f32 s8, s11
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s6, 0, s6
+; GFX12-ISEL-NEXT: s_cselect_b32 s7, 0x80000000, s7
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s10, 0x5effffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s7, 0x7fffffff, s7
+; GFX12-ISEL-NEXT: s_cselect_b32 s6, -1, s6
+; GFX12-ISEL-NEXT: s_cmp_u_f32 s10, s10
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s10, 0, s6
+; GFX12-ISEL-NEXT: s_cselect_b32 s12, 0, s7
+; GFX12-ISEL-NEXT: s_and_b32 s7, s8, 0x7fffffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s12
+; GFX12-ISEL-NEXT: s_mul_f32 s6, s7, 0x2f800000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_floor_f32 s9, s6
+; GFX12-ISEL-NEXT: s_ashr_i32 s6, s8, 31
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s7, s9, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s9, s9
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s8, s7
+; GFX12-ISEL-NEXT: s_mov_b32 s7, s6
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_xor_b64 s[8:9], s[8:9], s[6:7]
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s11, 0xdf000000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_sub_nc_u64 s[6:7], s[8:9], s[6:7]
+; GFX12-ISEL-NEXT: s_trunc_f32 s8, s13
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s6, 0, s6
+; GFX12-ISEL-NEXT: s_cselect_b32 s7, 0x80000000, s7
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s11, 0x5effffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s7, 0x7fffffff, s7
+; GFX12-ISEL-NEXT: s_cselect_b32 s6, -1, s6
+; GFX12-ISEL-NEXT: s_cmp_u_f32 s11, s11
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s11, 0, s6
+; GFX12-ISEL-NEXT: s_cselect_b32 s14, 0, s7
+; GFX12-ISEL-NEXT: s_and_b32 s7, s8, 0x7fffffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v10, s11 :: v_dual_mov_b32 v11, s14
+; GFX12-ISEL-NEXT: s_mul_f32 s6, s7, 0x2f800000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_floor_f32 s9, s6
+; GFX12-ISEL-NEXT: s_ashr_i32 s6, s8, 31
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s7, s9, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s9, s9
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s8, s7
+; GFX12-ISEL-NEXT: s_mov_b32 s7, s6
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_xor_b64 s[8:9], s[8:9], s[6:7]
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s13, 0xdf000000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_sub_nc_u64 s[6:7], s[8:9], s[6:7]
+; GFX12-ISEL-NEXT: s_trunc_f32 s8, s0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s6, 0, s6
+; GFX12-ISEL-NEXT: s_cselect_b32 s7, 0x80000000, s7
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s13, 0x5effffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s7, 0x7fffffff, s7
+; GFX12-ISEL-NEXT: s_cselect_b32 s6, -1, s6
+; GFX12-ISEL-NEXT: s_cmp_u_f32 s13, s13
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s13, 0, s6
+; GFX12-ISEL-NEXT: s_cselect_b32 s15, 0, s7
+; GFX12-ISEL-NEXT: s_and_b32 s7, s8, 0x7fffffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_mov_b32_e32 v15, s15
+; GFX12-ISEL-NEXT: s_mul_f32 s6, s7, 0x2f800000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_floor_f32 s9, s6
+; GFX12-ISEL-NEXT: s_ashr_i32 s6, s8, 31
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s7, s9, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s9, s9
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s8, s7
+; GFX12-ISEL-NEXT: s_mov_b32 s7, s6
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_xor_b64 s[8:9], s[8:9], s[6:7]
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s0, 0xdf000000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_sub_nc_u64 s[6:7], s[8:9], s[6:7]
+; GFX12-ISEL-NEXT: s_cvt_f32_f16 s8, s1
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s6, 0, s6
+; GFX12-ISEL-NEXT: s_cselect_b32 s7, 0x80000000, s7
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s0, 0x5effffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, 0x7fffffff, s7
+; GFX12-ISEL-NEXT: s_cselect_b32 s6, -1, s6
+; GFX12-ISEL-NEXT: s_cmp_u_f32 s0, s0
+; GFX12-ISEL-NEXT: s_trunc_f32 s0, s8
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s9, 0, s6
+; GFX12-ISEL-NEXT: s_cselect_b32 s16, 0, s1
+; GFX12-ISEL-NEXT: s_and_b32 s1, s0, 0x7fffffff
+; GFX12-ISEL-NEXT: s_ashr_i32 s0, s0, 31
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_mul_f32 s6, s1, 0x2f800000
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v14, s13 :: v_dual_mov_b32 v1, s16
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_floor_f32 s6, s6
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s1, s6, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s7, s6
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s6, s1
+; GFX12-ISEL-NEXT: s_mov_b32 s1, s0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1]
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s8, 0xdf000000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_sub_nc_u64 s[0:1], s[6:7], s[0:1]
+; GFX12-ISEL-NEXT: s_trunc_f32 s6, s2
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s0, 0, s0
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, 0x80000000, s1
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s8, 0x5effffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, 0x7fffffff, s1
+; GFX12-ISEL-NEXT: s_cselect_b32 s0, -1, s0
+; GFX12-ISEL-NEXT: s_cmp_u_f32 s8, s8
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s8, 0, s0
+; GFX12-ISEL-NEXT: s_cselect_b32 s17, 0, s1
+; GFX12-ISEL-NEXT: s_and_b32 s1, s6, 0x7fffffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v0, s9 :: v_dual_mov_b32 v5, s17
+; GFX12-ISEL-NEXT: s_mul_f32 s0, s1, 0x2f800000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_floor_f32 s7, s0
+; GFX12-ISEL-NEXT: s_ashr_i32 s0, s6, 31
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s1, s7, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s7, s7
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s6, s1
+; GFX12-ISEL-NEXT: s_mov_b32 s1, s0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1]
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s2, 0xdf000000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_sub_nc_u64 s[0:1], s[6:7], s[0:1]
+; GFX12-ISEL-NEXT: s_cvt_f32_f16 s6, s3
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s0, 0, s0
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, 0x80000000, s1
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s2, 0x5effffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, 0x7fffffff, s1
+; GFX12-ISEL-NEXT: s_cselect_b32 s0, -1, s0
+; GFX12-ISEL-NEXT: s_cmp_u_f32 s2, s2
+; GFX12-ISEL-NEXT: s_trunc_f32 s2, s6
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s7, 0, s0
+; GFX12-ISEL-NEXT: s_cselect_b32 s18, 0, s1
+; GFX12-ISEL-NEXT: s_and_b32 s1, s2, 0x7fffffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v9, s18
+; GFX12-ISEL-NEXT: s_mul_f32 s0, s1, 0x2f800000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_floor_f32 s3, s0
+; GFX12-ISEL-NEXT: s_ashr_i32 s0, s2, 31
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s1, s3, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s3, s3
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s2, s1
+; GFX12-ISEL-NEXT: s_mov_b32 s1, s0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1]
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s6, 0xdf000000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_sub_nc_u64 s[0:1], s[2:3], s[0:1]
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s0, 0, s0
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, 0x80000000, s1
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s6, 0x5effffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, 0x7fffffff, s1
+; GFX12-ISEL-NEXT: s_cselect_b32 s0, -1, s0
+; GFX12-ISEL-NEXT: s_cmp_u_f32 s6, s6
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: s_ashr_i32 s8, s4, 31
-; GFX12-ISEL-NEXT: s_ashr_i32 s9, s5, 31
-; GFX12-ISEL-NEXT: s_ashr_i32 s10, s6, 31
-; GFX12-ISEL-NEXT: s_ashr_i32 s11, s7, 31
-; GFX12-ISEL-NEXT: s_ashr_i32 s12, s0, 31
-; GFX12-ISEL-NEXT: s_ashr_i32 s13, s1, 31
-; GFX12-ISEL-NEXT: s_ashr_i32 s14, s2, 31
-; GFX12-ISEL-NEXT: s_ashr_i32 s15, s3, 31
+; GFX12-ISEL-NEXT: s_cselect_b32 s0, 0, s0
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, 0, s1
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s12
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s8
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v5, s13
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v7, s9
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s14
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v10, s6 :: v_dual_mov_b32 v11, s10
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v12, s3 :: v_dual_mov_b32 v13, s15
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v14, s7 :: v_dual_mov_b32 v15, s11
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v8, s7 :: v_dual_mov_b32 v13, s1
+; GFX12-ISEL-NEXT: v_mov_b32_e32 v12, s0
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_v8f16_v8i64:
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
index ec58b0090e5a4..5711bc35ed00b 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
@@ -1513,8 +1513,13 @@ define i64 @test_unsigned_i64_f16(half %f) nounwind {
; GFX7-ISEL: ; %bb.0:
; GFX7-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX7-ISEL-NEXT: s_mov_b32 s4, 0x5f7fffff
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v1, v0
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v0
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v1, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_unsigned_i64_f16:
@@ -1541,24 +1546,56 @@ define i64 @test_unsigned_i64_f16(half %f) nounwind {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: s_mov_b32 s5, 0xcf800000
+; GFX9-NEXT: s_mov_b32 s4, 0x5f7fffff
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
+; GFX9-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-NEXT: v_fma_f32 v1, v2, s5, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v1
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s4, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_unsigned_i64_f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: v_fmamk_f32 v1, v2, 0xcf800000, v1
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v1, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v2, -1, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v3, -1, vcc_lo
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: test_unsigned_i64_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v0
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: v_fmamk_f32 v1, v2, 0xcf800000, v1
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, v1, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v2, -1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v3, -1, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_unsigned_i64_f16:
@@ -1569,8 +1606,20 @@ define i64 @test_unsigned_i64_f16(half %f) nounwind {
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v1, v0
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v0
+; GFX12-FAKE16-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v2, v2
+; GFX12-FAKE16-NEXT: v_fmamk_f32 v1, v2, 0xcf800000, v1
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v1, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v2, -1, vcc_lo
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v3, -1, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_unsigned_i64_f16:
@@ -1581,8 +1630,20 @@ define i64 @test_unsigned_i64_f16(half %f) nounwind {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v1, v0
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v0
+; GFX12-TRUE16-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v2, v2
+; GFX12-TRUE16-NEXT: v_fmamk_f32 v1, v2, 0xcf800000, v1
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v3, v1, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, v2, -1, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, v3, -1, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_unsigned_i64_f16:
@@ -1888,8 +1949,13 @@ define i64 @test_s_unsigned_i64_f16(half inreg %f) nounwind {
; GFX7-ISEL: ; %bb.0:
; GFX7-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v0, s16
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX7-ISEL-NEXT: s_mov_b32 s4, 0x5f7fffff
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v1, v0
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v0
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v1, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_s_unsigned_i64_f16:
@@ -1920,16 +1986,38 @@ define i64 @test_s_unsigned_i64_f16(half inreg %f) nounwind {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s16
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: s_mov_b32 s5, 0xcf800000
+; GFX9-NEXT: s_mov_b32 s4, 0x5f7fffff
+; GFX9-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
+; GFX9-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-NEXT: v_fma_f32 v1, v2, s5, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v1
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s4, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_unsigned_i64_f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s0
-; GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
+; GFX11-NEXT: v_floor_f32_e32 v2, v2
+; GFX11-NEXT: v_fmamk_f32 v1, v2, 0xcf800000, v1
+; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX11-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v1, 0, vcc_lo
+; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, -1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v3, -1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_unsigned_i64_f16:
@@ -1940,11 +2028,27 @@ define i64 @test_s_unsigned_i64_f16(half inreg %f) nounwind {
; GFX12-ISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT: s_cvt_f32_f16 s0, s0
-; GFX12-ISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: s_cvt_u32_f32 s0, s0
+; GFX12-ISEL-NEXT: s_trunc_f32 s1, s0
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s0, 0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_mul_f32 s2, s1, 0x2f800000
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-ISEL-NEXT: s_floor_f32 s2, s2
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s1, s2, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s2, s2
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s1, s1
+; GFX12-ISEL-NEXT: s_cselect_b32 s2, 0, s2
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, 0, s1
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s0, 0x5f7fffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s0, -1, s1
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, -1, s2
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_unsigned_i64_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
index c1afbd5d2aa8e..f0a50d3bf3b55 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
@@ -2898,20 +2898,37 @@ define <4 x i64> @test_unsigned_v4f16_v4i64(<4 x half> %f) {
; GFX7-ISEL-LABEL: test_unsigned_v4f16_v4i64:
; GFX7-ISEL: ; %bb.0:
; GFX7-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v5, v2
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v4, v1
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v2, v3
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v6, v5
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v5, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v7, 0
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v6, v1
+; GFX7-ISEL-NEXT: s_mov_b32 s4, 0x5f7fffff
+; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v4, v2
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v2
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v7, v5
+; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v2
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v2, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v6
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v6, v3
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v4, v2, -1, vcc
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v2, v7
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v8, v6
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v7
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v7
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v7, v8, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v6, v7, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_unsigned_v4f16_v4i64:
@@ -2981,54 +2998,173 @@ define <4 x i64> @test_unsigned_v4f16_v4i64(<4 x half> %f) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: s_mov_b32 s10, 0x5f7fffff
+; GFX9-NEXT: s_mov_b32 s11, 0xcf800000
+; GFX9-NEXT: v_trunc_f32_e32 v4, v2
+; GFX9-NEXT: v_trunc_f32_e32 v7, v3
+; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
+; GFX9-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7
+; GFX9-NEXT: v_floor_f32_e32 v6, v5
+; GFX9-NEXT: v_floor_f32_e32 v9, v8
+; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v10, v9
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, 0, v2
+; GFX9-NEXT: v_cmp_nle_f32_e64 s[6:7], 0, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s10, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v10, 0, s[6:7]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[8:9], s10, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v5, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v2, -1, s[8:9]
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_fma_f32 v0, v6, s11, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v2
-; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v3
-; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v5
-; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v1
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_mov_b32_e32 v3, 0
-; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: v_mov_b32_e32 v7, 0
+; GFX9-NEXT: v_trunc_f32_e32 v6, v2
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x2f800000, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, 0, v2
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s10, v2
+; GFX9-NEXT: v_fma_f32 v2, v9, s11, v7
+; GFX9-NEXT: v_trunc_f32_e32 v7, v1
+; GFX9-NEXT: v_floor_f32_e32 v10, v3
+; GFX9-NEXT: v_mul_f32_e32 v4, 0x2f800000, v7
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_floor_f32_e32 v9, v4
+; GFX9-NEXT: v_fma_f32 v6, v10, s11, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v11, v9
+; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX9-NEXT: v_fma_f32 v7, v9, s11, v7
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v10
+; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[6:7]
+; GFX9-NEXT: v_cmp_nle_f32_e64 s[6:7], 0, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v2, -1, s[8:9]
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v11, 0, s[6:7]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[8:9], s10, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v6, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v2, -1, s[8:9]
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v1, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v9, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v1, -1, s[8:9]
+; GFX9-NEXT: v_mov_b32_e32 v1, v8
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_unsigned_v4f16_v4i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v4, v2
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v3
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, 0
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v4, v1
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v6, v3
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, 0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v1
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v2
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v1, 0x2f800000, v4
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, 0x5f7fffff, v2
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v0
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v7
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v5, 0x2f800000, v6
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e64 s0, 0, v3
+; GFX11-FAKE16-NEXT: v_dual_mul_f32 v10, 0x2f800000, v8 :: v_dual_mul_f32 v11, 0x2f800000, v9
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v12, v1
+; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v4, 0xcf800000, v1
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v1, v10
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v10, v11
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v13, v5
+; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v6, 0xcf800000, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v12, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_dual_fmac_f32 v8, 0xcf800000, v1 :: v_dual_fmac_f32 v9, 0xcf800000, v10
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v12, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v5, -1, s1
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e64 s2, 0, v0
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, 0x5f7fffff, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v4, v10
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v13, 0, s0
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v12, 0, s2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v2, -1, s1
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v2, v6
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v6, v8
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e64 s1, 0, v7
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v8, v9
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v11, -1, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, 0, s2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, v4, 0, s1
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5f7fffff, v7
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, 0, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, -1, s3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v2, -1, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v6, -1, s3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v9, -1, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, v8, -1, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: test_unsigned_v4f16_v4i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v4, v2
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v3
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 0
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v1
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v3
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, 0
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v2
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v1, 0x2f800000, v4
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, 0x5f7fffff, v2
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v0
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v7
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, 0x2f800000, v6
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v1, v1
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e64 s0, 0, v3
+; GFX11-TRUE16-NEXT: v_dual_mul_f32 v10, 0x2f800000, v8 :: v_dual_mul_f32 v11, 0x2f800000, v9
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v12, v1
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v4, 0xcf800000, v1
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v1, v10
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v10, v11
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v13, v5
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v6, 0xcf800000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v12, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_fmac_f32 v8, 0xcf800000, v1 :: v_dual_fmac_f32 v9, 0xcf800000, v10
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v12, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v5, -1, s1
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e64 s2, 0, v0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, 0x5f7fffff, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, v13, 0, s0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, v12, 0, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v2, -1, s1
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v6
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v8
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e64 s1, 0, v7
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v11, -1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v6, 0, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, v4, 0, s1
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5f7fffff, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, v8, 0, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, v3, -1, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, v2, -1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v6, -1, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, v9, -1, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v8, -1, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_unsigned_v4f16_v4i64:
@@ -3038,20 +3174,64 @@ define <4 x i64> @test_unsigned_v4f16_v4i64(<4 x half> %f) {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v4, v2
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v6, v3
; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, 0
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v4, v1
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v6, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, 0
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v7, 0
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v1
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v2
+; GFX12-FAKE16-NEXT: v_mul_f32_e32 v1, 0x2f800000, v4
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s1, 0x5f7fffff, v2
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v8, v0
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v9, v7
+; GFX12-FAKE16-NEXT: v_mul_f32_e32 v5, 0x2f800000, v6
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v1, v1
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e64 s0, 0, v3
+; GFX12-FAKE16-NEXT: v_dual_mul_f32 v10, 0x2f800000, v8 :: v_dual_mul_f32 v11, 0x2f800000, v9
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v12, v1
+; GFX12-FAKE16-NEXT: v_fmac_f32_e32 v4, 0xcf800000, v1
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v1, v10
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v10, v11
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v13, v5
+; GFX12-FAKE16-NEXT: v_fmac_f32_e32 v6, 0xcf800000, v5
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v5, v12, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_dual_fmac_f32 v8, 0xcf800000, v1 :: v_dual_fmac_f32 v9, 0xcf800000, v10
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v12, v1
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v5, -1, s1
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e64 s2, 0, v0
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, 0x5f7fffff, v0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v4, v10
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v13, 0, s0
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v3
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v12, 0, s2
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v2, -1, s1
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v2, v6
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v6, v8
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e64 s1, 0, v7
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v8, v9
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v5, v11, -1, vcc_lo
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, 0, s2
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v9, v4, 0, s1
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5f7fffff, v7
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v8, 0, s1
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, -1, s3
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v2, -1, vcc_lo
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v6, -1, s3
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v7, v9, -1, s0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v6, v8, -1, s0
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_unsigned_v4f16_v4i64:
@@ -3061,20 +3241,64 @@ define <4 x i64> @test_unsigned_v4f16_v4i64(<4 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v1.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v4, v2
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v6, v3
; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, 0
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v1
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v3
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, 0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, 0
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v2
+; GFX12-TRUE16-NEXT: v_mul_f32_e32 v1, 0x2f800000, v4
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, 0x5f7fffff, v2
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v8, v0
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v9, v7
+; GFX12-TRUE16-NEXT: v_mul_f32_e32 v5, 0x2f800000, v6
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v1, v1
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e64 s0, 0, v3
+; GFX12-TRUE16-NEXT: v_dual_mul_f32 v10, 0x2f800000, v8 :: v_dual_mul_f32 v11, 0x2f800000, v9
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v5, v5
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v12, v1
+; GFX12-TRUE16-NEXT: v_fmac_f32_e32 v4, 0xcf800000, v1
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v1, v10
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v10, v11
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v13, v5
+; GFX12-TRUE16-NEXT: v_fmac_f32_e32 v6, 0xcf800000, v5
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v12, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_dual_fmac_f32 v8, 0xcf800000, v1 :: v_dual_fmac_f32 v9, 0xcf800000, v10
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v12, v1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, v5, -1, s1
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e64 s2, 0, v0
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, 0x5f7fffff, v0
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v10
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v11, v13, 0, s0
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v3
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v3, v12, 0, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, v2, -1, s1
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v8
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e64 s1, 0, v7
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v9
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v11, -1, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v6, 0, s2
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v9, v4, 0, s1
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5f7fffff, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v8, v8, 0, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v3, v3, -1, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v4, v2, -1, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, v6, -1, s3
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v7, v9, -1, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v8, -1, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_unsigned_v4f16_v4i64:
@@ -3724,20 +3948,37 @@ define <4 x i64> @test_s_unsigned_v4f16_v4i64(<4 x half> inreg %f) {
; GFX7-ISEL-LABEL: test_s_unsigned_v4f16_v4i64:
; GFX7-ISEL: ; %bb.0:
; GFX7-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-ISEL-NEXT: s_lshr_b32 s4, s17, 16
-; GFX7-ISEL-NEXT: s_lshr_b32 s5, s16, 16
; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v0, s16
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v1, s17
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v2, s5
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v3, s4
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v4, v1
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v6, v3
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v5, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v7, 0
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v2, s17
+; GFX7-ISEL-NEXT: s_lshr_b32 s6, s16, 16
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v6, s6
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v1, v0
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GFX7-ISEL-NEXT: s_mov_b32 s4, 0x5f7fffff
+; GFX7-ISEL-NEXT: s_lshr_b32 s5, s17, 16
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v0
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v7, s5
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v1, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v2
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v2
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v2, v6
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v8, v7
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v4, v3, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v7
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v6, v8, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v7
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v6, v6, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_s_unsigned_v4f16_v4i64:
@@ -3820,39 +4061,119 @@ define <4 x i64> @test_s_unsigned_v4f16_v4i64(<4 x half> inreg %f) {
; GFX9-LABEL: test_s_unsigned_v4f16_v4i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_lshr_b32 s4, s16, 16
-; GFX9-NEXT: v_cvt_f32_f16_e32 v2, s4
-; GFX9-NEXT: s_lshr_b32 s4, s17, 16
+; GFX9-NEXT: v_cvt_f32_f16_e32 v2, s17
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s16
-; GFX9-NEXT: v_cvt_f32_f16_e32 v1, s17
-; GFX9-NEXT: v_cvt_f32_f16_e32 v3, s4
-; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: s_mov_b32 s10, 0x5f7fffff
+; GFX9-NEXT: s_lshr_b32 s11, s16, 16
+; GFX9-NEXT: v_trunc_f32_e32 v6, v2
+; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v6
+; GFX9-NEXT: v_floor_f32_e32 v7, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v7
+; GFX9-NEXT: v_trunc_f32_e32 v3, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v3
+; GFX9-NEXT: v_cmp_nle_f32_e64 s[6:7], 0, v2
+; GFX9-NEXT: v_floor_f32_e32 v4, v1
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s10, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v5, 0, s[6:7]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[8:9], s10, v2
+; GFX9-NEXT: v_cvt_f32_f16_e32 v2, s11
+; GFX9-NEXT: s_mov_b32 s11, 0xcf800000
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v0, -1, s[8:9]
+; GFX9-NEXT: v_fma_f32 v0, v4, s11, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v4
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v3
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_mov_b32_e32 v3, 0
-; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: v_mov_b32_e32 v7, 0
+; GFX9-NEXT: v_trunc_f32_e32 v8, v2
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x2f800000, v8
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[4:5]
+; GFX9-NEXT: s_lshr_b32 s4, s17, 16
+; GFX9-NEXT: v_cvt_f32_f16_e32 v10, s4
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, 0, v2
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s10, v2
+; GFX9-NEXT: v_fma_f32 v2, v7, s11, v6
+; GFX9-NEXT: v_trunc_f32_e32 v6, v10
+; GFX9-NEXT: v_mul_f32_e32 v4, 0x2f800000, v6
+; GFX9-NEXT: v_floor_f32_e32 v9, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_floor_f32_e32 v7, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v11, v7
+; GFX9-NEXT: v_fma_f32 v8, v9, s11, v8
+; GFX9-NEXT: v_fma_f32 v6, v7, s11, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v9
+; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[6:7]
+; GFX9-NEXT: v_cmp_nle_f32_e64 s[6:7], 0, v10
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v2, -1, s[8:9]
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v11, 0, s[6:7]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[8:9], s10, v10
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v2, -1, s[8:9]
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, -1, s[8:9]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_unsigned_v4f16_v4i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: s_lshr_b32 s2, s0, 16
; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s0
-; GFX11-NEXT: s_lshr_b32 s0, s1, 16
-; GFX11-NEXT: v_cvt_f32_f16_e32 v1, s2
-; GFX11-NEXT: v_cvt_f32_f16_e32 v3, s1
-; GFX11-NEXT: v_cvt_f32_f16_e32 v5, s0
-; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: v_mov_b32_e32 v7, 0
-; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v1
-; GFX11-NEXT: v_cvt_u32_f32_e32 v4, v3
-; GFX11-NEXT: v_cvt_u32_f32_e32 v6, v5
-; GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-NEXT: v_mov_b32_e32 v3, 0
-; GFX11-NEXT: v_mov_b32_e32 v5, 0
+; GFX11-NEXT: v_cvt_f32_f16_e32 v2, s1
+; GFX11-NEXT: s_lshr_b32 s0, s0, 16
+; GFX11-NEXT: s_lshr_b32 s1, s1, 16
+; GFX11-NEXT: v_cvt_f32_f16_e32 v3, s0
+; GFX11-NEXT: v_cvt_f32_f16_e32 v4, s1
+; GFX11-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-NEXT: v_trunc_f32_e32 v6, v2
+; GFX11-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: v_trunc_f32_e32 v7, v3
+; GFX11-NEXT: v_trunc_f32_e32 v8, v4
+; GFX11-NEXT: v_mul_f32_e32 v5, 0x2f800000, v1
+; GFX11-NEXT: v_mul_f32_e32 v9, 0x2f800000, v6
+; GFX11-NEXT: v_cmp_nle_f32_e64 s1, 0, v2
+; GFX11-NEXT: v_dual_mul_f32 v10, 0x2f800000, v7 :: v_dual_mul_f32 v11, 0x2f800000, v8
+; GFX11-NEXT: v_floor_f32_e32 v5, v5
+; GFX11-NEXT: v_floor_f32_e32 v9, v9
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x5f7fffff, v0
+; GFX11-NEXT: v_floor_f32_e32 v10, v10
+; GFX11-NEXT: v_floor_f32_e32 v11, v11
+; GFX11-NEXT: v_fmac_f32_e32 v1, 0xcf800000, v5
+; GFX11-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX11-NEXT: v_cvt_u32_f32_e32 v12, v9
+; GFX11-NEXT: v_dual_fmac_f32 v6, 0xcf800000, v9 :: v_dual_fmac_f32 v7, 0xcf800000, v10
+; GFX11-NEXT: v_fmac_f32_e32 v8, 0xcf800000, v11
+; GFX11-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v12, 0, s1
+; GFX11-NEXT: v_cmp_lt_f32_e64 s2, 0x5f7fffff, v2
+; GFX11-NEXT: v_cvt_u32_f32_e32 v9, v10
+; GFX11-NEXT: v_cndmask_b32_e64 v12, v1, 0, vcc_lo
+; GFX11-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v3
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v0, -1, s2
+; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v6
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v12, -1, s0
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x5f7fffff, v3
+; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v11
+; GFX11-NEXT: v_cvt_u32_f32_e32 v6, v7
+; GFX11-NEXT: v_cmp_nle_f32_e64 s3, 0, v4
+; GFX11-NEXT: v_cvt_u32_f32_e32 v7, v8
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v3, 0, s3
+; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v4
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v7, 0, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v9, -1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v2, -1, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v6, -1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v8, -1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v10, -1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_unsigned_v4f16_v4i64:
@@ -3862,20 +4183,76 @@ define <4 x i64> @test_s_unsigned_v4f16_v4i64(<4 x half> inreg %f) {
; GFX12-ISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-ISEL-NEXT: s_cvt_f32_f16 s2, s0
-; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s0, s0
-; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s3, s1
+; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s2, s0
+; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s4, s1
+; GFX12-ISEL-NEXT: s_cvt_f32_f16 s0, s0
; GFX12-ISEL-NEXT: s_cvt_f32_f16 s1, s1
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: s_cvt_u32_f32 s2, s2
-; GFX12-ISEL-NEXT: s_cvt_u32_f32 s0, s0
+; GFX12-ISEL-NEXT: s_trunc_f32 s3, s2
+; GFX12-ISEL-NEXT: s_trunc_f32 s6, s4
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s2, 0
+; GFX12-ISEL-NEXT: s_trunc_f32 s8, s0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_mul_f32 s5, s3, 0x2f800000
+; GFX12-ISEL-NEXT: s_mul_f32 s7, s6, 0x2f800000
+; GFX12-ISEL-NEXT: s_mul_f32 s9, s8, 0x2f800000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_floor_f32 s5, s5
+; GFX12-ISEL-NEXT: s_floor_f32 s7, s7
+; GFX12-ISEL-NEXT: s_floor_f32 s9, s9
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s3, s5, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s5, s5
+; GFX12-ISEL-NEXT: s_fmac_f32 s6, s7, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s7, s7
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT: s_cvt_u32_f32 s3, s3
-; GFX12-ISEL-NEXT: s_cvt_u32_f32 s1, s1
+; GFX12-ISEL-NEXT: s_cselect_b32 s5, 0, s5
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s6, s6
+; GFX12-ISEL-NEXT: s_fmac_f32 s8, s9, 0xcf800000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s3, 0, s3
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s2, 0x5f7fffff
+; GFX12-ISEL-NEXT: s_trunc_f32 s2, s1
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s8, s8
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s9, s9
+; GFX12-ISEL-NEXT: s_cselect_b32 s5, -1, s5
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s3, -1, s3
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s4, 0
+; GFX12-ISEL-NEXT: s_mul_f32 s10, s2, 0x2f800000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v2, s3 :: v_dual_mov_b32 v3, s5
+; GFX12-ISEL-NEXT: s_cselect_b32 s6, 0, s6
+; GFX12-ISEL-NEXT: s_cselect_b32 s7, 0, s7
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s4, 0x5f7fffff
+; GFX12-ISEL-NEXT: s_floor_f32 s4, s10
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s7, -1, s7
+; GFX12-ISEL-NEXT: s_cselect_b32 s6, -1, s6
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s0, 0
+; GFX12-ISEL-NEXT: s_fmac_f32 s2, s4, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s4, s4
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
+; GFX12-ISEL-NEXT: s_cselect_b32 s8, 0, s8
+; GFX12-ISEL-NEXT: s_cselect_b32 s9, 0, s9
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s0, 0x5f7fffff
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s0, s2
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s2, -1, s9
+; GFX12-ISEL-NEXT: s_cselect_b32 s8, -1, s8
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s1, 0
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, 0
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v5, 0
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v7, 0
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s2
+; GFX12-ISEL-NEXT: s_cselect_b32 s0, 0, s0
+; GFX12-ISEL-NEXT: s_cselect_b32 s4, 0, s4
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s1, 0x5f7fffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, -1, s4
+; GFX12-ISEL-NEXT: s_cselect_b32 s0, -1, s0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v5, s1 :: v_dual_mov_b32 v4, s0
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_unsigned_v4f16_v4i64:
@@ -4970,34 +5347,67 @@ define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
; GFX7-ISEL-LABEL: test_unsigned_v8f16_v8i64:
; GFX7-ISEL: ; %bb.0:
; GFX7-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v3, v3
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v4, v0
+; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v11, 16, v0
; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v4, v1
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v12, v3
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v1, v9
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v3, v7
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v7, v6
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v5, v5
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v5, v4
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v4
+; GFX7-ISEL-NEXT: s_mov_b32 s4, 0x5f7fffff
+; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v5, 0, vcc
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v4
; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v8, v2
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v2, v1
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v6, v3
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v10, v7
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v14, v5
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v5, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v7, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v9, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v11, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v13, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v15, 0
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v3, v3
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v4, v5
+; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v10, 16, v1
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v5
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v5
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v4, v4, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v2
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v2
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v2, v3
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v11, v11
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v8, v8, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v3
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v3
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v12, v2, -1, vcc
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v2, v11
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v10, v10
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v11
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v11
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v11, v10
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v14, v6
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v15, v7
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v10
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v6, v11, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v10
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v10, v14
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v16, v15
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v6, v6, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v14
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v14
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v10, v10, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v15
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v14, v16, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v15
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v14, v14, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v15, 0, -1, vcc
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_unsigned_v8f16_v8i64:
@@ -5121,31 +5531,114 @@ define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
; GFX9-LABEL: test_unsigned_v8f16_v8i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_e32 v7, v2
-; GFX9-NEXT: v_cvt_f32_f16_e32 v4, v0
-; GFX9-NEXT: v_cvt_f32_f16_e32 v6, v1
-; GFX9-NEXT: v_cvt_f32_f16_e32 v9, v3
-; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v7
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_mov_b32_e32 v4, v1
+; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v0
+; GFX9-NEXT: v_cvt_f32_f16_e32 v8, v4
+; GFX9-NEXT: v_cvt_f32_f16_e32 v12, v2
+; GFX9-NEXT: s_mov_b32 s18, 0x5f7fffff
+; GFX9-NEXT: v_trunc_f32_e32 v6, v1
+; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v6
+; GFX9-NEXT: v_trunc_f32_e32 v10, v8
+; GFX9-NEXT: v_floor_f32_e32 v7, v5
+; GFX9-NEXT: v_mul_f32_e32 v9, 0x2f800000, v10
+; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v7
+; GFX9-NEXT: v_floor_f32_e32 v11, v9
+; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v11
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, 0, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s18, v1
+; GFX9-NEXT: v_cmp_nle_f32_e64 s[6:7], 0, v8
+; GFX9-NEXT: v_trunc_f32_e32 v14, v12
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v5, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v9, 0, s[6:7]
+; GFX9-NEXT: v_mul_f32_e32 v9, 0x2f800000, v14
+; GFX9-NEXT: v_floor_f32_e32 v15, v9
+; GFX9-NEXT: v_cvt_f32_f16_e32 v13, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v15
+; GFX9-NEXT: v_cmp_nle_f32_e64 s[10:11], 0, v12
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[8:9], s18, v8
+; GFX9-NEXT: v_trunc_f32_e32 v17, v13
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v9, 0, s[10:11]
+; GFX9-NEXT: v_mul_f32_e32 v9, 0x2f800000, v17
+; GFX9-NEXT: v_floor_f32_e32 v18, v9
+; GFX9-NEXT: v_cvt_u32_f32_e32 v16, v18
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[12:13], s18, v12
+; GFX9-NEXT: v_cmp_nle_f32_e64 s[14:15], 0, v13
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v8, -1, s[12:13]
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v16, 0, s[14:15]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[16:17], s18, v13
+; GFX9-NEXT: s_mov_b32 s19, 0xcf800000
+; GFX9-NEXT: v_cndmask_b32_e64 v13, v8, -1, s[16:17]
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_fma_f32 v0, v7, s19, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_trunc_f32_e32 v6, v8
+; GFX9-NEXT: v_mul_f32_e32 v7, 0x2f800000, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, 0, v8
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s18, v8
+; GFX9-NEXT: v_fma_f32 v8, v15, s19, v14
+; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX9-NEXT: v_floor_f32_e32 v12, v7
; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v4
-; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v6
-; GFX9-NEXT: v_cvt_u32_f32_e32 v12, v9
-; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v10, v7
-; GFX9-NEXT: v_cvt_u32_f32_e32 v14, v3
-; GFX9-NEXT: v_mov_b32_e32 v0, v5
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_mov_b32_e32 v3, 0
-; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: v_mov_b32_e32 v7, 0
-; GFX9-NEXT: v_mov_b32_e32 v9, 0
-; GFX9-NEXT: v_mov_b32_e32 v11, 0
-; GFX9-NEXT: v_mov_b32_e32 v13, 0
-; GFX9-NEXT: v_mov_b32_e32 v15, 0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v12
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v19, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[10:11]
+; GFX9-NEXT: v_trunc_f32_e32 v14, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, -1, s[12:13]
+; GFX9-NEXT: v_cmp_nle_f32_e64 s[10:11], 0, v2
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[12:13], s18, v2
+; GFX9-NEXT: v_fma_f32 v2, v18, s19, v17
+; GFX9-NEXT: v_trunc_f32_e32 v17, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
+; GFX9-NEXT: v_fma_f32 v4, v11, s19, v10
+; GFX9-NEXT: v_trunc_f32_e32 v10, v19
+; GFX9-NEXT: v_mul_f32_e32 v15, 0x2f800000, v17
+; GFX9-NEXT: v_cndmask_b32_e64 v16, v7, -1, s[4:5]
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX9-NEXT: v_mul_f32_e32 v7, 0x2f800000, v10
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_floor_f32_e32 v18, v15
+; GFX9-NEXT: v_floor_f32_e32 v20, v7
+; GFX9-NEXT: v_fma_f32 v6, v12, s19, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v15, v18
+; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX9-NEXT: v_fma_f32 v10, v20, s19, v10
+; GFX9-NEXT: v_cvt_u32_f32_e32 v10, v10
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[6:7]
+; GFX9-NEXT: v_mul_f32_e32 v11, 0x2f800000, v14
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[14:15]
+; GFX9-NEXT: v_cmp_nle_f32_e64 s[14:15], 0, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, -1, s[8:9]
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, -1, s[8:9]
+; GFX9-NEXT: v_cmp_nle_f32_e64 s[6:7], 0, v19
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[8:9], s18, v19
+; GFX9-NEXT: v_floor_f32_e32 v19, v11
+; GFX9-NEXT: v_cndmask_b32_e64 v12, v2, -1, s[16:17]
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v15, 0, s[14:15]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[16:17], s18, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v15, v2, -1, s[16:17]
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
+; GFX9-NEXT: v_fma_f32 v6, v19, s19, v14
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v10, 0, s[6:7]
+; GFX9-NEXT: v_cvt_u32_f32_e32 v10, v6
+; GFX9-NEXT: v_fma_f32 v6, v18, s19, v17
+; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v20
+; GFX9-NEXT: v_cvt_u32_f32_e32 v11, v19
+; GFX9-NEXT: v_cvt_u32_f32_e32 v14, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v3, -1, s[8:9]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v10, 0, s[10:11]
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, 0, s[10:11]
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v3, -1, s[12:13]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v14, 0, s[14:15]
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, -1, s[8:9]
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, -1, s[12:13]
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v14, v3, -1, s[16:17]
+; GFX9-NEXT: v_mov_b32_e32 v3, v16
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_unsigned_v8f16_v8i64:
@@ -5153,32 +5646,111 @@ define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, v1
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v4
-; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v4, v5
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v2
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v8, v3
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v4
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v10, v5
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v6
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v8
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v13, 0x2f800000, v10
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v20, v1
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v9, 0x2f800000, v7
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v18, v0
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e64 s5, 0, v8
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s6, 0x5f7fffff, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v8, v6
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v8, 0x2f800000, v20
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v15, v9
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v14, 0x2f800000, v11
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v17, v13
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e64 s1, 0, v6
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s4, 0x5f7fffff, v6
+; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v7, 0xcf800000, v15
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v18
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v15
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v4
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, 0x5f7fffff, v4
+; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v10, 0xcf800000, v17
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v4, v7
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v7, 0x2f800000, v6
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v21, v2
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v9, 0x2f800000, v12
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v14, v14
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v15, v7
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v7, v10
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v10, v8
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v8, 0x2f800000, v21
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v19, v9
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v9, v17
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v13, v14
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e64 s0, 0, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v16, v0, -1, s2
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v19
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, 0x5f7fffff, v5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v13, v13, 0, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, v9, 0, s0
+; GFX11-FAKE16-NEXT: v_dual_fmac_f32 v11, 0xcf800000, v14 :: v_dual_fmac_f32 v12, 0xcf800000, v19
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0, s5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, v9, -1, s3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, v13, -1, s4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, 0, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v13, v0, -1, s6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v4, v15
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v18
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5f7fffff, v18
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v14, v8
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v7
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v2
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, v5
-; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v12, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, -1, s2
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e64 s2, 0, v1
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v8, v12
+; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v18, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, v4, -1, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, v7, -1, s3
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, 0x5f7fffff, v1
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v1, v14
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, 0, s1
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e64 s1, 0, v2
+; GFX11-FAKE16-NEXT: v_mul_f32_e32 v12, 0x2f800000, v18
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, v8, 0, s5
+; GFX11-FAKE16-NEXT: v_dual_fmac_f32 v6, 0xcf800000, v15 :: v_dual_fmac_f32 v21, 0xcf800000, v14
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, s1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, v11, -1, s4
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e64 s4, 0x5f7fffff, v2
+; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v20, 0xcf800000, v10
; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v2, v6
-; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v6, v1
-; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v10, v7
-; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v14, v5
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, 0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, 0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v13, 0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v15, 0
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v7, v10
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v10, v21
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, v1, -1, s4
+; GFX11-FAKE16-NEXT: v_floor_f32_e32 v1, v12
+; GFX11-FAKE16-NEXT: v_cmp_nle_f32_e64 s5, 0, v3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, v17 :: v_dual_fmac_f32 v18, 0xcf800000, v1
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v6, v20
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, 0, s2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, v10, 0, s1
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v14, v18
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, s5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, 0, s2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, -1, s3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, v19, -1, s6
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, 0, s5
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v15, v1, -1, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, -1, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, -1, s3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, v10, -1, s4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, -1, vcc_lo
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, v16
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: test_unsigned_v8f16_v8i64:
@@ -5186,32 +5758,111 @@ define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v4
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v5
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v2.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v3.l
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v4
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v10, v5
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v6
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v8
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v13, 0x2f800000, v10
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v20, v1
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, 0x2f800000, v7
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v18, v0.l
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e64 s5, 0, v8
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s6, 0x5f7fffff, v8
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v6
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v8, 0x2f800000, v20
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v15, v9
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v14, 0x2f800000, v11
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v17, v13
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e64 s1, 0, v6
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s4, 0x5f7fffff, v6
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v7, 0xcf800000, v15
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v18
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v15
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, 0x5f7fffff, v4
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v10, 0xcf800000, v17
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v7
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v7, 0x2f800000, v6
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v21, v2
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, 0x2f800000, v12
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v14, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v15, v7
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v7, v10
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v10, v8
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v8, 0x2f800000, v21
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v19, v9
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v9, v17
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v13, v14
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e64 s0, 0, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v16, v0, -1, s2
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v19
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, 0x5f7fffff, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, v13, 0, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, v9, 0, s0
+; GFX11-TRUE16-NEXT: v_dual_fmac_f32 v11, 0xcf800000, v14 :: v_dual_fmac_f32 v12, 0xcf800000, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0, s5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, v9, -1, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, v13, -1, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, v7, 0, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, v0, -1, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v15
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v18
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5f7fffff, v18
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v14, v8
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v7.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v5.l
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v12, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, -1, s2
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e64 s2, 0, v1
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v12
+; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v18, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v17, v4, -1, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, v7, -1, s3
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, 0x5f7fffff, v1
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v1, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, 0, s1
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e64 s1, 0, v2
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v12, 0x2f800000, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v19, v8, 0, s5
+; GFX11-TRUE16-NEXT: v_dual_fmac_f32 v6, 0xcf800000, v15 :: v_dual_fmac_f32 v21, 0xcf800000, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, v11, -1, s4
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s4, 0x5f7fffff, v2
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v20, 0xcf800000, v10
; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v6
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v1
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v10, v7
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v14, v5
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, 0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v9, 0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, 0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v15, 0
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v7, v10
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v10, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, v1, -1, s4
+; GFX11-TRUE16-NEXT: v_floor_f32_e32 v1, v12
+; GFX11-TRUE16-NEXT: v_cmp_nle_f32_e64 s5, 0, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v3
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v17 :: v_dual_fmac_f32 v18, 0xcf800000, v1
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, v7, 0, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, v10, 0, s1
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v14, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, s5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v6, 0, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, v7, -1, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, v19, -1, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v14, v14, 0, s5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v15, v1, -1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, -1, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, v6, -1, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, v10, -1, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v14, v14, -1, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_unsigned_v8f16_v8i64:
@@ -5223,32 +5874,120 @@ define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v0
; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, v1
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v2
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v4
-; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v4, v5
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v2
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v8, v3
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v7, v4
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v10, v5
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v11, v6
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v12, v8
+; GFX12-FAKE16-NEXT: v_mul_f32_e32 v13, 0x2f800000, v10
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v20, v1
+; GFX12-FAKE16-NEXT: v_mul_f32_e32 v9, 0x2f800000, v7
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v18, v0
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e64 s5, 0, v8
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s6, 0x5f7fffff, v8
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v8, v6
+; GFX12-FAKE16-NEXT: v_mul_f32_e32 v8, 0x2f800000, v20
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v15, v9
+; GFX12-FAKE16-NEXT: v_mul_f32_e32 v14, 0x2f800000, v11
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v17, v13
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e64 s1, 0, v6
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s4, 0x5f7fffff, v6
+; GFX12-FAKE16-NEXT: v_fmac_f32_e32 v7, 0xcf800000, v15
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v6, v18
+; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v15
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v4
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s2, 0x5f7fffff, v4
+; GFX12-FAKE16-NEXT: v_fmac_f32_e32 v10, 0xcf800000, v17
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v4, v7
+; GFX12-FAKE16-NEXT: v_mul_f32_e32 v7, 0x2f800000, v6
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v21, v2
+; GFX12-FAKE16-NEXT: v_mul_f32_e32 v9, 0x2f800000, v12
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v14, v14
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v15, v7
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v7, v10
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v10, v8
+; GFX12-FAKE16-NEXT: v_mul_f32_e32 v8, 0x2f800000, v21
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v19, v9
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v9, v17
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v13, v14
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e64 s0, 0, v5
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v16, v0, -1, s2
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v19
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, 0x5f7fffff, v5
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v13, v13, 0, s1
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v9, v9, 0, s0
+; GFX12-FAKE16-NEXT: v_dual_fmac_f32 v11, 0xcf800000, v14 :: v_dual_fmac_f32 v12, 0xcf800000, v19
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0, s5
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v5, v9, -1, s3
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v9, v13, -1, s4
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, 0, s0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v13, v0, -1, s6
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v4, v15
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v18
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5f7fffff, v18
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v14, v8
; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v7
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v2
-; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, v5
-; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v12, v3
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, -1, s2
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e64 s2, 0, v1
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v8, v12
+; GFX12-FAKE16-NEXT: v_trunc_f32_e32 v18, v3
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v17, v4, -1, s0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v7, -1, s3
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s3, 0x5f7fffff, v1
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v1, v14
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v11, 0, s1
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e64 s1, 0, v2
+; GFX12-FAKE16-NEXT: v_mul_f32_e32 v12, 0x2f800000, v18
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v19, v8, 0, s5
+; GFX12-FAKE16-NEXT: v_dual_fmac_f32 v6, 0xcf800000, v15 :: v_dual_fmac_f32 v21, 0xcf800000, v14
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, s1
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v8, v11, -1, s4
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s4, 0x5f7fffff, v2
+; GFX12-FAKE16-NEXT: v_fmac_f32_e32 v20, 0xcf800000, v10
; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v2, v6
-; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v6, v1
-; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v10, v7
-; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v14, v5
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, 0
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, 0
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v7, 0
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v9, 0
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v11, 0
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v13, 0
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v15, 0
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v7, v10
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v10, v21
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v11, v1, -1, s4
+; GFX12-FAKE16-NEXT: v_floor_f32_e32 v1, v12
+; GFX12-FAKE16-NEXT: v_cmp_nle_f32_e64 s5, 0, v3
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v3
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v3, v17 :: v_dual_fmac_f32 v18, 0xcf800000, v1
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v6, v20
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, 0, s2
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v10, v10, 0, s1
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v14, v18
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, s5
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, 0, s2
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v7, v7, -1, s3
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v12, v19, -1, s6
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, 0, s5
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v15, v1, -1, vcc_lo
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, -1, s0
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, -1, s3
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v10, v10, -1, s4
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v14, v14, -1, vcc_lo
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v16
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_unsigned_v8f16_v8i64:
@@ -5260,32 +5999,120 @@ define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.l
; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v2.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v4
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v5
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v2.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v3.l
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v7, v4
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v10, v5
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v11, v6
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v12, v8
+; GFX12-TRUE16-NEXT: v_mul_f32_e32 v13, 0x2f800000, v10
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v20, v1
+; GFX12-TRUE16-NEXT: v_mul_f32_e32 v9, 0x2f800000, v7
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v18, v0.l
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e64 s5, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s6, 0x5f7fffff, v8
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v6
+; GFX12-TRUE16-NEXT: v_mul_f32_e32 v8, 0x2f800000, v20
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v15, v9
+; GFX12-TRUE16-NEXT: v_mul_f32_e32 v14, 0x2f800000, v11
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v17, v13
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e64 s1, 0, v6
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s4, 0x5f7fffff, v6
+; GFX12-TRUE16-NEXT: v_fmac_f32_e32 v7, 0xcf800000, v15
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v6, v18
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v15
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v4
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, 0x5f7fffff, v4
+; GFX12-TRUE16-NEXT: v_fmac_f32_e32 v10, 0xcf800000, v17
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v7
+; GFX12-TRUE16-NEXT: v_mul_f32_e32 v7, 0x2f800000, v6
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v21, v2
+; GFX12-TRUE16-NEXT: v_mul_f32_e32 v9, 0x2f800000, v12
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v14, v14
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v15, v7
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v7, v10
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v10, v8
+; GFX12-TRUE16-NEXT: v_mul_f32_e32 v8, 0x2f800000, v21
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v19, v9
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v9, v17
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v13, v14
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e64 s0, 0, v5
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v16, v0, -1, s2
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v19
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, 0x5f7fffff, v5
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v13, v13, 0, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v9, v9, 0, s0
+; GFX12-TRUE16-NEXT: v_dual_fmac_f32 v11, 0xcf800000, v14 :: v_dual_fmac_f32 v12, 0xcf800000, v19
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0, s5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v5, v9, -1, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v9, v13, -1, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v7, v7, 0, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v13, v0, -1, s6
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v15
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v18
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0x5f7fffff, v18
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v14, v8
; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v7.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v5.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v12, v3
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, -1, s2
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e64 s2, 0, v1
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v12
+; GFX12-TRUE16-NEXT: v_trunc_f32_e32 v18, v3
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v17, v4, -1, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v4, v7, -1, s3
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, 0x5f7fffff, v1
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v1, v14
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v11, v11, 0, s1
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e64 s1, 0, v2
+; GFX12-TRUE16-NEXT: v_mul_f32_e32 v12, 0x2f800000, v18
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v19, v8, 0, s5
+; GFX12-TRUE16-NEXT: v_dual_fmac_f32 v6, 0xcf800000, v15 :: v_dual_fmac_f32 v21, 0xcf800000, v14
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v8, v11, -1, s4
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s4, 0x5f7fffff, v2
+; GFX12-TRUE16-NEXT: v_fmac_f32_e32 v20, 0xcf800000, v10
; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v6
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v1
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v10, v7
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v14, v5
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, 0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, 0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, 0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v9, 0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v11, 0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v13, 0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v15, 0
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v7, v10
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v10, v21
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v11, v1, -1, s4
+; GFX12-TRUE16-NEXT: v_floor_f32_e32 v1, v12
+; GFX12-TRUE16-NEXT: v_cmp_nle_f32_e64 s5, 0, v3
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v3
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v3, v17 :: v_dual_fmac_f32 v18, 0xcf800000, v1
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v20
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v7, v7, 0, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v10, v10, 0, s1
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v14, v18
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, s5
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v6, 0, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v7, v7, -1, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v12, v19, -1, s6
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v14, v14, 0, s5
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v15, v1, -1, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, -1, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v6, v6, -1, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v10, v10, -1, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v14, v14, -1, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v16
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_unsigned_v8f16_v8i64:
@@ -6421,34 +7248,67 @@ define <8 x i64> @test_s_unsigned_v8f16_v8i64(<8 x half> inreg %f) {
; GFX7-ISEL-LABEL: test_s_unsigned_v8f16_v8i64:
; GFX7-ISEL: ; %bb.0:
; GFX7-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v1, s17
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v0, s16
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v2, s17
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v6, s18
+; GFX7-ISEL-NEXT: s_mov_b32 s8, 0x5f7fffff
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v1, v0
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v0
+; GFX7-ISEL-NEXT: s_lshr_b32 s7, s16, 16
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v0
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v0, v1, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v2
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v2, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v4, v3, -1, vcc
; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v3, s19
-; GFX7-ISEL-NEXT: s_lshr_b32 s4, s19, 16
-; GFX7-ISEL-NEXT: s_lshr_b32 s5, s18, 16
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v8, v2, -1, vcc
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v2, v3
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v6, s7
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v3
; GFX7-ISEL-NEXT: s_lshr_b32 s6, s17, 16
-; GFX7-ISEL-NEXT: s_lshr_b32 s7, s16, 16
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v0, s16
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v2, s18
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v4, v1
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v12, v3
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v1, s7
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v3, s6
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v5, s5
-; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v7, s4
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v8, v2
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v2, v1
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v6, v3
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v10, v5
-; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v14, v7
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v5, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v7, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v9, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v11, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v13, 0
-; GFX7-ISEL-NEXT: v_mov_b32_e32 v15, 0
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v3
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v12, v2, -1, vcc
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v2, v6
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v7, s6
+; GFX7-ISEL-NEXT: s_lshr_b32 s5, s18, 16
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v10, s5
+; GFX7-ISEL-NEXT: s_lshr_b32 s4, s19, 16
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v6
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v6
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v6, v7
+; GFX7-ISEL-NEXT: v_cvt_f32_f16_e32 v14, s4
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v11, v10
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v7
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v7
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v15, v14
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v6, v6, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v10
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v11, v11, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v10
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v10, v11, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
+; GFX7-ISEL-NEXT: v_cmp_nle_f32_e32 vcc, 0, v14
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v15, v15, 0, vcc
+; GFX7-ISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v14
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v14, v15, -1, vcc
+; GFX7-ISEL-NEXT: v_cndmask_b32_e64 v15, 0, -1, vcc
; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_s_unsigned_v8f16_v8i64:
@@ -6601,67 +7461,228 @@ define <8 x i64> @test_s_unsigned_v8f16_v8i64(<8 x half> inreg %f) {
; GFX9-LABEL: test_s_unsigned_v8f16_v8i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_e32 v1, s17
-; GFX9-NEXT: v_cvt_f32_f16_e32 v3, s19
-; GFX9-NEXT: s_lshr_b32 s4, s16, 16
+; GFX9-NEXT: v_cvt_f32_f16_e32 v4, s17
+; GFX9-NEXT: v_cvt_f32_f16_e32 v8, s18
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s16
-; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v1
-; GFX9-NEXT: v_cvt_f32_f16_e32 v1, s4
-; GFX9-NEXT: s_lshr_b32 s4, s17, 16
-; GFX9-NEXT: v_cvt_u32_f32_e32 v12, v3
-; GFX9-NEXT: v_cvt_f32_f16_e32 v3, s4
-; GFX9-NEXT: s_lshr_b32 s4, s18, 16
-; GFX9-NEXT: v_cvt_f32_f16_e32 v5, s4
-; GFX9-NEXT: s_lshr_b32 s4, s19, 16
-; GFX9-NEXT: v_cvt_f32_f16_e32 v2, s18
-; GFX9-NEXT: v_cvt_f32_f16_e32 v7, s4
+; GFX9-NEXT: v_cvt_f32_f16_e32 v12, s19
+; GFX9-NEXT: v_trunc_f32_e32 v6, v4
+; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v6
+; GFX9-NEXT: v_floor_f32_e32 v7, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v7
+; GFX9-NEXT: s_mov_b32 s22, 0x5f7fffff
+; GFX9-NEXT: v_cmp_nle_f32_e64 s[6:7], 0, v4
+; GFX9-NEXT: v_trunc_f32_e32 v10, v8
+; GFX9-NEXT: v_trunc_f32_e32 v2, v0
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s22, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v5, 0, s[6:7]
+; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v10
+; GFX9-NEXT: v_trunc_f32_e32 v14, v12
+; GFX9-NEXT: v_floor_f32_e32 v11, v5
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[8:9], s22, v4
+; GFX9-NEXT: v_mul_f32_e32 v4, 0x2f800000, v14
+; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v11
+; GFX9-NEXT: v_floor_f32_e32 v15, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v15
+; GFX9-NEXT: v_cmp_nle_f32_e64 s[10:11], 0, v8
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v0, -1, s[8:9]
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v9, 0, s[10:11]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[12:13], s22, v8
+; GFX9-NEXT: v_cmp_nle_f32_e64 s[14:15], 0, v12
+; GFX9-NEXT: v_floor_f32_e32 v3, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v0, -1, s[12:13]
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[14:15]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[20:21], s22, v12
+; GFX9-NEXT: s_mov_b32 s23, 0xcf800000
+; GFX9-NEXT: v_cndmask_b32_e64 v13, v0, -1, s[20:21]
+; GFX9-NEXT: v_fma_f32 v0, v3, s23, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v3
-; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v2
-; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v10, v5
-; GFX9-NEXT: v_cvt_u32_f32_e32 v14, v7
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_mov_b32_e32 v3, 0
-; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: v_mov_b32_e32 v7, 0
-; GFX9-NEXT: v_mov_b32_e32 v9, 0
-; GFX9-NEXT: v_mov_b32_e32 v11, 0
-; GFX9-NEXT: v_mov_b32_e32 v13, 0
-; GFX9-NEXT: v_mov_b32_e32 v15, 0
+; GFX9-NEXT: s_lshr_b32 s16, s16, 16
+; GFX9-NEXT: v_cvt_f32_f16_e32 v4, s16
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[4:5]
+; GFX9-NEXT: s_lshr_b32 s4, s17, 16
+; GFX9-NEXT: v_trunc_f32_e32 v2, v4
+; GFX9-NEXT: v_cmp_nle_f32_e32 vcc, 0, v4
+; GFX9-NEXT: v_cvt_f32_f16_e32 v8, s4
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], s22, v4
+; GFX9-NEXT: v_fma_f32 v4, v7, s23, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX9-NEXT: v_trunc_f32_e32 v6, v8
+; GFX9-NEXT: v_fma_f32 v14, v15, s23, v14
+; GFX9-NEXT: v_cvt_u32_f32_e32 v14, v14
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, -1, s[8:9]
+; GFX9-NEXT: s_lshr_b32 s8, s18, 16
+; GFX9-NEXT: v_cmp_nle_f32_e64 s[6:7], 0, v8
+; GFX9-NEXT: v_cvt_f32_f16_e32 v17, s8
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[8:9], s22, v8
+; GFX9-NEXT: v_fma_f32 v8, v11, s23, v10
+; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX9-NEXT: v_trunc_f32_e32 v10, v17
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; GFX9-NEXT: v_floor_f32_e32 v12, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[10:11]
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, -1, s[12:13]
+; GFX9-NEXT: s_lshr_b32 s12, s19, 16
+; GFX9-NEXT: v_cvt_f32_f16_e32 v19, s12
+; GFX9-NEXT: v_cmp_nle_f32_e64 s[10:11], 0, v17
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[12:13], s22, v17
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v12
+; GFX9-NEXT: v_trunc_f32_e32 v17, v19
+; GFX9-NEXT: v_mul_f32_e32 v15, 0x2f800000, v17
+; GFX9-NEXT: v_floor_f32_e32 v20, v15
+; GFX9-NEXT: v_cvt_u32_f32_e32 v15, v20
+; GFX9-NEXT: v_mul_f32_e32 v7, 0x2f800000, v6
+; GFX9-NEXT: v_mul_f32_e32 v11, 0x2f800000, v10
+; GFX9-NEXT: v_fma_f32 v2, v12, s23, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v12, v14, 0, s[14:15]
+; GFX9-NEXT: v_cmp_nle_f32_e64 s[14:15], 0, v19
+; GFX9-NEXT: v_floor_f32_e32 v16, v7
+; GFX9-NEXT: v_floor_f32_e32 v18, v11
+; GFX9-NEXT: v_cndmask_b32_e64 v14, v15, 0, s[14:15]
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[16:17], s22, v19
+; GFX9-NEXT: v_fma_f32 v6, v16, s23, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v15, v14, -1, s[16:17]
+; GFX9-NEXT: v_fma_f32 v10, v18, s23, v10
+; GFX9-NEXT: v_fma_f32 v14, v20, s23, v17
+; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v16
+; GFX9-NEXT: v_cvt_u32_f32_e32 v11, v18
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v10, v10
+; GFX9-NEXT: v_cvt_u32_f32_e32 v14, v14
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, 0, s[10:11]
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[10:11]
+; GFX9-NEXT: v_cndmask_b32_e64 v14, v14, 0, s[14:15]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, -1, s[8:9]
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, -1, s[12:13]
+; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, -1, s[20:21]
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, -1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, -1, s[8:9]
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, -1, s[12:13]
+; GFX9-NEXT: v_cndmask_b32_e64 v14, v14, -1, s[16:17]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_unsigned_v8f16_v8i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cvt_f32_f16_e32 v2, s2
-; GFX11-NEXT: v_cvt_f32_f16_e32 v1, s1
; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s0
+; GFX11-NEXT: v_cvt_f32_f16_e32 v2, s1
+; GFX11-NEXT: v_cvt_f32_f16_e32 v6, s2
+; GFX11-NEXT: v_cvt_f32_f16_e32 v7, s3
; GFX11-NEXT: s_lshr_b32 s0, s0, 16
+; GFX11-NEXT: v_trunc_f32_e32 v3, v0
+; GFX11-NEXT: v_trunc_f32_e32 v4, v2
+; GFX11-NEXT: v_trunc_f32_e32 v8, v6
+; GFX11-NEXT: v_trunc_f32_e32 v10, v7
+; GFX11-NEXT: v_cvt_f32_f16_e32 v12, s0
+; GFX11-NEXT: v_mul_f32_e32 v1, 0x2f800000, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
+; GFX11-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: v_cmp_nle_f32_e64 s0, 0, v2
; GFX11-NEXT: s_lshr_b32 s1, s1, 16
-; GFX11-NEXT: v_cvt_u32_f32_e32 v8, v2
-; GFX11-NEXT: v_cvt_f32_f16_e32 v2, s0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v3, s1
-; GFX11-NEXT: s_lshr_b32 s0, s2, 16
-; GFX11-NEXT: s_lshr_b32 s1, s3, 16
-; GFX11-NEXT: v_cvt_u32_f32_e32 v4, v1
-; GFX11-NEXT: v_cvt_f32_f16_e32 v1, s3
-; GFX11-NEXT: v_cvt_f32_f16_e32 v5, s0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v7, s1
-; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-NEXT: v_floor_f32_e32 v9, v1
+; GFX11-NEXT: v_floor_f32_e32 v11, v5
+; GFX11-NEXT: v_mul_f32_e32 v1, 0x2f800000, v8
+; GFX11-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-NEXT: v_mul_f32_e32 v13, 0x2f800000, v10
+; GFX11-NEXT: v_cvt_u32_f32_e32 v5, v9
+; GFX11-NEXT: v_cvt_u32_f32_e32 v14, v11
+; GFX11-NEXT: v_floor_f32_e32 v15, v1
+; GFX11-NEXT: v_cmp_nle_f32_e64 s6, 0, v6
+; GFX11-NEXT: v_dual_fmac_f32 v3, 0xcf800000, v9 :: v_dual_fmac_f32 v4, 0xcf800000, v11
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v14, 0, s0
+; GFX11-NEXT: v_cvt_u32_f32_e32 v14, v15
+; GFX11-NEXT: v_cvt_f32_f16_e32 v16, s1
+; GFX11-NEXT: v_cvt_f32_f16_e32 v11, s2
+; GFX11-NEXT: v_cmp_lt_f32_e64 s4, 0x5f7fffff, v0
+; GFX11-NEXT: v_cmp_lt_f32_e64 s5, 0x5f7fffff, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v14, 0, s6
+; GFX11-NEXT: v_floor_f32_e32 v2, v13
+; GFX11-NEXT: v_cmp_lt_f32_e64 s7, 0x5f7fffff, v6
+; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-NEXT: v_trunc_f32_e32 v17, v16
+; GFX11-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX11-NEXT: v_trunc_f32_e32 v19, v11
+; GFX11-NEXT: v_trunc_f32_e32 v14, v12
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v0, -1, s7
+; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v2
+; GFX11-NEXT: v_cmp_nle_f32_e64 s1, 0, v7
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
+; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v7
+; GFX11-NEXT: v_mul_f32_e32 v7, 0x2f800000, v17
+; GFX11-NEXT: v_cmp_nle_f32_e64 s2, 0, v12
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, 0, s0
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x5f7fffff, v12
+; GFX11-NEXT: v_mul_f32_e32 v12, 0x2f800000, v19
+; GFX11-NEXT: s_lshr_b32 s3, s3, 16
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0, s1
+; GFX11-NEXT: v_floor_f32_e32 v18, v7
+; GFX11-NEXT: v_fmac_f32_e32 v8, 0xcf800000, v15
+; GFX11-NEXT: v_floor_f32_e32 v15, v12
+; GFX11-NEXT: v_cvt_f32_f16_e32 v20, s3
+; GFX11-NEXT: v_fmac_f32_e32 v10, 0xcf800000, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, -1, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, -1, s5
+; GFX11-NEXT: v_cndmask_b32_e64 v13, v0, -1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v3, -1, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, -1, s5
+; GFX11-NEXT: v_cmp_nle_f32_e64 s4, 0, v16
+; GFX11-NEXT: v_cmp_lt_f32_e64 s3, 0x5f7fffff, v16
+; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v15
+; GFX11-NEXT: v_trunc_f32_e32 v16, v20
+; GFX11-NEXT: v_cmp_nle_f32_e64 s5, 0, v11
+; GFX11-NEXT: v_fmac_f32_e32 v19, 0xcf800000, v15
+; GFX11-NEXT: v_cvt_u32_f32_e32 v10, v10
+; GFX11-NEXT: v_mul_f32_e32 v6, 0x2f800000, v14
+; GFX11-NEXT: v_mul_f32_e32 v12, 0x2f800000, v16
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, s5
+; GFX11-NEXT: v_fmac_f32_e32 v17, 0xcf800000, v18
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, 0, s1
+; GFX11-NEXT: v_cmp_lt_f32_e64 s1, 0x5f7fffff, v11
+; GFX11-NEXT: v_floor_f32_e32 v6, v6
+; GFX11-NEXT: v_cvt_u32_f32_e32 v7, v18
+; GFX11-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX11-NEXT: v_cndmask_b32_e64 v11, v2, -1, s1
+; GFX11-NEXT: v_floor_f32_e32 v2, v12
+; GFX11-NEXT: v_fmac_f32_e32 v14, 0xcf800000, v6
+; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v6
+; GFX11-NEXT: v_cndmask_b32_e64 v12, v10, -1, vcc_lo
+; GFX11-NEXT: v_cvt_u32_f32_e32 v10, v17
+; GFX11-NEXT: v_fmac_f32_e32 v16, 0xcf800000, v2
; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX11-NEXT: v_cvt_u32_f32_e32 v12, v1
-; GFX11-NEXT: v_cvt_u32_f32_e32 v6, v3
-; GFX11-NEXT: v_cvt_u32_f32_e32 v10, v5
-; GFX11-NEXT: v_cvt_u32_f32_e32 v14, v7
-; GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-NEXT: v_mov_b32_e32 v3, 0
-; GFX11-NEXT: v_mov_b32_e32 v5, 0
-; GFX11-NEXT: v_mov_b32_e32 v7, 0
-; GFX11-NEXT: v_mov_b32_e32 v9, 0
-; GFX11-NEXT: v_mov_b32_e32 v11, 0
-; GFX11-NEXT: v_mov_b32_e32 v13, 0
-; GFX11-NEXT: v_mov_b32_e32 v15, 0
+; GFX11-NEXT: v_cvt_u32_f32_e32 v6, v14
+; GFX11-NEXT: v_cvt_u32_f32_e32 v14, v19
+; GFX11-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v20
+; GFX11-NEXT: v_cvt_u32_f32_e32 v15, v16
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, 0, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, 0, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, 0, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, 0, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, 0, s5
+; GFX11-NEXT: v_cndmask_b32_e64 v16, v15, 0, vcc_lo
+; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x5f7fffff, v20
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, -1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, -1, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, -1, s7
+; GFX11-NEXT: v_cndmask_b32_e64 v15, v2, -1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v6, -1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v10, -1, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v14, -1, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v14, v16, -1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_unsigned_v8f16_v8i64:
@@ -6671,32 +7692,145 @@ define <8 x i64> @test_s_unsigned_v8f16_v8i64(<8 x half> inreg %f) {
; GFX12-ISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s4, s0
-; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s5, s1
-; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s6, s2
-; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s7, s3
-; GFX12-ISEL-NEXT: s_cvt_f32_f16 s0, s0
+; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s4, s1
+; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s6, s3
+; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s9, s2
; GFX12-ISEL-NEXT: s_cvt_f32_f16 s1, s1
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_trunc_f32 s5, s4
+; GFX12-ISEL-NEXT: s_trunc_f32 s8, s6
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s4, 0
+; GFX12-ISEL-NEXT: s_trunc_f32 s11, s9
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_mul_f32 s7, s5, 0x2f800000
+; GFX12-ISEL-NEXT: s_mul_f32 s10, s8, 0x2f800000
; GFX12-ISEL-NEXT: s_cvt_f32_f16 s2, s2
-; GFX12-ISEL-NEXT: s_cvt_f32_f16 s3, s3
+; GFX12-ISEL-NEXT: s_mul_f32 s12, s11, 0x2f800000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_floor_f32 s7, s7
+; GFX12-ISEL-NEXT: s_floor_f32 s10, s10
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s5, s7, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s7, s7
+; GFX12-ISEL-NEXT: s_fmac_f32 s8, s10, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s10, s10
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: s_cvt_u32_f32 s4, s4
; GFX12-ISEL-NEXT: s_cvt_u32_f32 s5, s5
+; GFX12-ISEL-NEXT: s_cselect_b32 s7, 0, s7
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s8, s8
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s5, 0, s5
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s4, 0x5f7fffff
+; GFX12-ISEL-NEXT: s_floor_f32 s4, s12
+; GFX12-ISEL-NEXT: s_cvt_hi_f32_f16 s12, s0
+; GFX12-ISEL-NEXT: s_cvt_f32_f16 s0, s0
+; GFX12-ISEL-NEXT: s_cselect_b32 s7, -1, s7
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s5, -1, s5
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s6, 0
+; GFX12-ISEL-NEXT: s_fmac_f32 s11, s4, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s4, s4
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v7, s7
+; GFX12-ISEL-NEXT: s_cselect_b32 s8, 0, s8
+; GFX12-ISEL-NEXT: s_cselect_b32 s10, 0, s10
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s6, 0x5f7fffff
+; GFX12-ISEL-NEXT: s_trunc_f32 s6, s12
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s11, s11
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s10, -1, s10
+; GFX12-ISEL-NEXT: s_mul_f32 s13, s6, 0x2f800000
+; GFX12-ISEL-NEXT: s_cselect_b32 s8, -1, s8
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s9, 0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v14, s8 :: v_dual_mov_b32 v15, s10
+; GFX12-ISEL-NEXT: s_floor_f32 s13, s13
+; GFX12-ISEL-NEXT: s_cselect_b32 s11, 0, s11
+; GFX12-ISEL-NEXT: s_cselect_b32 s4, 0, s4
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s9, 0x5f7fffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s6, s13, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s13, s13
+; GFX12-ISEL-NEXT: s_cselect_b32 s4, -1, s4
+; GFX12-ISEL-NEXT: s_cselect_b32 s9, -1, s11
+; GFX12-ISEL-NEXT: s_trunc_f32 s11, s1
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT: s_cvt_u32_f32 s6, s6
-; GFX12-ISEL-NEXT: s_cvt_u32_f32 s7, s7
-; GFX12-ISEL-NEXT: s_cvt_u32_f32 s0, s0
-; GFX12-ISEL-NEXT: s_cvt_u32_f32 s1, s1
-; GFX12-ISEL-NEXT: s_cvt_u32_f32 s2, s2
-; GFX12-ISEL-NEXT: s_cvt_u32_f32 s3, s3
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s12, 0
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v10, s9 :: v_dual_mov_b32 v11, s4
+; GFX12-ISEL-NEXT: s_mul_f32 s14, s11, 0x2f800000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s6, 0, s6
+; GFX12-ISEL-NEXT: s_cselect_b32 s13, 0, s13
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s12, 0x5f7fffff
+; GFX12-ISEL-NEXT: s_floor_f32 s14, s14
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s12, -1, s13
+; GFX12-ISEL-NEXT: s_trunc_f32 s13, s2
+; GFX12-ISEL-NEXT: s_fmac_f32 s11, s14, 0xcf800000
+; GFX12-ISEL-NEXT: s_cselect_b32 s6, -1, s6
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s1, 0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_mul_f32 s15, s13, 0x2f800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s11, s11
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s14, s14
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s12
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_floor_f32 s15, s15
+; GFX12-ISEL-NEXT: s_cselect_b32 s11, 0, s11
+; GFX12-ISEL-NEXT: s_cselect_b32 s14, 0, s14
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s1, 0x5f7fffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s13, s15, 0xcf800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s15, s15
+; GFX12-ISEL-NEXT: s_cselect_b32 s1, -1, s14
+; GFX12-ISEL-NEXT: s_cselect_b32 s11, -1, s11
+; GFX12-ISEL-NEXT: s_trunc_f32 s14, s0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s13, s13
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s2, 0
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v4, s11 :: v_dual_mov_b32 v5, s1
+; GFX12-ISEL-NEXT: s_mul_f32 s16, s14, 0x2f800000
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s13, 0, s13
+; GFX12-ISEL-NEXT: s_cselect_b32 s15, 0, s15
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s2, 0x5f7fffff
+; GFX12-ISEL-NEXT: s_cvt_f32_f16 s2, s3
+; GFX12-ISEL-NEXT: s_floor_f32 s16, s16
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s3, -1, s15
+; GFX12-ISEL-NEXT: s_trunc_f32 s15, s2
+; GFX12-ISEL-NEXT: s_fmac_f32 s14, s16, 0xcf800000
+; GFX12-ISEL-NEXT: s_cselect_b32 s13, -1, s13
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s0, 0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_mul_f32 s17, s15, 0x2f800000
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s14, s14
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s16, s16
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v8, s13 :: v_dual_mov_b32 v9, s3
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_floor_f32 s17, s17
+; GFX12-ISEL-NEXT: s_cselect_b32 s14, 0, s14
+; GFX12-ISEL-NEXT: s_cselect_b32 s16, 0, s16
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s0, 0x5f7fffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_fmac_f32 s15, s17, 0xcf800000
+; GFX12-ISEL-NEXT: s_cselect_b32 s0, -1, s16
+; GFX12-ISEL-NEXT: s_cselect_b32 s14, -1, s14
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s15, s15
+; GFX12-ISEL-NEXT: s_cmp_nge_f32 s2, 0
+; GFX12-ISEL-NEXT: s_cvt_u32_f32 s16, s17
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v0, s14 :: v_dual_mov_b32 v1, s0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s15, 0, s15
+; GFX12-ISEL-NEXT: s_cselect_b32 s16, 0, s16
+; GFX12-ISEL-NEXT: s_cmp_gt_f32 s2, 0x5f7fffff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: s_cselect_b32 s2, -1, s16
+; GFX12-ISEL-NEXT: s_cselect_b32 s15, -1, s15
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, 0
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, 0
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v5, 0
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v7, 0
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, 0
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v10, s6 :: v_dual_mov_b32 v11, 0
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v12, s3 :: v_dual_mov_b32 v13, 0
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v14, s7 :: v_dual_mov_b32 v15, 0
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v12, s15
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_unsigned_v8f16_v8i64:
>From f4749cb68174b31c25ef3e6f1e7c9ee72f4cdeed Mon Sep 17 00:00:00 2001
From: Nathaniel McCallum <nathaniel at mccallum.life>
Date: Mon, 10 Aug 2026 08:44:50 -0400
Subject: [PATCH 4/7] [AArch64][GlobalISel] Add saturating f16 to 128-bit
legalizer test (NFC)
The result recorded here is wrong: the legalizer narrows the saturating
conversion to i64, so it saturates to the bounds of an i64 rather than an i128,
and pairs the result with a zero constant instead of sign-extending it.
The existing fptosi-sat tests cover the same conversion, but their check lines
are whole functions of generated code; this pins the legalizer output directly.
---
.../GlobalISel/legalize-fptosi-sat.mir | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptosi-sat.mir
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptosi-sat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptosi-sat.mir
new file mode 100644
index 0000000000000..c967e0c74f1cb
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptosi-sat.mir
@@ -0,0 +1,30 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=aarch64 -mattr=+fullfp16 -run-pass=legalizer %s -o - | FileCheck %s
+
+# FIXME: the checks below record an incorrect result. The saturating conversion
+# is narrowed to i64, which saturates to the bounds of an i64 rather than an
+# i128, and the upper half is set to zero instead of being sign-extended.
+
+---
+name: fptosi_sat_s128_s16
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $h0
+
+ ; CHECK-LABEL: name: fptosi_sat_s128_s16
+ ; CHECK: liveins: $h0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f16) = COPY $h0
+ ; CHECK-NEXT: [[FPTOSI_SAT:%[0-9]+]]:_(i64) = G_FPTOSI_SAT [[COPY]](f16)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: $x0 = COPY [[FPTOSI_SAT]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[C]](i64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
+ %0:_(f16) = COPY $h0
+ %1:_(i128) = G_FPTOSI_SAT %0
+ %2:_(i64), %3:_(i64) = G_UNMERGE_VALUES %1
+ $x0 = COPY %2
+ $x1 = COPY %3
+ RET_ReallyLR implicit $x0, implicit $x1
+...
>From 40b823c47c38291474254fa4c6d27849c2b8cb7c Mon Sep 17 00:00:00 2001
From: Nathaniel McCallum <nathaniel at mccallum.life>
Date: Mon, 10 Aug 2026 08:46:27 -0400
Subject: [PATCH 5/7] [AArch64][GlobalISel] Fix saturating f16 to 128-bit
conversions
The legalizer narrowed the result of a saturating conversion to i64 whenever the
source was a 16-bit float, on the grounds that the range of an f16 fits into an
i17. The range argument holds for finite values, but the operation being
narrowed is a saturating one, and its clamp bounds are those of the
destination width. Narrowing therefore saturates at the wrong bounds. The
narrowed value was also zero-extended rather than sign-extended, because the
generic helper derives signedness from G_FPTOSI alone:
fptosi.sat.i128.f16(-1.0) gave 0x0..0FFFFFFFFFFFFFFFF, expected -1
fptosi.sat.i128.f16(inf) gave the largest i64, expected the largest i128
fptosi.sat.i128.f16(-inf) gave 0x0..08000000000000000, expected the smallest
i128
fptoui.sat.i128.f16(inf) gave the largest u64, expected the largest u128
Drop the rule so these fall through to the generic expansion, as f32 and f64
sources already do. Nothing is lost: the lowering expands the saturation at the
result width and narrows the non-saturating conversion inside it, so the emitted
code still uses fcvtzs on the half directly.
The operations were added in feac761f3797 with the wrong output already recorded
as expected in the existing tests.
---
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 7 -
.../GlobalISel/legalize-fptosi-sat.mir | 29 +-
.../test/CodeGen/AArch64/fptosi-sat-scalar.ll | 80 ++-
.../test/CodeGen/AArch64/fptosi-sat-vector.ll | 580 ++++++++++++++----
.../test/CodeGen/AArch64/fptoui-sat-scalar.ll | 44 +-
.../test/CodeGen/AArch64/fptoui-sat-vector.ll | 395 ++++++++----
6 files changed, 871 insertions(+), 264 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 2263712120de8..992d36558711d 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -974,13 +974,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
// Handle types larger than i64 by scalarizing/lowering.
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.scalarizeIf(scalarOrEltWiderThan(1, 64), 1)
- // The range of a fp16 value fits into an i17, so we can lower the width
- // to i64.
- .narrowScalarIf(
- [=](const LegalityQuery &Query) {
- return Query.Types[1] == f16 && Query.Types[0].getSizeInBits() > 64;
- },
- changeTo(0, i64))
.lowerIf(::any(scalarWiderThan(0, 64), scalarWiderThan(1, 64)), 0)
.moreElementsToNextPow2(0)
.widenScalarToNextPow2(0, /*MinSize=*/32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptosi-sat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptosi-sat.mir
index c967e0c74f1cb..1c714d410c1bb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptosi-sat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptosi-sat.mir
@@ -1,9 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=aarch64 -mattr=+fullfp16 -run-pass=legalizer %s -o - | FileCheck %s
-# FIXME: the checks below record an incorrect result. The saturating conversion
-# is narrowed to i64, which saturates to the bounds of an i64 rather than an
-# i128, and the upper half is set to zero instead of being sign-extended.
+# The saturation bounds of G_FPTOSI_SAT are those of its result type, so this is
+# lowered rather than narrowed to a legal integer width.
---
name: fptosi_sat_s128_s16
@@ -16,10 +15,26 @@ body: |
; CHECK: liveins: $h0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f16) = COPY $h0
- ; CHECK-NEXT: [[FPTOSI_SAT:%[0-9]+]]:_(i64) = G_FPTOSI_SAT [[COPY]](f16)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: $x0 = COPY [[FPTOSI_SAT]](i64)
- ; CHECK-NEXT: $x1 = COPY [[C]](i64)
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(i64) = G_FPTOSI [[COPY]](f16)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 63
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i64) = G_ASHR [[FPTOSI]], [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half -6.550400e+04
+ ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(i32) = G_FCMP floatpred(ult), [[COPY]](f16), [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i64) = G_SELECT [[FCMP]](i32), [[C2]], [[FPTOSI]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(i64) = G_SELECT [[FCMP]](i32), [[C3]], [[ASHR]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f16) = G_FCONSTANT half 6.550400e+04
+ ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(i32) = G_FCMP floatpred(ogt), [[COPY]](f16), [[C4]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(i64) = G_SELECT [[FCMP1]](i32), [[C5]], [[SELECT]]
+ ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(i64) = G_SELECT [[FCMP1]](i32), [[C6]], [[SELECT1]]
+ ; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(i32) = G_FCMP floatpred(uno), [[COPY]](f16), [[COPY]]
+ ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(i64) = G_SELECT [[FCMP2]](i32), [[C2]], [[SELECT2]]
+ ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(i64) = G_SELECT [[FCMP2]](i32), [[C2]], [[SELECT3]]
+ ; CHECK-NEXT: $x0 = COPY [[SELECT4]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[SELECT5]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%0:_(f16) = COPY $h0
%1:_(i128) = G_FPTOSI_SAT %0
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
index f95d338198c4d..921e87f15c272 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
@@ -877,14 +877,46 @@ define i100 @test_signed_i100_f16(half %f) nounwind {
; CHECK-GI-CVT-LABEL: test_signed_i100_f16:
; CHECK-GI-CVT: // %bb.0:
; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: mov x1, xzr
-; CHECK-GI-CVT-NEXT: fcvtzs x0, s0
+; CHECK-GI-CVT-NEXT: mov w9, #57344 // =0xe000
+; CHECK-GI-CVT-NEXT: mov w10, #57344 // =0xe000
+; CHECK-GI-CVT-NEXT: movk w9, #51071, lsl #16
+; CHECK-GI-CVT-NEXT: movk w10, #18303, lsl #16
+; CHECK-GI-CVT-NEXT: fmov s1, w9
+; CHECK-GI-CVT-NEXT: fcvtzs x8, s0
+; CHECK-GI-CVT-NEXT: fcmp s0, s1
+; CHECK-GI-CVT-NEXT: fmov s1, w10
+; CHECK-GI-CVT-NEXT: mov x10, #34359738368 // =0x800000000
+; CHECK-GI-CVT-NEXT: asr x9, x8, #63
+; CHECK-GI-CVT-NEXT: csel x8, xzr, x8, lt
+; CHECK-GI-CVT-NEXT: csel x9, x10, x9, lt
+; CHECK-GI-CVT-NEXT: fcmp s0, s1
+; CHECK-GI-CVT-NEXT: mov x10, #34359738367 // =0x7ffffffff
+; CHECK-GI-CVT-NEXT: csinv x8, x8, xzr, le
+; CHECK-GI-CVT-NEXT: csel x9, x10, x9, gt
+; CHECK-GI-CVT-NEXT: fcmp s0, s0
+; CHECK-GI-CVT-NEXT: csel x0, xzr, x8, vs
+; CHECK-GI-CVT-NEXT: csel x1, xzr, x9, vs
; CHECK-GI-CVT-NEXT: ret
;
; CHECK-GI-FP16-LABEL: test_signed_i100_f16:
; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzs x0, h0
-; CHECK-GI-FP16-NEXT: mov x1, xzr
+; CHECK-GI-FP16-NEXT: adrp x8, .LCPI28_1
+; CHECK-GI-FP16-NEXT: fcvtzs x9, h0
+; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI28_1]
+; CHECK-GI-FP16-NEXT: adrp x8, .LCPI28_0
+; CHECK-GI-FP16-NEXT: fcmp h0, h1
+; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI28_0]
+; CHECK-GI-FP16-NEXT: mov x8, #34359738368 // =0x800000000
+; CHECK-GI-FP16-NEXT: asr x10, x9, #63
+; CHECK-GI-FP16-NEXT: csel x9, xzr, x9, lt
+; CHECK-GI-FP16-NEXT: csel x8, x8, x10, lt
+; CHECK-GI-FP16-NEXT: fcmp h0, h1
+; CHECK-GI-FP16-NEXT: mov x10, #34359738367 // =0x7ffffffff
+; CHECK-GI-FP16-NEXT: csinv x9, x9, xzr, le
+; CHECK-GI-FP16-NEXT: csel x8, x10, x8, gt
+; CHECK-GI-FP16-NEXT: fcmp h0, h0
+; CHECK-GI-FP16-NEXT: csel x0, xzr, x9, vs
+; CHECK-GI-FP16-NEXT: csel x1, xzr, x8, vs
; CHECK-GI-FP16-NEXT: ret
%x = call i100 @llvm.fptosi.sat.i100.f16(half %f)
ret i100 %x
@@ -919,14 +951,46 @@ define i128 @test_signed_i128_f16(half %f) nounwind {
; CHECK-GI-CVT-LABEL: test_signed_i128_f16:
; CHECK-GI-CVT: // %bb.0:
; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: mov x1, xzr
-; CHECK-GI-CVT-NEXT: fcvtzs x0, s0
+; CHECK-GI-CVT-NEXT: mov w9, #57344 // =0xe000
+; CHECK-GI-CVT-NEXT: mov w10, #57344 // =0xe000
+; CHECK-GI-CVT-NEXT: movk w9, #51071, lsl #16
+; CHECK-GI-CVT-NEXT: movk w10, #18303, lsl #16
+; CHECK-GI-CVT-NEXT: fmov s1, w9
+; CHECK-GI-CVT-NEXT: fcvtzs x8, s0
+; CHECK-GI-CVT-NEXT: fcmp s0, s1
+; CHECK-GI-CVT-NEXT: fmov s1, w10
+; CHECK-GI-CVT-NEXT: mov x10, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-CVT-NEXT: asr x9, x8, #63
+; CHECK-GI-CVT-NEXT: csel x8, xzr, x8, lt
+; CHECK-GI-CVT-NEXT: csel x9, x10, x9, lt
+; CHECK-GI-CVT-NEXT: fcmp s0, s1
+; CHECK-GI-CVT-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-GI-CVT-NEXT: csinv x8, x8, xzr, le
+; CHECK-GI-CVT-NEXT: csel x9, x10, x9, gt
+; CHECK-GI-CVT-NEXT: fcmp s0, s0
+; CHECK-GI-CVT-NEXT: csel x0, xzr, x8, vs
+; CHECK-GI-CVT-NEXT: csel x1, xzr, x9, vs
; CHECK-GI-CVT-NEXT: ret
;
; CHECK-GI-FP16-LABEL: test_signed_i128_f16:
; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzs x0, h0
-; CHECK-GI-FP16-NEXT: mov x1, xzr
+; CHECK-GI-FP16-NEXT: adrp x8, .LCPI29_1
+; CHECK-GI-FP16-NEXT: fcvtzs x9, h0
+; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI29_1]
+; CHECK-GI-FP16-NEXT: adrp x8, .LCPI29_0
+; CHECK-GI-FP16-NEXT: fcmp h0, h1
+; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI29_0]
+; CHECK-GI-FP16-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-FP16-NEXT: asr x10, x9, #63
+; CHECK-GI-FP16-NEXT: csel x9, xzr, x9, lt
+; CHECK-GI-FP16-NEXT: csel x8, x8, x10, lt
+; CHECK-GI-FP16-NEXT: fcmp h0, h1
+; CHECK-GI-FP16-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-GI-FP16-NEXT: csinv x9, x9, xzr, le
+; CHECK-GI-FP16-NEXT: csel x8, x10, x8, gt
+; CHECK-GI-FP16-NEXT: fcmp h0, h0
+; CHECK-GI-FP16-NEXT: csel x0, xzr, x9, vs
+; CHECK-GI-FP16-NEXT: csel x1, xzr, x8, vs
; CHECK-GI-FP16-NEXT: ret
%x = call i128 @llvm.fptosi.sat.i128.f16(half %f)
ret i128 %x
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index 145aef9123a4e..fcceef66470c7 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -3237,37 +3237,123 @@ define <4 x i100> @test_signed_v4f16_v4i100(<4 x half> %f) {
; CHECK-GI-CVT-LABEL: test_signed_v4f16_v4i100:
; CHECK-GI-CVT: // %bb.0:
; CHECK-GI-CVT-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-CVT-NEXT: mov h1, v0.h[1]
-; CHECK-GI-CVT-NEXT: mov h2, v0.h[2]
-; CHECK-GI-CVT-NEXT: mov x1, xzr
-; CHECK-GI-CVT-NEXT: mov h3, v0.h[3]
-; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: mov x3, xzr
-; CHECK-GI-CVT-NEXT: mov x5, xzr
-; CHECK-GI-CVT-NEXT: mov x7, xzr
-; CHECK-GI-CVT-NEXT: fcvt s1, h1
-; CHECK-GI-CVT-NEXT: fcvt s2, h2
+; CHECK-GI-CVT-NEXT: fcvt s2, h0
+; CHECK-GI-CVT-NEXT: mov w9, #57344 // =0xe000
+; CHECK-GI-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-GI-CVT-NEXT: movk w9, #51071, lsl #16
+; CHECK-GI-CVT-NEXT: mov x11, #34359738368 // =0x800000000
+; CHECK-GI-CVT-NEXT: mov h5, v0.h[2]
+; CHECK-GI-CVT-NEXT: fmov s1, w9
+; CHECK-GI-CVT-NEXT: mov w9, #57344 // =0xe000
+; CHECK-GI-CVT-NEXT: mov h0, v0.h[3]
+; CHECK-GI-CVT-NEXT: movk w9, #18303, lsl #16
+; CHECK-GI-CVT-NEXT: fcvtzs x8, s2
+; CHECK-GI-CVT-NEXT: fmov s4, w9
; CHECK-GI-CVT-NEXT: fcvt s3, h3
-; CHECK-GI-CVT-NEXT: fcvtzs x0, s0
-; CHECK-GI-CVT-NEXT: fcvtzs x2, s1
-; CHECK-GI-CVT-NEXT: fcvtzs x4, s2
-; CHECK-GI-CVT-NEXT: fcvtzs x6, s3
+; CHECK-GI-CVT-NEXT: fcmp s2, s1
+; CHECK-GI-CVT-NEXT: fcvt s0, h0
+; CHECK-GI-CVT-NEXT: asr x10, x8, #63
+; CHECK-GI-CVT-NEXT: csel x8, xzr, x8, lt
+; CHECK-GI-CVT-NEXT: fcvtzs x12, s3
+; CHECK-GI-CVT-NEXT: csel x9, x11, x10, lt
+; CHECK-GI-CVT-NEXT: fcmp s2, s4
+; CHECK-GI-CVT-NEXT: mov x10, #34359738367 // =0x7ffffffff
+; CHECK-GI-CVT-NEXT: csinv x8, x8, xzr, le
+; CHECK-GI-CVT-NEXT: csel x9, x10, x9, gt
+; CHECK-GI-CVT-NEXT: fcmp s2, s2
+; CHECK-GI-CVT-NEXT: fcvt s2, h5
+; CHECK-GI-CVT-NEXT: csel x0, xzr, x8, vs
+; CHECK-GI-CVT-NEXT: csel x1, xzr, x9, vs
+; CHECK-GI-CVT-NEXT: fcmp s3, s1
+; CHECK-GI-CVT-NEXT: asr x8, x12, #63
+; CHECK-GI-CVT-NEXT: csel x9, xzr, x12, lt
+; CHECK-GI-CVT-NEXT: csel x8, x11, x8, lt
+; CHECK-GI-CVT-NEXT: fcmp s3, s4
+; CHECK-GI-CVT-NEXT: fcvtzs x12, s2
+; CHECK-GI-CVT-NEXT: csinv x9, x9, xzr, le
+; CHECK-GI-CVT-NEXT: csel x8, x10, x8, gt
+; CHECK-GI-CVT-NEXT: fcmp s3, s3
+; CHECK-GI-CVT-NEXT: csel x2, xzr, x9, vs
+; CHECK-GI-CVT-NEXT: csel x3, xzr, x8, vs
+; CHECK-GI-CVT-NEXT: fcmp s2, s1
+; CHECK-GI-CVT-NEXT: asr x8, x12, #63
+; CHECK-GI-CVT-NEXT: csel x9, xzr, x12, lt
+; CHECK-GI-CVT-NEXT: csel x8, x11, x8, lt
+; CHECK-GI-CVT-NEXT: fcmp s2, s4
+; CHECK-GI-CVT-NEXT: fcvtzs x12, s0
+; CHECK-GI-CVT-NEXT: csinv x9, x9, xzr, le
+; CHECK-GI-CVT-NEXT: csel x8, x10, x8, gt
+; CHECK-GI-CVT-NEXT: fcmp s2, s2
+; CHECK-GI-CVT-NEXT: csel x4, xzr, x9, vs
+; CHECK-GI-CVT-NEXT: csel x5, xzr, x8, vs
+; CHECK-GI-CVT-NEXT: fcmp s0, s1
+; CHECK-GI-CVT-NEXT: asr x8, x12, #63
+; CHECK-GI-CVT-NEXT: csel x9, xzr, x12, lt
+; CHECK-GI-CVT-NEXT: csel x8, x11, x8, lt
+; CHECK-GI-CVT-NEXT: fcmp s0, s4
+; CHECK-GI-CVT-NEXT: csinv x9, x9, xzr, le
+; CHECK-GI-CVT-NEXT: csel x8, x10, x8, gt
+; CHECK-GI-CVT-NEXT: fcmp s0, s0
+; CHECK-GI-CVT-NEXT: csel x6, xzr, x9, vs
+; CHECK-GI-CVT-NEXT: csel x7, xzr, x8, vs
; CHECK-GI-CVT-NEXT: ret
;
; CHECK-GI-FP16-LABEL: test_signed_v4f16_v4i100:
; CHECK-GI-FP16: // %bb.0:
; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-GI-FP16-NEXT: mov x1, xzr
-; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
-; CHECK-GI-FP16-NEXT: fcvtzs x0, h0
-; CHECK-GI-FP16-NEXT: mov x3, xzr
-; CHECK-GI-FP16-NEXT: mov x5, xzr
-; CHECK-GI-FP16-NEXT: mov x7, xzr
-; CHECK-GI-FP16-NEXT: fcvtzs x2, h1
-; CHECK-GI-FP16-NEXT: fcvtzs x4, h2
-; CHECK-GI-FP16-NEXT: fcvtzs x6, h3
+; CHECK-GI-FP16-NEXT: adrp x8, .LCPI64_1
+; CHECK-GI-FP16-NEXT: fcvtzs x9, h0
+; CHECK-GI-FP16-NEXT: mov h2, v0.h[1]
+; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI64_1]
+; CHECK-GI-FP16-NEXT: adrp x8, .LCPI64_0
+; CHECK-GI-FP16-NEXT: mov x10, #34359738368 // =0x800000000
+; CHECK-GI-FP16-NEXT: ldr h3, [x8, :lo12:.LCPI64_0]
+; CHECK-GI-FP16-NEXT: mov x11, #34359738367 // =0x7ffffffff
+; CHECK-GI-FP16-NEXT: mov h4, v0.h[2]
+; CHECK-GI-FP16-NEXT: fcmp h0, h1
+; CHECK-GI-FP16-NEXT: asr x8, x9, #63
+; CHECK-GI-FP16-NEXT: fcvtzs x12, h2
+; CHECK-GI-FP16-NEXT: csel x9, xzr, x9, lt
+; CHECK-GI-FP16-NEXT: csel x8, x10, x8, lt
+; CHECK-GI-FP16-NEXT: fcmp h0, h3
+; CHECK-GI-FP16-NEXT: csinv x9, x9, xzr, le
+; CHECK-GI-FP16-NEXT: csel x8, x11, x8, gt
+; CHECK-GI-FP16-NEXT: fcmp h0, h0
+; CHECK-GI-FP16-NEXT: mov h0, v0.h[3]
+; CHECK-GI-FP16-NEXT: csel x0, xzr, x9, vs
+; CHECK-GI-FP16-NEXT: csel x1, xzr, x8, vs
+; CHECK-GI-FP16-NEXT: fcmp h2, h1
+; CHECK-GI-FP16-NEXT: asr x8, x12, #63
+; CHECK-GI-FP16-NEXT: csel x9, xzr, x12, lt
+; CHECK-GI-FP16-NEXT: csel x8, x10, x8, lt
+; CHECK-GI-FP16-NEXT: fcmp h2, h3
+; CHECK-GI-FP16-NEXT: fcvtzs x12, h4
+; CHECK-GI-FP16-NEXT: csinv x9, x9, xzr, le
+; CHECK-GI-FP16-NEXT: csel x8, x11, x8, gt
+; CHECK-GI-FP16-NEXT: fcmp h2, h2
+; CHECK-GI-FP16-NEXT: csel x2, xzr, x9, vs
+; CHECK-GI-FP16-NEXT: csel x3, xzr, x8, vs
+; CHECK-GI-FP16-NEXT: fcmp h4, h1
+; CHECK-GI-FP16-NEXT: asr x8, x12, #63
+; CHECK-GI-FP16-NEXT: csel x9, xzr, x12, lt
+; CHECK-GI-FP16-NEXT: csel x8, x10, x8, lt
+; CHECK-GI-FP16-NEXT: fcmp h4, h3
+; CHECK-GI-FP16-NEXT: fcvtzs x12, h0
+; CHECK-GI-FP16-NEXT: csinv x9, x9, xzr, le
+; CHECK-GI-FP16-NEXT: csel x8, x11, x8, gt
+; CHECK-GI-FP16-NEXT: fcmp h4, h4
+; CHECK-GI-FP16-NEXT: csel x4, xzr, x9, vs
+; CHECK-GI-FP16-NEXT: csel x5, xzr, x8, vs
+; CHECK-GI-FP16-NEXT: fcmp h0, h1
+; CHECK-GI-FP16-NEXT: asr x8, x12, #63
+; CHECK-GI-FP16-NEXT: csel x9, xzr, x12, lt
+; CHECK-GI-FP16-NEXT: csel x8, x10, x8, lt
+; CHECK-GI-FP16-NEXT: fcmp h0, h3
+; CHECK-GI-FP16-NEXT: csinv x9, x9, xzr, le
+; CHECK-GI-FP16-NEXT: csel x8, x11, x8, gt
+; CHECK-GI-FP16-NEXT: fcmp h0, h0
+; CHECK-GI-FP16-NEXT: csel x6, xzr, x9, vs
+; CHECK-GI-FP16-NEXT: csel x7, xzr, x8, vs
; CHECK-GI-FP16-NEXT: ret
%x = call <4 x i100> @llvm.fptosi.sat.v4f16.v4i100(<4 x half> %f)
ret <4 x i100> %x
@@ -3377,37 +3463,123 @@ define <4 x i128> @test_signed_v4f16_v4i128(<4 x half> %f) {
; CHECK-GI-CVT-LABEL: test_signed_v4f16_v4i128:
; CHECK-GI-CVT: // %bb.0:
; CHECK-GI-CVT-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-CVT-NEXT: mov h1, v0.h[1]
-; CHECK-GI-CVT-NEXT: mov h2, v0.h[2]
-; CHECK-GI-CVT-NEXT: mov x1, xzr
-; CHECK-GI-CVT-NEXT: mov h3, v0.h[3]
-; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: mov x3, xzr
-; CHECK-GI-CVT-NEXT: mov x5, xzr
-; CHECK-GI-CVT-NEXT: mov x7, xzr
-; CHECK-GI-CVT-NEXT: fcvt s1, h1
-; CHECK-GI-CVT-NEXT: fcvt s2, h2
+; CHECK-GI-CVT-NEXT: fcvt s2, h0
+; CHECK-GI-CVT-NEXT: mov w9, #57344 // =0xe000
+; CHECK-GI-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-GI-CVT-NEXT: movk w9, #51071, lsl #16
+; CHECK-GI-CVT-NEXT: mov x11, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-CVT-NEXT: mov h5, v0.h[2]
+; CHECK-GI-CVT-NEXT: fmov s1, w9
+; CHECK-GI-CVT-NEXT: mov w9, #57344 // =0xe000
+; CHECK-GI-CVT-NEXT: mov h0, v0.h[3]
+; CHECK-GI-CVT-NEXT: movk w9, #18303, lsl #16
+; CHECK-GI-CVT-NEXT: fcvtzs x8, s2
+; CHECK-GI-CVT-NEXT: fmov s4, w9
; CHECK-GI-CVT-NEXT: fcvt s3, h3
-; CHECK-GI-CVT-NEXT: fcvtzs x0, s0
-; CHECK-GI-CVT-NEXT: fcvtzs x2, s1
-; CHECK-GI-CVT-NEXT: fcvtzs x4, s2
-; CHECK-GI-CVT-NEXT: fcvtzs x6, s3
+; CHECK-GI-CVT-NEXT: fcmp s2, s1
+; CHECK-GI-CVT-NEXT: fcvt s0, h0
+; CHECK-GI-CVT-NEXT: asr x10, x8, #63
+; CHECK-GI-CVT-NEXT: csel x8, xzr, x8, lt
+; CHECK-GI-CVT-NEXT: fcvtzs x12, s3
+; CHECK-GI-CVT-NEXT: csel x9, x11, x10, lt
+; CHECK-GI-CVT-NEXT: fcmp s2, s4
+; CHECK-GI-CVT-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-GI-CVT-NEXT: csinv x8, x8, xzr, le
+; CHECK-GI-CVT-NEXT: csel x9, x10, x9, gt
+; CHECK-GI-CVT-NEXT: fcmp s2, s2
+; CHECK-GI-CVT-NEXT: fcvt s2, h5
+; CHECK-GI-CVT-NEXT: csel x0, xzr, x8, vs
+; CHECK-GI-CVT-NEXT: csel x1, xzr, x9, vs
+; CHECK-GI-CVT-NEXT: fcmp s3, s1
+; CHECK-GI-CVT-NEXT: asr x8, x12, #63
+; CHECK-GI-CVT-NEXT: csel x9, xzr, x12, lt
+; CHECK-GI-CVT-NEXT: csel x8, x11, x8, lt
+; CHECK-GI-CVT-NEXT: fcmp s3, s4
+; CHECK-GI-CVT-NEXT: fcvtzs x12, s2
+; CHECK-GI-CVT-NEXT: csinv x9, x9, xzr, le
+; CHECK-GI-CVT-NEXT: csel x8, x10, x8, gt
+; CHECK-GI-CVT-NEXT: fcmp s3, s3
+; CHECK-GI-CVT-NEXT: csel x2, xzr, x9, vs
+; CHECK-GI-CVT-NEXT: csel x3, xzr, x8, vs
+; CHECK-GI-CVT-NEXT: fcmp s2, s1
+; CHECK-GI-CVT-NEXT: asr x8, x12, #63
+; CHECK-GI-CVT-NEXT: csel x9, xzr, x12, lt
+; CHECK-GI-CVT-NEXT: csel x8, x11, x8, lt
+; CHECK-GI-CVT-NEXT: fcmp s2, s4
+; CHECK-GI-CVT-NEXT: fcvtzs x12, s0
+; CHECK-GI-CVT-NEXT: csinv x9, x9, xzr, le
+; CHECK-GI-CVT-NEXT: csel x8, x10, x8, gt
+; CHECK-GI-CVT-NEXT: fcmp s2, s2
+; CHECK-GI-CVT-NEXT: csel x4, xzr, x9, vs
+; CHECK-GI-CVT-NEXT: csel x5, xzr, x8, vs
+; CHECK-GI-CVT-NEXT: fcmp s0, s1
+; CHECK-GI-CVT-NEXT: asr x8, x12, #63
+; CHECK-GI-CVT-NEXT: csel x9, xzr, x12, lt
+; CHECK-GI-CVT-NEXT: csel x8, x11, x8, lt
+; CHECK-GI-CVT-NEXT: fcmp s0, s4
+; CHECK-GI-CVT-NEXT: csinv x9, x9, xzr, le
+; CHECK-GI-CVT-NEXT: csel x8, x10, x8, gt
+; CHECK-GI-CVT-NEXT: fcmp s0, s0
+; CHECK-GI-CVT-NEXT: csel x6, xzr, x9, vs
+; CHECK-GI-CVT-NEXT: csel x7, xzr, x8, vs
; CHECK-GI-CVT-NEXT: ret
;
; CHECK-GI-FP16-LABEL: test_signed_v4f16_v4i128:
; CHECK-GI-FP16: // %bb.0:
; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-GI-FP16-NEXT: mov x1, xzr
-; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
-; CHECK-GI-FP16-NEXT: fcvtzs x0, h0
-; CHECK-GI-FP16-NEXT: mov x3, xzr
-; CHECK-GI-FP16-NEXT: mov x5, xzr
-; CHECK-GI-FP16-NEXT: mov x7, xzr
-; CHECK-GI-FP16-NEXT: fcvtzs x2, h1
-; CHECK-GI-FP16-NEXT: fcvtzs x4, h2
-; CHECK-GI-FP16-NEXT: fcvtzs x6, h3
+; CHECK-GI-FP16-NEXT: adrp x8, .LCPI65_1
+; CHECK-GI-FP16-NEXT: fcvtzs x9, h0
+; CHECK-GI-FP16-NEXT: mov h2, v0.h[1]
+; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI65_1]
+; CHECK-GI-FP16-NEXT: adrp x8, .LCPI65_0
+; CHECK-GI-FP16-NEXT: mov x10, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-FP16-NEXT: ldr h3, [x8, :lo12:.LCPI65_0]
+; CHECK-GI-FP16-NEXT: mov x11, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-GI-FP16-NEXT: mov h4, v0.h[2]
+; CHECK-GI-FP16-NEXT: fcmp h0, h1
+; CHECK-GI-FP16-NEXT: asr x8, x9, #63
+; CHECK-GI-FP16-NEXT: fcvtzs x12, h2
+; CHECK-GI-FP16-NEXT: csel x9, xzr, x9, lt
+; CHECK-GI-FP16-NEXT: csel x8, x10, x8, lt
+; CHECK-GI-FP16-NEXT: fcmp h0, h3
+; CHECK-GI-FP16-NEXT: csinv x9, x9, xzr, le
+; CHECK-GI-FP16-NEXT: csel x8, x11, x8, gt
+; CHECK-GI-FP16-NEXT: fcmp h0, h0
+; CHECK-GI-FP16-NEXT: mov h0, v0.h[3]
+; CHECK-GI-FP16-NEXT: csel x0, xzr, x9, vs
+; CHECK-GI-FP16-NEXT: csel x1, xzr, x8, vs
+; CHECK-GI-FP16-NEXT: fcmp h2, h1
+; CHECK-GI-FP16-NEXT: asr x8, x12, #63
+; CHECK-GI-FP16-NEXT: csel x9, xzr, x12, lt
+; CHECK-GI-FP16-NEXT: csel x8, x10, x8, lt
+; CHECK-GI-FP16-NEXT: fcmp h2, h3
+; CHECK-GI-FP16-NEXT: fcvtzs x12, h4
+; CHECK-GI-FP16-NEXT: csinv x9, x9, xzr, le
+; CHECK-GI-FP16-NEXT: csel x8, x11, x8, gt
+; CHECK-GI-FP16-NEXT: fcmp h2, h2
+; CHECK-GI-FP16-NEXT: csel x2, xzr, x9, vs
+; CHECK-GI-FP16-NEXT: csel x3, xzr, x8, vs
+; CHECK-GI-FP16-NEXT: fcmp h4, h1
+; CHECK-GI-FP16-NEXT: asr x8, x12, #63
+; CHECK-GI-FP16-NEXT: csel x9, xzr, x12, lt
+; CHECK-GI-FP16-NEXT: csel x8, x10, x8, lt
+; CHECK-GI-FP16-NEXT: fcmp h4, h3
+; CHECK-GI-FP16-NEXT: fcvtzs x12, h0
+; CHECK-GI-FP16-NEXT: csinv x9, x9, xzr, le
+; CHECK-GI-FP16-NEXT: csel x8, x11, x8, gt
+; CHECK-GI-FP16-NEXT: fcmp h4, h4
+; CHECK-GI-FP16-NEXT: csel x4, xzr, x9, vs
+; CHECK-GI-FP16-NEXT: csel x5, xzr, x8, vs
+; CHECK-GI-FP16-NEXT: fcmp h0, h1
+; CHECK-GI-FP16-NEXT: asr x8, x12, #63
+; CHECK-GI-FP16-NEXT: csel x9, xzr, x12, lt
+; CHECK-GI-FP16-NEXT: csel x8, x10, x8, lt
+; CHECK-GI-FP16-NEXT: fcmp h0, h3
+; CHECK-GI-FP16-NEXT: csinv x9, x9, xzr, le
+; CHECK-GI-FP16-NEXT: csel x8, x11, x8, gt
+; CHECK-GI-FP16-NEXT: fcmp h0, h0
+; CHECK-GI-FP16-NEXT: csel x6, xzr, x9, vs
+; CHECK-GI-FP16-NEXT: csel x7, xzr, x8, vs
; CHECK-GI-FP16-NEXT: ret
%x = call <4 x i128> @llvm.fptosi.sat.v4f16.v4i128(<4 x half> %f)
ret <4 x i128> %x
@@ -4209,86 +4381,260 @@ define <8 x i128> @test_signed_v8f16_v8i128(<8 x half> %f) {
;
; CHECK-GI-CVT-LABEL: test_signed_v8f16_v8i128:
; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: mov h1, v0.h[1]
-; CHECK-GI-CVT-NEXT: mov h2, v0.h[2]
-; CHECK-GI-CVT-NEXT: mov h3, v0.h[3]
-; CHECK-GI-CVT-NEXT: mov h4, v0.h[4]
-; CHECK-GI-CVT-NEXT: fcvt s5, h0
-; CHECK-GI-CVT-NEXT: mov h6, v0.h[5]
-; CHECK-GI-CVT-NEXT: mov h7, v0.h[6]
+; CHECK-GI-CVT-NEXT: fcvt s3, h0
+; CHECK-GI-CVT-NEXT: mov w10, #57344 // =0xe000
+; CHECK-GI-CVT-NEXT: mov h2, v0.h[1]
+; CHECK-GI-CVT-NEXT: movk w10, #51071, lsl #16
+; CHECK-GI-CVT-NEXT: mov w11, #57344 // =0xe000
+; CHECK-GI-CVT-NEXT: mov h5, v0.h[2]
+; CHECK-GI-CVT-NEXT: fmov s1, w10
+; CHECK-GI-CVT-NEXT: movk w11, #18303, lsl #16
+; CHECK-GI-CVT-NEXT: mov x10, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-CVT-NEXT: fcvtzs x9, s3
+; CHECK-GI-CVT-NEXT: fcvt s4, h2
+; CHECK-GI-CVT-NEXT: fmov s2, w11
+; CHECK-GI-CVT-NEXT: fcmp s3, s1
+; CHECK-GI-CVT-NEXT: asr x12, x9, #63
+; CHECK-GI-CVT-NEXT: csel x11, xzr, x9, lt
+; CHECK-GI-CVT-NEXT: mov x9, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-GI-CVT-NEXT: fcvtzs x13, s4
+; CHECK-GI-CVT-NEXT: csel x12, x10, x12, lt
+; CHECK-GI-CVT-NEXT: fcmp s3, s2
+; CHECK-GI-CVT-NEXT: csinv x11, x11, xzr, le
+; CHECK-GI-CVT-NEXT: csel x14, x9, x12, gt
+; CHECK-GI-CVT-NEXT: fcmp s3, s3
+; CHECK-GI-CVT-NEXT: fcvt s3, h5
+; CHECK-GI-CVT-NEXT: mov h5, v0.h[3]
+; CHECK-GI-CVT-NEXT: csel x12, xzr, x11, vs
+; CHECK-GI-CVT-NEXT: csel x11, xzr, x14, vs
+; CHECK-GI-CVT-NEXT: fcmp s4, s1
+; CHECK-GI-CVT-NEXT: asr x14, x13, #63
+; CHECK-GI-CVT-NEXT: fcvtzs x15, s3
+; CHECK-GI-CVT-NEXT: csel x13, xzr, x13, lt
+; CHECK-GI-CVT-NEXT: csel x14, x10, x14, lt
+; CHECK-GI-CVT-NEXT: fcmp s4, s2
+; CHECK-GI-CVT-NEXT: csinv x13, x13, xzr, le
+; CHECK-GI-CVT-NEXT: csel x16, x9, x14, gt
+; CHECK-GI-CVT-NEXT: fcmp s4, s4
+; CHECK-GI-CVT-NEXT: fcvt s4, h5
+; CHECK-GI-CVT-NEXT: mov h5, v0.h[4]
+; CHECK-GI-CVT-NEXT: csel x14, xzr, x13, vs
+; CHECK-GI-CVT-NEXT: csel x13, xzr, x16, vs
+; CHECK-GI-CVT-NEXT: fcmp s3, s1
+; CHECK-GI-CVT-NEXT: asr x16, x15, #63
+; CHECK-GI-CVT-NEXT: fcvtzs x17, s4
+; CHECK-GI-CVT-NEXT: csel x15, xzr, x15, lt
+; CHECK-GI-CVT-NEXT: csel x16, x10, x16, lt
+; CHECK-GI-CVT-NEXT: fcmp s3, s2
+; CHECK-GI-CVT-NEXT: csinv x15, x15, xzr, le
+; CHECK-GI-CVT-NEXT: csel x18, x9, x16, gt
+; CHECK-GI-CVT-NEXT: fcmp s3, s3
+; CHECK-GI-CVT-NEXT: fcvt s3, h5
+; CHECK-GI-CVT-NEXT: mov h5, v0.h[5]
+; CHECK-GI-CVT-NEXT: csel x16, xzr, x15, vs
+; CHECK-GI-CVT-NEXT: csel x15, xzr, x18, vs
+; CHECK-GI-CVT-NEXT: fcmp s4, s1
+; CHECK-GI-CVT-NEXT: asr x18, x17, #63
+; CHECK-GI-CVT-NEXT: fcvtzs x0, s3
+; CHECK-GI-CVT-NEXT: csel x17, xzr, x17, lt
+; CHECK-GI-CVT-NEXT: csel x18, x10, x18, lt
+; CHECK-GI-CVT-NEXT: fcmp s4, s2
+; CHECK-GI-CVT-NEXT: csinv x17, x17, xzr, le
+; CHECK-GI-CVT-NEXT: csel x1, x9, x18, gt
+; CHECK-GI-CVT-NEXT: fcmp s4, s4
+; CHECK-GI-CVT-NEXT: fcvt s4, h5
+; CHECK-GI-CVT-NEXT: mov h5, v0.h[6]
; CHECK-GI-CVT-NEXT: mov h0, v0.h[7]
-; CHECK-GI-CVT-NEXT: fcvt s1, h1
-; CHECK-GI-CVT-NEXT: fcvt s2, h2
-; CHECK-GI-CVT-NEXT: fcvt s3, h3
-; CHECK-GI-CVT-NEXT: fcvtzs x9, s5
-; CHECK-GI-CVT-NEXT: fcvt s4, h4
-; CHECK-GI-CVT-NEXT: fcvt s5, h6
+; CHECK-GI-CVT-NEXT: csel x18, xzr, x17, vs
+; CHECK-GI-CVT-NEXT: csel x17, xzr, x1, vs
+; CHECK-GI-CVT-NEXT: fcmp s3, s1
+; CHECK-GI-CVT-NEXT: asr x1, x0, #63
+; CHECK-GI-CVT-NEXT: fcvtzs x2, s4
; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: fcvtzs x10, s1
-; CHECK-GI-CVT-NEXT: fcvt s1, h7
-; CHECK-GI-CVT-NEXT: fcvtzs x11, s2
-; CHECK-GI-CVT-NEXT: fcvtzs x12, s3
-; CHECK-GI-CVT-NEXT: mov v2.d[0], x9
-; CHECK-GI-CVT-NEXT: fcvtzs x9, s4
-; CHECK-GI-CVT-NEXT: mov v3.d[0], x10
-; CHECK-GI-CVT-NEXT: fcvtzs x10, s5
-; CHECK-GI-CVT-NEXT: mov v4.d[0], x11
-; CHECK-GI-CVT-NEXT: fcvtzs x11, s1
+; CHECK-GI-CVT-NEXT: csel x0, xzr, x0, lt
+; CHECK-GI-CVT-NEXT: csel x1, x10, x1, lt
+; CHECK-GI-CVT-NEXT: fcmp s3, s2
+; CHECK-GI-CVT-NEXT: csinv x0, x0, xzr, le
+; CHECK-GI-CVT-NEXT: csel x3, x9, x1, gt
+; CHECK-GI-CVT-NEXT: fcmp s3, s3
+; CHECK-GI-CVT-NEXT: fcvt s3, h5
+; CHECK-GI-CVT-NEXT: fcvtzs x6, s0
+; CHECK-GI-CVT-NEXT: csel x1, xzr, x0, vs
+; CHECK-GI-CVT-NEXT: csel x0, xzr, x3, vs
+; CHECK-GI-CVT-NEXT: fcmp s4, s1
+; CHECK-GI-CVT-NEXT: asr x3, x2, #63
+; CHECK-GI-CVT-NEXT: fcvtzs x4, s3
+; CHECK-GI-CVT-NEXT: asr x7, x6, #63
+; CHECK-GI-CVT-NEXT: csel x2, xzr, x2, lt
+; CHECK-GI-CVT-NEXT: csel x3, x10, x3, lt
+; CHECK-GI-CVT-NEXT: fcmp s4, s2
+; CHECK-GI-CVT-NEXT: csinv x2, x2, xzr, le
+; CHECK-GI-CVT-NEXT: csel x3, x9, x3, gt
+; CHECK-GI-CVT-NEXT: fcmp s4, s4
+; CHECK-GI-CVT-NEXT: asr x5, x4, #63
+; CHECK-GI-CVT-NEXT: mov v4.d[0], x18
+; CHECK-GI-CVT-NEXT: csel x2, xzr, x2, vs
+; CHECK-GI-CVT-NEXT: csel x3, xzr, x3, vs
+; CHECK-GI-CVT-NEXT: fcmp s3, s1
+; CHECK-GI-CVT-NEXT: mov v5.d[0], x2
+; CHECK-GI-CVT-NEXT: mov v4.d[1], x17
+; CHECK-GI-CVT-NEXT: csel x4, xzr, x4, lt
+; CHECK-GI-CVT-NEXT: csel x5, x10, x5, lt
+; CHECK-GI-CVT-NEXT: fcmp s3, s2
+; CHECK-GI-CVT-NEXT: mov v5.d[1], x3
+; CHECK-GI-CVT-NEXT: csinv x4, x4, xzr, le
+; CHECK-GI-CVT-NEXT: csel x5, x9, x5, gt
+; CHECK-GI-CVT-NEXT: fcmp s3, s3
+; CHECK-GI-CVT-NEXT: mov v3.d[0], x16
+; CHECK-GI-CVT-NEXT: csel x4, xzr, x4, vs
+; CHECK-GI-CVT-NEXT: csel x5, xzr, x5, vs
+; CHECK-GI-CVT-NEXT: fcmp s0, s1
; CHECK-GI-CVT-NEXT: mov v1.d[0], x12
-; CHECK-GI-CVT-NEXT: fcvtzs x12, s0
-; CHECK-GI-CVT-NEXT: mov v0.d[0], x9
-; CHECK-GI-CVT-NEXT: mov v2.d[1], xzr
-; CHECK-GI-CVT-NEXT: mov v5.d[0], x10
-; CHECK-GI-CVT-NEXT: mov v3.d[1], xzr
-; CHECK-GI-CVT-NEXT: mov v4.d[1], xzr
-; CHECK-GI-CVT-NEXT: mov v6.d[0], x11
-; CHECK-GI-CVT-NEXT: mov v7.d[0], x12
-; CHECK-GI-CVT-NEXT: mov v1.d[1], xzr
-; CHECK-GI-CVT-NEXT: mov v0.d[1], xzr
-; CHECK-GI-CVT-NEXT: mov v5.d[1], xzr
-; CHECK-GI-CVT-NEXT: stp q2, q3, [x8]
-; CHECK-GI-CVT-NEXT: mov v6.d[1], xzr
-; CHECK-GI-CVT-NEXT: mov v7.d[1], xzr
-; CHECK-GI-CVT-NEXT: stp q4, q1, [x8, #32]
+; CHECK-GI-CVT-NEXT: mov v6.d[0], x4
+; CHECK-GI-CVT-NEXT: mov v3.d[1], x15
+; CHECK-GI-CVT-NEXT: csel x10, x10, x7, lt
+; CHECK-GI-CVT-NEXT: csel x12, xzr, x6, lt
+; CHECK-GI-CVT-NEXT: fcmp s0, s2
+; CHECK-GI-CVT-NEXT: mov v2.d[0], x14
+; CHECK-GI-CVT-NEXT: mov v1.d[1], x11
+; CHECK-GI-CVT-NEXT: mov v6.d[1], x5
+; CHECK-GI-CVT-NEXT: csel x9, x9, x10, gt
+; CHECK-GI-CVT-NEXT: csinv x10, x12, xzr, le
+; CHECK-GI-CVT-NEXT: fcmp s0, s0
+; CHECK-GI-CVT-NEXT: mov v0.d[0], x1
+; CHECK-GI-CVT-NEXT: stp q3, q4, [x8, #32]
+; CHECK-GI-CVT-NEXT: mov v2.d[1], x13
+; CHECK-GI-CVT-NEXT: csel x10, xzr, x10, vs
+; CHECK-GI-CVT-NEXT: csel x9, xzr, x9, vs
+; CHECK-GI-CVT-NEXT: mov v7.d[0], x10
+; CHECK-GI-CVT-NEXT: mov v0.d[1], x0
+; CHECK-GI-CVT-NEXT: stp q1, q2, [x8]
+; CHECK-GI-CVT-NEXT: mov v7.d[1], x9
; CHECK-GI-CVT-NEXT: stp q0, q5, [x8, #64]
; CHECK-GI-CVT-NEXT: stp q6, q7, [x8, #96]
; CHECK-GI-CVT-NEXT: ret
;
; CHECK-GI-FP16-LABEL: test_signed_v8f16_v8i128:
; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
+; CHECK-GI-FP16-NEXT: adrp x9, .LCPI75_1
+; CHECK-GI-FP16-NEXT: fcvtzs x11, h0
+; CHECK-GI-FP16-NEXT: mov h3, v0.h[1]
+; CHECK-GI-FP16-NEXT: ldr h1, [x9, :lo12:.LCPI75_1]
+; CHECK-GI-FP16-NEXT: adrp x9, .LCPI75_0
+; CHECK-GI-FP16-NEXT: mov x10, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-FP16-NEXT: ldr h2, [x9, :lo12:.LCPI75_0]
+; CHECK-GI-FP16-NEXT: mov h4, v0.h[2]
+; CHECK-GI-FP16-NEXT: fcmp h0, h1
+; CHECK-GI-FP16-NEXT: asr x9, x11, #63
+; CHECK-GI-FP16-NEXT: fcvtzs x13, h3
+; CHECK-GI-FP16-NEXT: csel x11, xzr, x11, lt
+; CHECK-GI-FP16-NEXT: csel x12, x10, x9, lt
+; CHECK-GI-FP16-NEXT: fcmp h0, h2
+; CHECK-GI-FP16-NEXT: mov x9, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-GI-FP16-NEXT: fcvtzs x15, h4
+; CHECK-GI-FP16-NEXT: csinv x11, x11, xzr, le
+; CHECK-GI-FP16-NEXT: csel x14, x9, x12, gt
+; CHECK-GI-FP16-NEXT: fcmp h0, h0
+; CHECK-GI-FP16-NEXT: csel x12, xzr, x11, vs
+; CHECK-GI-FP16-NEXT: csel x11, xzr, x14, vs
+; CHECK-GI-FP16-NEXT: fcmp h3, h1
+; CHECK-GI-FP16-NEXT: asr x14, x13, #63
+; CHECK-GI-FP16-NEXT: csel x13, xzr, x13, lt
+; CHECK-GI-FP16-NEXT: csel x14, x10, x14, lt
+; CHECK-GI-FP16-NEXT: fcmp h3, h2
+; CHECK-GI-FP16-NEXT: csinv x13, x13, xzr, le
+; CHECK-GI-FP16-NEXT: csel x16, x9, x14, gt
+; CHECK-GI-FP16-NEXT: fcmp h3, h3
; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
+; CHECK-GI-FP16-NEXT: csel x14, xzr, x13, vs
+; CHECK-GI-FP16-NEXT: csel x13, xzr, x16, vs
+; CHECK-GI-FP16-NEXT: fcmp h4, h1
+; CHECK-GI-FP16-NEXT: asr x16, x15, #63
+; CHECK-GI-FP16-NEXT: fcvtzs x17, h3
+; CHECK-GI-FP16-NEXT: csel x15, xzr, x15, lt
+; CHECK-GI-FP16-NEXT: csel x16, x10, x16, lt
+; CHECK-GI-FP16-NEXT: fcmp h4, h2
+; CHECK-GI-FP16-NEXT: csinv x15, x15, xzr, le
+; CHECK-GI-FP16-NEXT: csel x18, x9, x16, gt
+; CHECK-GI-FP16-NEXT: fcmp h4, h4
; CHECK-GI-FP16-NEXT: mov h4, v0.h[4]
-; CHECK-GI-FP16-NEXT: fcvtzs x9, h0
-; CHECK-GI-FP16-NEXT: mov h5, v0.h[5]
-; CHECK-GI-FP16-NEXT: fcvtzs x10, h1
-; CHECK-GI-FP16-NEXT: mov h1, v0.h[6]
-; CHECK-GI-FP16-NEXT: fcvtzs x11, h2
+; CHECK-GI-FP16-NEXT: csel x16, xzr, x15, vs
+; CHECK-GI-FP16-NEXT: csel x15, xzr, x18, vs
+; CHECK-GI-FP16-NEXT: fcmp h3, h1
+; CHECK-GI-FP16-NEXT: asr x18, x17, #63
+; CHECK-GI-FP16-NEXT: fcvtzs x0, h4
+; CHECK-GI-FP16-NEXT: csel x17, xzr, x17, lt
+; CHECK-GI-FP16-NEXT: csel x18, x10, x18, lt
+; CHECK-GI-FP16-NEXT: fcmp h3, h2
+; CHECK-GI-FP16-NEXT: csinv x17, x17, xzr, le
+; CHECK-GI-FP16-NEXT: csel x1, x9, x18, gt
+; CHECK-GI-FP16-NEXT: fcmp h3, h3
+; CHECK-GI-FP16-NEXT: mov h3, v0.h[5]
+; CHECK-GI-FP16-NEXT: csel x18, xzr, x17, vs
+; CHECK-GI-FP16-NEXT: csel x17, xzr, x1, vs
+; CHECK-GI-FP16-NEXT: fcmp h4, h1
+; CHECK-GI-FP16-NEXT: asr x1, x0, #63
+; CHECK-GI-FP16-NEXT: fcvtzs x2, h3
+; CHECK-GI-FP16-NEXT: csel x0, xzr, x0, lt
+; CHECK-GI-FP16-NEXT: csel x1, x10, x1, lt
+; CHECK-GI-FP16-NEXT: fcmp h4, h2
+; CHECK-GI-FP16-NEXT: csinv x0, x0, xzr, le
+; CHECK-GI-FP16-NEXT: csel x1, x9, x1, gt
+; CHECK-GI-FP16-NEXT: fcmp h4, h4
+; CHECK-GI-FP16-NEXT: mov h4, v0.h[6]
; CHECK-GI-FP16-NEXT: mov h0, v0.h[7]
-; CHECK-GI-FP16-NEXT: fcvtzs x12, h3
-; CHECK-GI-FP16-NEXT: mov v2.d[0], x9
-; CHECK-GI-FP16-NEXT: fcvtzs x9, h4
-; CHECK-GI-FP16-NEXT: mov v3.d[0], x10
-; CHECK-GI-FP16-NEXT: fcvtzs x10, h5
-; CHECK-GI-FP16-NEXT: mov v4.d[0], x11
-; CHECK-GI-FP16-NEXT: fcvtzs x11, h1
+; CHECK-GI-FP16-NEXT: csel x3, xzr, x0, vs
+; CHECK-GI-FP16-NEXT: csel x0, xzr, x1, vs
+; CHECK-GI-FP16-NEXT: fcmp h3, h1
+; CHECK-GI-FP16-NEXT: asr x1, x2, #63
+; CHECK-GI-FP16-NEXT: fcvtzs x4, h4
+; CHECK-GI-FP16-NEXT: fcvtzs x6, h0
+; CHECK-GI-FP16-NEXT: csel x2, xzr, x2, lt
+; CHECK-GI-FP16-NEXT: csel x1, x10, x1, lt
+; CHECK-GI-FP16-NEXT: fcmp h3, h2
+; CHECK-GI-FP16-NEXT: csinv x2, x2, xzr, le
+; CHECK-GI-FP16-NEXT: csel x1, x9, x1, gt
+; CHECK-GI-FP16-NEXT: fcmp h3, h3
+; CHECK-GI-FP16-NEXT: asr x5, x4, #63
+; CHECK-GI-FP16-NEXT: asr x7, x6, #63
+; CHECK-GI-FP16-NEXT: mov v3.d[0], x16
+; CHECK-GI-FP16-NEXT: csel x2, xzr, x2, vs
+; CHECK-GI-FP16-NEXT: csel x1, xzr, x1, vs
+; CHECK-GI-FP16-NEXT: fcmp h4, h1
+; CHECK-GI-FP16-NEXT: mov v5.d[0], x2
+; CHECK-GI-FP16-NEXT: mov v3.d[1], x15
+; CHECK-GI-FP16-NEXT: csel x4, xzr, x4, lt
+; CHECK-GI-FP16-NEXT: csel x5, x10, x5, lt
+; CHECK-GI-FP16-NEXT: fcmp h4, h2
+; CHECK-GI-FP16-NEXT: mov v5.d[1], x1
+; CHECK-GI-FP16-NEXT: csinv x4, x4, xzr, le
+; CHECK-GI-FP16-NEXT: csel x5, x9, x5, gt
+; CHECK-GI-FP16-NEXT: fcmp h4, h4
+; CHECK-GI-FP16-NEXT: mov v4.d[0], x18
+; CHECK-GI-FP16-NEXT: csel x4, xzr, x4, vs
+; CHECK-GI-FP16-NEXT: csel x5, xzr, x5, vs
+; CHECK-GI-FP16-NEXT: fcmp h0, h1
; CHECK-GI-FP16-NEXT: mov v1.d[0], x12
-; CHECK-GI-FP16-NEXT: fcvtzs x12, h0
-; CHECK-GI-FP16-NEXT: mov v0.d[0], x9
-; CHECK-GI-FP16-NEXT: mov v2.d[1], xzr
-; CHECK-GI-FP16-NEXT: mov v5.d[0], x10
-; CHECK-GI-FP16-NEXT: mov v3.d[1], xzr
-; CHECK-GI-FP16-NEXT: mov v4.d[1], xzr
-; CHECK-GI-FP16-NEXT: mov v6.d[0], x11
-; CHECK-GI-FP16-NEXT: mov v7.d[0], x12
-; CHECK-GI-FP16-NEXT: mov v1.d[1], xzr
-; CHECK-GI-FP16-NEXT: mov v0.d[1], xzr
-; CHECK-GI-FP16-NEXT: mov v5.d[1], xzr
-; CHECK-GI-FP16-NEXT: stp q2, q3, [x8]
-; CHECK-GI-FP16-NEXT: mov v6.d[1], xzr
-; CHECK-GI-FP16-NEXT: mov v7.d[1], xzr
-; CHECK-GI-FP16-NEXT: stp q4, q1, [x8, #32]
+; CHECK-GI-FP16-NEXT: mov v6.d[0], x4
+; CHECK-GI-FP16-NEXT: mov v4.d[1], x17
+; CHECK-GI-FP16-NEXT: csel x10, x10, x7, lt
+; CHECK-GI-FP16-NEXT: csel x12, xzr, x6, lt
+; CHECK-GI-FP16-NEXT: fcmp h0, h2
+; CHECK-GI-FP16-NEXT: mov v2.d[0], x14
+; CHECK-GI-FP16-NEXT: mov v1.d[1], x11
+; CHECK-GI-FP16-NEXT: mov v6.d[1], x5
+; CHECK-GI-FP16-NEXT: csel x9, x9, x10, gt
+; CHECK-GI-FP16-NEXT: csinv x10, x12, xzr, le
+; CHECK-GI-FP16-NEXT: fcmp h0, h0
+; CHECK-GI-FP16-NEXT: mov v0.d[0], x3
+; CHECK-GI-FP16-NEXT: stp q3, q4, [x8, #32]
+; CHECK-GI-FP16-NEXT: mov v2.d[1], x13
+; CHECK-GI-FP16-NEXT: csel x10, xzr, x10, vs
+; CHECK-GI-FP16-NEXT: csel x9, xzr, x9, vs
+; CHECK-GI-FP16-NEXT: mov v7.d[0], x10
+; CHECK-GI-FP16-NEXT: mov v0.d[1], x0
+; CHECK-GI-FP16-NEXT: stp q1, q2, [x8]
+; CHECK-GI-FP16-NEXT: mov v7.d[1], x9
; CHECK-GI-FP16-NEXT: stp q0, q5, [x8, #64]
; CHECK-GI-FP16-NEXT: stp q6, q7, [x8, #96]
; CHECK-GI-FP16-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
index 7a5fe0f4222bc..40c9201b0f79a 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
@@ -705,14 +705,29 @@ define i100 @test_unsigned_i100_f16(half %f) nounwind {
; CHECK-GI-CVT-LABEL: test_unsigned_i100_f16:
; CHECK-GI-CVT: // %bb.0:
; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: mov x1, xzr
-; CHECK-GI-CVT-NEXT: fcvtzu x0, s0
+; CHECK-GI-CVT-NEXT: mov w9, #57344 // =0xe000
+; CHECK-GI-CVT-NEXT: movk w9, #18303, lsl #16
+; CHECK-GI-CVT-NEXT: fmov s1, w9
+; CHECK-GI-CVT-NEXT: mov x9, #68719476735 // =0xfffffffff
+; CHECK-GI-CVT-NEXT: fcvtzu x8, s0
+; CHECK-GI-CVT-NEXT: fcmp s0, #0.0
+; CHECK-GI-CVT-NEXT: csel x8, xzr, x8, lt
+; CHECK-GI-CVT-NEXT: fcmp s0, s1
+; CHECK-GI-CVT-NEXT: csinv x0, x8, xzr, le
+; CHECK-GI-CVT-NEXT: csel x1, x9, xzr, gt
; CHECK-GI-CVT-NEXT: ret
;
; CHECK-GI-FP16-LABEL: test_unsigned_i100_f16:
; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzu x0, h0
-; CHECK-GI-FP16-NEXT: mov x1, xzr
+; CHECK-GI-FP16-NEXT: fcvtzu x9, h0
+; CHECK-GI-FP16-NEXT: adrp x8, .LCPI28_0
+; CHECK-GI-FP16-NEXT: fcmp h0, #0.0
+; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI28_0]
+; CHECK-GI-FP16-NEXT: csel x8, xzr, x9, lt
+; CHECK-GI-FP16-NEXT: fcmp h0, h1
+; CHECK-GI-FP16-NEXT: mov x9, #68719476735 // =0xfffffffff
+; CHECK-GI-FP16-NEXT: csinv x0, x8, xzr, le
+; CHECK-GI-FP16-NEXT: csel x1, x9, xzr, gt
; CHECK-GI-FP16-NEXT: ret
%x = call i100 @llvm.fptoui.sat.i100.f16(half %f)
ret i100 %x
@@ -741,14 +756,27 @@ define i128 @test_unsigned_i128_f16(half %f) nounwind {
; CHECK-GI-CVT-LABEL: test_unsigned_i128_f16:
; CHECK-GI-CVT: // %bb.0:
; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: mov x1, xzr
-; CHECK-GI-CVT-NEXT: fcvtzu x0, s0
+; CHECK-GI-CVT-NEXT: mov w8, #57344 // =0xe000
+; CHECK-GI-CVT-NEXT: movk w8, #18303, lsl #16
+; CHECK-GI-CVT-NEXT: fmov s1, w8
+; CHECK-GI-CVT-NEXT: fcvtzu x9, s0
+; CHECK-GI-CVT-NEXT: fcmp s0, #0.0
+; CHECK-GI-CVT-NEXT: csel x8, xzr, x9, lt
+; CHECK-GI-CVT-NEXT: fcmp s0, s1
+; CHECK-GI-CVT-NEXT: csinv x0, x8, xzr, le
+; CHECK-GI-CVT-NEXT: csetm x1, gt
; CHECK-GI-CVT-NEXT: ret
;
; CHECK-GI-FP16-LABEL: test_unsigned_i128_f16:
; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzu x0, h0
-; CHECK-GI-FP16-NEXT: mov x1, xzr
+; CHECK-GI-FP16-NEXT: fcvtzu x9, h0
+; CHECK-GI-FP16-NEXT: adrp x8, .LCPI29_0
+; CHECK-GI-FP16-NEXT: fcmp h0, #0.0
+; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI29_0]
+; CHECK-GI-FP16-NEXT: csel x8, xzr, x9, lt
+; CHECK-GI-FP16-NEXT: fcmp h0, h1
+; CHECK-GI-FP16-NEXT: csinv x0, x8, xzr, le
+; CHECK-GI-FP16-NEXT: csetm x1, gt
; CHECK-GI-FP16-NEXT: ret
%x = call i128 @llvm.fptoui.sat.i128.f16(half %f)
ret i128 %x
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
index 083a84292029d..c2b106dcbd2ac 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
@@ -2587,37 +2587,76 @@ define <4 x i100> @test_unsigned_v4f16_v4i100(<4 x half> %f) {
; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i100:
; CHECK-GI-CVT: // %bb.0:
; CHECK-GI-CVT-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-CVT-NEXT: mov h1, v0.h[1]
-; CHECK-GI-CVT-NEXT: mov h2, v0.h[2]
-; CHECK-GI-CVT-NEXT: mov x1, xzr
-; CHECK-GI-CVT-NEXT: mov h3, v0.h[3]
-; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: mov x3, xzr
-; CHECK-GI-CVT-NEXT: mov x5, xzr
-; CHECK-GI-CVT-NEXT: mov x7, xzr
-; CHECK-GI-CVT-NEXT: fcvt s1, h1
+; CHECK-GI-CVT-NEXT: fcvt s1, h0
+; CHECK-GI-CVT-NEXT: mov h2, v0.h[1]
+; CHECK-GI-CVT-NEXT: mov w8, #57344 // =0xe000
+; CHECK-GI-CVT-NEXT: movk w8, #18303, lsl #16
+; CHECK-GI-CVT-NEXT: mov h4, v0.h[2]
+; CHECK-GI-CVT-NEXT: mov h0, v0.h[3]
+; CHECK-GI-CVT-NEXT: fmov s3, w8
+; CHECK-GI-CVT-NEXT: fcvtzu x9, s1
+; CHECK-GI-CVT-NEXT: fcmp s1, #0.0
; CHECK-GI-CVT-NEXT: fcvt s2, h2
-; CHECK-GI-CVT-NEXT: fcvt s3, h3
-; CHECK-GI-CVT-NEXT: fcvtzu x0, s0
-; CHECK-GI-CVT-NEXT: fcvtzu x2, s1
-; CHECK-GI-CVT-NEXT: fcvtzu x4, s2
-; CHECK-GI-CVT-NEXT: fcvtzu x6, s3
+; CHECK-GI-CVT-NEXT: fcvt s0, h0
+; CHECK-GI-CVT-NEXT: csel x8, xzr, x9, lt
+; CHECK-GI-CVT-NEXT: fcmp s1, s3
+; CHECK-GI-CVT-NEXT: mov x9, #68719476735 // =0xfffffffff
+; CHECK-GI-CVT-NEXT: fcvtzu x10, s2
+; CHECK-GI-CVT-NEXT: fcvt s1, h4
+; CHECK-GI-CVT-NEXT: csinv x0, x8, xzr, le
+; CHECK-GI-CVT-NEXT: csel x1, x9, xzr, gt
+; CHECK-GI-CVT-NEXT: fcmp s2, #0.0
+; CHECK-GI-CVT-NEXT: csel x8, xzr, x10, lt
+; CHECK-GI-CVT-NEXT: fcmp s2, s3
+; CHECK-GI-CVT-NEXT: fcvtzu x10, s1
+; CHECK-GI-CVT-NEXT: csinv x2, x8, xzr, le
+; CHECK-GI-CVT-NEXT: csel x3, x9, xzr, gt
+; CHECK-GI-CVT-NEXT: fcmp s1, #0.0
+; CHECK-GI-CVT-NEXT: csel x8, xzr, x10, lt
+; CHECK-GI-CVT-NEXT: fcmp s1, s3
+; CHECK-GI-CVT-NEXT: fcvtzu x10, s0
+; CHECK-GI-CVT-NEXT: csinv x4, x8, xzr, le
+; CHECK-GI-CVT-NEXT: csel x5, x9, xzr, gt
+; CHECK-GI-CVT-NEXT: fcmp s0, #0.0
+; CHECK-GI-CVT-NEXT: csel x8, xzr, x10, lt
+; CHECK-GI-CVT-NEXT: fcmp s0, s3
+; CHECK-GI-CVT-NEXT: csinv x6, x8, xzr, le
+; CHECK-GI-CVT-NEXT: csel x7, x9, xzr, gt
; CHECK-GI-CVT-NEXT: ret
;
; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i100:
; CHECK-GI-FP16: // %bb.0:
; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-FP16-NEXT: fcvtzu x9, h0
+; CHECK-GI-FP16-NEXT: adrp x8, .LCPI64_0
+; CHECK-GI-FP16-NEXT: fcmp h0, #0.0
; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-GI-FP16-NEXT: mov x1, xzr
-; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
-; CHECK-GI-FP16-NEXT: fcvtzu x0, h0
-; CHECK-GI-FP16-NEXT: mov x3, xzr
-; CHECK-GI-FP16-NEXT: mov x5, xzr
-; CHECK-GI-FP16-NEXT: mov x7, xzr
-; CHECK-GI-FP16-NEXT: fcvtzu x2, h1
-; CHECK-GI-FP16-NEXT: fcvtzu x4, h2
-; CHECK-GI-FP16-NEXT: fcvtzu x6, h3
+; CHECK-GI-FP16-NEXT: ldr h2, [x8, :lo12:.LCPI64_0]
+; CHECK-GI-FP16-NEXT: mov h3, v0.h[2]
+; CHECK-GI-FP16-NEXT: csel x8, xzr, x9, lt
+; CHECK-GI-FP16-NEXT: fcmp h0, h2
+; CHECK-GI-FP16-NEXT: mov x9, #68719476735 // =0xfffffffff
+; CHECK-GI-FP16-NEXT: fcvtzu x10, h1
+; CHECK-GI-FP16-NEXT: mov h0, v0.h[3]
+; CHECK-GI-FP16-NEXT: csinv x0, x8, xzr, le
+; CHECK-GI-FP16-NEXT: csel x1, x9, xzr, gt
+; CHECK-GI-FP16-NEXT: fcmp h1, #0.0
+; CHECK-GI-FP16-NEXT: csel x8, xzr, x10, lt
+; CHECK-GI-FP16-NEXT: fcmp h1, h2
+; CHECK-GI-FP16-NEXT: fcvtzu x10, h3
+; CHECK-GI-FP16-NEXT: csinv x2, x8, xzr, le
+; CHECK-GI-FP16-NEXT: csel x3, x9, xzr, gt
+; CHECK-GI-FP16-NEXT: fcmp h3, #0.0
+; CHECK-GI-FP16-NEXT: csel x8, xzr, x10, lt
+; CHECK-GI-FP16-NEXT: fcmp h3, h2
+; CHECK-GI-FP16-NEXT: fcvtzu x10, h0
+; CHECK-GI-FP16-NEXT: csinv x4, x8, xzr, le
+; CHECK-GI-FP16-NEXT: csel x5, x9, xzr, gt
+; CHECK-GI-FP16-NEXT: fcmp h0, #0.0
+; CHECK-GI-FP16-NEXT: csel x8, xzr, x10, lt
+; CHECK-GI-FP16-NEXT: fcmp h0, h2
+; CHECK-GI-FP16-NEXT: csinv x6, x8, xzr, le
+; CHECK-GI-FP16-NEXT: csel x7, x9, xzr, gt
; CHECK-GI-FP16-NEXT: ret
%x = call <4 x i100> @llvm.fptoui.sat.v4f16.v4i100(<4 x half> %f)
ret <4 x i100> %x
@@ -2705,37 +2744,74 @@ define <4 x i128> @test_unsigned_v4f16_v4i128(<4 x half> %f) {
; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i128:
; CHECK-GI-CVT: // %bb.0:
; CHECK-GI-CVT-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-CVT-NEXT: mov h1, v0.h[1]
-; CHECK-GI-CVT-NEXT: mov h2, v0.h[2]
-; CHECK-GI-CVT-NEXT: mov x1, xzr
-; CHECK-GI-CVT-NEXT: mov h3, v0.h[3]
-; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: mov x3, xzr
-; CHECK-GI-CVT-NEXT: mov x5, xzr
-; CHECK-GI-CVT-NEXT: mov x7, xzr
-; CHECK-GI-CVT-NEXT: fcvt s1, h1
+; CHECK-GI-CVT-NEXT: fcvt s1, h0
+; CHECK-GI-CVT-NEXT: mov h2, v0.h[1]
+; CHECK-GI-CVT-NEXT: mov w8, #57344 // =0xe000
+; CHECK-GI-CVT-NEXT: movk w8, #18303, lsl #16
+; CHECK-GI-CVT-NEXT: mov h4, v0.h[2]
+; CHECK-GI-CVT-NEXT: mov h0, v0.h[3]
+; CHECK-GI-CVT-NEXT: fmov s3, w8
+; CHECK-GI-CVT-NEXT: fcvtzu x9, s1
+; CHECK-GI-CVT-NEXT: fcmp s1, #0.0
; CHECK-GI-CVT-NEXT: fcvt s2, h2
-; CHECK-GI-CVT-NEXT: fcvt s3, h3
-; CHECK-GI-CVT-NEXT: fcvtzu x0, s0
-; CHECK-GI-CVT-NEXT: fcvtzu x2, s1
-; CHECK-GI-CVT-NEXT: fcvtzu x4, s2
-; CHECK-GI-CVT-NEXT: fcvtzu x6, s3
+; CHECK-GI-CVT-NEXT: fcvt s0, h0
+; CHECK-GI-CVT-NEXT: csel x8, xzr, x9, lt
+; CHECK-GI-CVT-NEXT: fcmp s1, s3
+; CHECK-GI-CVT-NEXT: fcvtzu x9, s2
+; CHECK-GI-CVT-NEXT: fcvt s1, h4
+; CHECK-GI-CVT-NEXT: csinv x0, x8, xzr, le
+; CHECK-GI-CVT-NEXT: csetm x1, gt
+; CHECK-GI-CVT-NEXT: fcmp s2, #0.0
+; CHECK-GI-CVT-NEXT: csel x8, xzr, x9, lt
+; CHECK-GI-CVT-NEXT: fcmp s2, s3
+; CHECK-GI-CVT-NEXT: fcvtzu x9, s1
+; CHECK-GI-CVT-NEXT: csinv x2, x8, xzr, le
+; CHECK-GI-CVT-NEXT: csetm x3, gt
+; CHECK-GI-CVT-NEXT: fcmp s1, #0.0
+; CHECK-GI-CVT-NEXT: csel x8, xzr, x9, lt
+; CHECK-GI-CVT-NEXT: fcmp s1, s3
+; CHECK-GI-CVT-NEXT: fcvtzu x9, s0
+; CHECK-GI-CVT-NEXT: csinv x4, x8, xzr, le
+; CHECK-GI-CVT-NEXT: csetm x5, gt
+; CHECK-GI-CVT-NEXT: fcmp s0, #0.0
+; CHECK-GI-CVT-NEXT: csel x8, xzr, x9, lt
+; CHECK-GI-CVT-NEXT: fcmp s0, s3
+; CHECK-GI-CVT-NEXT: csinv x6, x8, xzr, le
+; CHECK-GI-CVT-NEXT: csetm x7, gt
; CHECK-GI-CVT-NEXT: ret
;
; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i128:
; CHECK-GI-FP16: // %bb.0:
; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-FP16-NEXT: fcvtzu x9, h0
+; CHECK-GI-FP16-NEXT: adrp x8, .LCPI65_0
+; CHECK-GI-FP16-NEXT: fcmp h0, #0.0
; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-GI-FP16-NEXT: mov x1, xzr
-; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
-; CHECK-GI-FP16-NEXT: fcvtzu x0, h0
-; CHECK-GI-FP16-NEXT: mov x3, xzr
-; CHECK-GI-FP16-NEXT: mov x5, xzr
-; CHECK-GI-FP16-NEXT: mov x7, xzr
-; CHECK-GI-FP16-NEXT: fcvtzu x2, h1
-; CHECK-GI-FP16-NEXT: fcvtzu x4, h2
-; CHECK-GI-FP16-NEXT: fcvtzu x6, h3
+; CHECK-GI-FP16-NEXT: ldr h2, [x8, :lo12:.LCPI65_0]
+; CHECK-GI-FP16-NEXT: mov h3, v0.h[2]
+; CHECK-GI-FP16-NEXT: csel x8, xzr, x9, lt
+; CHECK-GI-FP16-NEXT: fcmp h0, h2
+; CHECK-GI-FP16-NEXT: mov h0, v0.h[3]
+; CHECK-GI-FP16-NEXT: fcvtzu x9, h1
+; CHECK-GI-FP16-NEXT: csinv x0, x8, xzr, le
+; CHECK-GI-FP16-NEXT: csetm x1, gt
+; CHECK-GI-FP16-NEXT: fcmp h1, #0.0
+; CHECK-GI-FP16-NEXT: csel x8, xzr, x9, lt
+; CHECK-GI-FP16-NEXT: fcmp h1, h2
+; CHECK-GI-FP16-NEXT: fcvtzu x9, h3
+; CHECK-GI-FP16-NEXT: csinv x2, x8, xzr, le
+; CHECK-GI-FP16-NEXT: csetm x3, gt
+; CHECK-GI-FP16-NEXT: fcmp h3, #0.0
+; CHECK-GI-FP16-NEXT: csel x8, xzr, x9, lt
+; CHECK-GI-FP16-NEXT: fcmp h3, h2
+; CHECK-GI-FP16-NEXT: fcvtzu x9, h0
+; CHECK-GI-FP16-NEXT: csinv x4, x8, xzr, le
+; CHECK-GI-FP16-NEXT: csetm x5, gt
+; CHECK-GI-FP16-NEXT: fcmp h0, #0.0
+; CHECK-GI-FP16-NEXT: csel x8, xzr, x9, lt
+; CHECK-GI-FP16-NEXT: fcmp h0, h2
+; CHECK-GI-FP16-NEXT: csinv x6, x8, xzr, le
+; CHECK-GI-FP16-NEXT: csetm x7, gt
; CHECK-GI-FP16-NEXT: ret
%x = call <4 x i128> @llvm.fptoui.sat.v4f16.v4i128(<4 x half> %f)
ret <4 x i128> %x
@@ -3409,87 +3485,172 @@ define <8 x i128> @test_unsigned_v8f16_v8i128(<8 x half> %f) {
;
; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i128:
; CHECK-GI-CVT: // %bb.0:
+; CHECK-GI-CVT-NEXT: fcvt s2, h0
; CHECK-GI-CVT-NEXT: mov h1, v0.h[1]
-; CHECK-GI-CVT-NEXT: mov h2, v0.h[2]
-; CHECK-GI-CVT-NEXT: mov h3, v0.h[3]
+; CHECK-GI-CVT-NEXT: mov w9, #57344 // =0xe000
+; CHECK-GI-CVT-NEXT: movk w9, #18303, lsl #16
+; CHECK-GI-CVT-NEXT: mov h4, v0.h[2]
+; CHECK-GI-CVT-NEXT: fcvtzu x10, s2
+; CHECK-GI-CVT-NEXT: fcmp s2, #0.0
+; CHECK-GI-CVT-NEXT: fcvt s3, h1
+; CHECK-GI-CVT-NEXT: fmov s1, w9
+; CHECK-GI-CVT-NEXT: csel x9, xzr, x10, lt
+; CHECK-GI-CVT-NEXT: fcmp s2, s1
+; CHECK-GI-CVT-NEXT: fcvtzu x11, s3
+; CHECK-GI-CVT-NEXT: fcvt s2, h4
+; CHECK-GI-CVT-NEXT: mov h4, v0.h[3]
+; CHECK-GI-CVT-NEXT: csinv x10, x9, xzr, le
+; CHECK-GI-CVT-NEXT: csetm x9, gt
+; CHECK-GI-CVT-NEXT: fcmp s3, #0.0
+; CHECK-GI-CVT-NEXT: fcvtzu x13, s2
+; CHECK-GI-CVT-NEXT: csel x11, xzr, x11, lt
+; CHECK-GI-CVT-NEXT: fcmp s3, s1
+; CHECK-GI-CVT-NEXT: fcvt s3, h4
; CHECK-GI-CVT-NEXT: mov h4, v0.h[4]
-; CHECK-GI-CVT-NEXT: fcvt s5, h0
-; CHECK-GI-CVT-NEXT: mov h6, v0.h[5]
-; CHECK-GI-CVT-NEXT: mov h7, v0.h[6]
+; CHECK-GI-CVT-NEXT: csinv x12, x11, xzr, le
+; CHECK-GI-CVT-NEXT: csetm x11, gt
+; CHECK-GI-CVT-NEXT: fcmp s2, #0.0
+; CHECK-GI-CVT-NEXT: fcvtzu x15, s3
+; CHECK-GI-CVT-NEXT: csel x13, xzr, x13, lt
+; CHECK-GI-CVT-NEXT: fcmp s2, s1
+; CHECK-GI-CVT-NEXT: fcvt s2, h4
+; CHECK-GI-CVT-NEXT: mov h4, v0.h[5]
+; CHECK-GI-CVT-NEXT: csinv x14, x13, xzr, le
+; CHECK-GI-CVT-NEXT: csetm x13, gt
+; CHECK-GI-CVT-NEXT: fcmp s3, #0.0
+; CHECK-GI-CVT-NEXT: fcvtzu x16, s2
+; CHECK-GI-CVT-NEXT: csel x15, xzr, x15, lt
+; CHECK-GI-CVT-NEXT: fcmp s3, s1
+; CHECK-GI-CVT-NEXT: fcvt s3, h4
+; CHECK-GI-CVT-NEXT: mov h4, v0.h[6]
; CHECK-GI-CVT-NEXT: mov h0, v0.h[7]
-; CHECK-GI-CVT-NEXT: fcvt s1, h1
-; CHECK-GI-CVT-NEXT: fcvt s2, h2
-; CHECK-GI-CVT-NEXT: fcvt s3, h3
-; CHECK-GI-CVT-NEXT: fcvtzu x9, s5
-; CHECK-GI-CVT-NEXT: fcvt s4, h4
-; CHECK-GI-CVT-NEXT: fcvt s5, h6
+; CHECK-GI-CVT-NEXT: csinv x15, x15, xzr, le
+; CHECK-GI-CVT-NEXT: csetm x17, gt
+; CHECK-GI-CVT-NEXT: fcmp s2, #0.0
+; CHECK-GI-CVT-NEXT: fcvtzu x18, s3
+; CHECK-GI-CVT-NEXT: mov v5.d[0], x15
; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: fcvtzu x10, s1
-; CHECK-GI-CVT-NEXT: fcvt s1, h7
-; CHECK-GI-CVT-NEXT: fcvtzu x11, s2
-; CHECK-GI-CVT-NEXT: fcvtzu x12, s3
-; CHECK-GI-CVT-NEXT: mov v2.d[0], x9
-; CHECK-GI-CVT-NEXT: fcvtzu x9, s4
-; CHECK-GI-CVT-NEXT: mov v3.d[0], x10
-; CHECK-GI-CVT-NEXT: fcvtzu x10, s5
-; CHECK-GI-CVT-NEXT: mov v4.d[0], x11
-; CHECK-GI-CVT-NEXT: fcvtzu x11, s1
-; CHECK-GI-CVT-NEXT: mov v1.d[0], x12
-; CHECK-GI-CVT-NEXT: fcvtzu x12, s0
-; CHECK-GI-CVT-NEXT: mov v0.d[0], x9
-; CHECK-GI-CVT-NEXT: mov v2.d[1], xzr
-; CHECK-GI-CVT-NEXT: mov v5.d[0], x10
-; CHECK-GI-CVT-NEXT: mov v3.d[1], xzr
-; CHECK-GI-CVT-NEXT: mov v4.d[1], xzr
-; CHECK-GI-CVT-NEXT: mov v6.d[0], x11
-; CHECK-GI-CVT-NEXT: mov v7.d[0], x12
-; CHECK-GI-CVT-NEXT: mov v1.d[1], xzr
-; CHECK-GI-CVT-NEXT: mov v0.d[1], xzr
-; CHECK-GI-CVT-NEXT: mov v5.d[1], xzr
+; CHECK-GI-CVT-NEXT: csel x16, xzr, x16, lt
+; CHECK-GI-CVT-NEXT: fcmp s2, s1
+; CHECK-GI-CVT-NEXT: fcvt s2, h4
+; CHECK-GI-CVT-NEXT: mov v4.d[0], x14
+; CHECK-GI-CVT-NEXT: mov v5.d[1], x17
+; CHECK-GI-CVT-NEXT: csinv x16, x16, xzr, le
+; CHECK-GI-CVT-NEXT: csetm x0, gt
+; CHECK-GI-CVT-NEXT: fcmp s3, #0.0
+; CHECK-GI-CVT-NEXT: fcvtzu x1, s2
+; CHECK-GI-CVT-NEXT: mov v4.d[1], x13
+; CHECK-GI-CVT-NEXT: csel x18, xzr, x18, lt
+; CHECK-GI-CVT-NEXT: fcmp s3, s1
+; CHECK-GI-CVT-NEXT: mov v3.d[0], x12
+; CHECK-GI-CVT-NEXT: csinv x18, x18, xzr, le
+; CHECK-GI-CVT-NEXT: csetm x2, gt
+; CHECK-GI-CVT-NEXT: fcmp s2, #0.0
+; CHECK-GI-CVT-NEXT: mov v3.d[1], x11
+; CHECK-GI-CVT-NEXT: stp q4, q5, [x8, #32]
+; CHECK-GI-CVT-NEXT: csel x1, xzr, x1, lt
+; CHECK-GI-CVT-NEXT: fcmp s2, s1
+; CHECK-GI-CVT-NEXT: mov v2.d[0], x10
+; CHECK-GI-CVT-NEXT: fcvtzu x10, s0
+; CHECK-GI-CVT-NEXT: csinv x1, x1, xzr, le
+; CHECK-GI-CVT-NEXT: csetm x3, gt
+; CHECK-GI-CVT-NEXT: fcmp s0, #0.0
+; CHECK-GI-CVT-NEXT: mov v2.d[1], x9
+; CHECK-GI-CVT-NEXT: mov v6.d[0], x1
+; CHECK-GI-CVT-NEXT: csel x10, xzr, x10, lt
+; CHECK-GI-CVT-NEXT: fcmp s0, s1
+; CHECK-GI-CVT-NEXT: mov v0.d[0], x16
+; CHECK-GI-CVT-NEXT: mov v1.d[0], x18
+; CHECK-GI-CVT-NEXT: mov v6.d[1], x3
; CHECK-GI-CVT-NEXT: stp q2, q3, [x8]
-; CHECK-GI-CVT-NEXT: mov v6.d[1], xzr
-; CHECK-GI-CVT-NEXT: mov v7.d[1], xzr
-; CHECK-GI-CVT-NEXT: stp q4, q1, [x8, #32]
-; CHECK-GI-CVT-NEXT: stp q0, q5, [x8, #64]
+; CHECK-GI-CVT-NEXT: csinv x9, x10, xzr, le
+; CHECK-GI-CVT-NEXT: mov v7.d[0], x9
+; CHECK-GI-CVT-NEXT: csetm x9, gt
+; CHECK-GI-CVT-NEXT: mov v0.d[1], x0
+; CHECK-GI-CVT-NEXT: mov v1.d[1], x2
+; CHECK-GI-CVT-NEXT: mov v7.d[1], x9
+; CHECK-GI-CVT-NEXT: stp q0, q1, [x8, #64]
; CHECK-GI-CVT-NEXT: stp q6, q7, [x8, #96]
; CHECK-GI-CVT-NEXT: ret
;
; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i128:
; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]
-; CHECK-GI-FP16-NEXT: mov h4, v0.h[4]
-; CHECK-GI-FP16-NEXT: fcvtzu x9, h0
-; CHECK-GI-FP16-NEXT: mov h5, v0.h[5]
-; CHECK-GI-FP16-NEXT: fcvtzu x10, h1
-; CHECK-GI-FP16-NEXT: mov h1, v0.h[6]
-; CHECK-GI-FP16-NEXT: fcvtzu x11, h2
+; CHECK-GI-FP16-NEXT: fcvtzu x10, h0
+; CHECK-GI-FP16-NEXT: adrp x9, .LCPI75_0
+; CHECK-GI-FP16-NEXT: fcmp h0, #0.0
+; CHECK-GI-FP16-NEXT: mov h2, v0.h[1]
+; CHECK-GI-FP16-NEXT: ldr h1, [x9, :lo12:.LCPI75_0]
+; CHECK-GI-FP16-NEXT: mov h3, v0.h[2]
+; CHECK-GI-FP16-NEXT: csel x9, xzr, x10, lt
+; CHECK-GI-FP16-NEXT: fcmp h0, h1
+; CHECK-GI-FP16-NEXT: fcvtzu x10, h2
+; CHECK-GI-FP16-NEXT: fcvtzu x13, h3
+; CHECK-GI-FP16-NEXT: csinv x11, x9, xzr, le
+; CHECK-GI-FP16-NEXT: csetm x9, gt
+; CHECK-GI-FP16-NEXT: fcmp h2, #0.0
+; CHECK-GI-FP16-NEXT: csel x10, xzr, x10, lt
+; CHECK-GI-FP16-NEXT: fcmp h2, h1
+; CHECK-GI-FP16-NEXT: mov h2, v0.h[3]
+; CHECK-GI-FP16-NEXT: csinv x12, x10, xzr, le
+; CHECK-GI-FP16-NEXT: csetm x10, gt
+; CHECK-GI-FP16-NEXT: fcmp h3, #0.0
+; CHECK-GI-FP16-NEXT: fcvtzu x14, h2
+; CHECK-GI-FP16-NEXT: csel x13, xzr, x13, lt
+; CHECK-GI-FP16-NEXT: fcmp h3, h1
+; CHECK-GI-FP16-NEXT: mov h3, v0.h[4]
+; CHECK-GI-FP16-NEXT: csinv x13, x13, xzr, le
+; CHECK-GI-FP16-NEXT: csetm x15, gt
+; CHECK-GI-FP16-NEXT: fcmp h2, #0.0
+; CHECK-GI-FP16-NEXT: fcvtzu x16, h3
+; CHECK-GI-FP16-NEXT: mov v4.d[0], x13
+; CHECK-GI-FP16-NEXT: csel x14, xzr, x14, lt
+; CHECK-GI-FP16-NEXT: fcmp h2, h1
+; CHECK-GI-FP16-NEXT: mov h2, v0.h[5]
+; CHECK-GI-FP16-NEXT: mov v4.d[1], x15
+; CHECK-GI-FP16-NEXT: csinv x14, x14, xzr, le
+; CHECK-GI-FP16-NEXT: csetm x17, gt
+; CHECK-GI-FP16-NEXT: fcmp h3, #0.0
+; CHECK-GI-FP16-NEXT: fcvtzu x18, h2
+; CHECK-GI-FP16-NEXT: mov v5.d[0], x14
+; CHECK-GI-FP16-NEXT: csel x16, xzr, x16, lt
+; CHECK-GI-FP16-NEXT: fcmp h3, h1
+; CHECK-GI-FP16-NEXT: mov h3, v0.h[6]
; CHECK-GI-FP16-NEXT: mov h0, v0.h[7]
-; CHECK-GI-FP16-NEXT: fcvtzu x12, h3
-; CHECK-GI-FP16-NEXT: mov v2.d[0], x9
-; CHECK-GI-FP16-NEXT: fcvtzu x9, h4
-; CHECK-GI-FP16-NEXT: mov v3.d[0], x10
-; CHECK-GI-FP16-NEXT: fcvtzu x10, h5
-; CHECK-GI-FP16-NEXT: mov v4.d[0], x11
-; CHECK-GI-FP16-NEXT: fcvtzu x11, h1
-; CHECK-GI-FP16-NEXT: mov v1.d[0], x12
-; CHECK-GI-FP16-NEXT: fcvtzu x12, h0
-; CHECK-GI-FP16-NEXT: mov v0.d[0], x9
-; CHECK-GI-FP16-NEXT: mov v2.d[1], xzr
-; CHECK-GI-FP16-NEXT: mov v5.d[0], x10
-; CHECK-GI-FP16-NEXT: mov v3.d[1], xzr
-; CHECK-GI-FP16-NEXT: mov v4.d[1], xzr
-; CHECK-GI-FP16-NEXT: mov v6.d[0], x11
-; CHECK-GI-FP16-NEXT: mov v7.d[0], x12
-; CHECK-GI-FP16-NEXT: mov v1.d[1], xzr
-; CHECK-GI-FP16-NEXT: mov v0.d[1], xzr
-; CHECK-GI-FP16-NEXT: mov v5.d[1], xzr
+; CHECK-GI-FP16-NEXT: mov v5.d[1], x17
+; CHECK-GI-FP16-NEXT: csinv x16, x16, xzr, le
+; CHECK-GI-FP16-NEXT: csetm x0, gt
+; CHECK-GI-FP16-NEXT: fcmp h2, #0.0
+; CHECK-GI-FP16-NEXT: fcvtzu x1, h3
+; CHECK-GI-FP16-NEXT: csel x18, xzr, x18, lt
+; CHECK-GI-FP16-NEXT: fcmp h2, h1
+; CHECK-GI-FP16-NEXT: mov v2.d[0], x11
+; CHECK-GI-FP16-NEXT: fcvtzu x11, h0
+; CHECK-GI-FP16-NEXT: stp q4, q5, [x8, #32]
+; CHECK-GI-FP16-NEXT: csinv x18, x18, xzr, le
+; CHECK-GI-FP16-NEXT: csetm x2, gt
+; CHECK-GI-FP16-NEXT: fcmp h3, #0.0
+; CHECK-GI-FP16-NEXT: mov v2.d[1], x9
+; CHECK-GI-FP16-NEXT: csel x1, xzr, x1, lt
+; CHECK-GI-FP16-NEXT: fcmp h3, h1
+; CHECK-GI-FP16-NEXT: mov v3.d[0], x12
+; CHECK-GI-FP16-NEXT: csinv x1, x1, xzr, le
+; CHECK-GI-FP16-NEXT: csetm x3, gt
+; CHECK-GI-FP16-NEXT: fcmp h0, #0.0
+; CHECK-GI-FP16-NEXT: mov v6.d[0], x1
+; CHECK-GI-FP16-NEXT: mov v3.d[1], x10
+; CHECK-GI-FP16-NEXT: csel x11, xzr, x11, lt
+; CHECK-GI-FP16-NEXT: fcmp h0, h1
+; CHECK-GI-FP16-NEXT: mov v0.d[0], x16
+; CHECK-GI-FP16-NEXT: mov v1.d[0], x18
+; CHECK-GI-FP16-NEXT: mov v6.d[1], x3
; CHECK-GI-FP16-NEXT: stp q2, q3, [x8]
-; CHECK-GI-FP16-NEXT: mov v6.d[1], xzr
-; CHECK-GI-FP16-NEXT: mov v7.d[1], xzr
-; CHECK-GI-FP16-NEXT: stp q4, q1, [x8, #32]
-; CHECK-GI-FP16-NEXT: stp q0, q5, [x8, #64]
+; CHECK-GI-FP16-NEXT: csinv x9, x11, xzr, le
+; CHECK-GI-FP16-NEXT: mov v7.d[0], x9
+; CHECK-GI-FP16-NEXT: csetm x9, gt
+; CHECK-GI-FP16-NEXT: mov v0.d[1], x0
+; CHECK-GI-FP16-NEXT: mov v1.d[1], x2
+; CHECK-GI-FP16-NEXT: mov v7.d[1], x9
+; CHECK-GI-FP16-NEXT: stp q0, q1, [x8, #64]
; CHECK-GI-FP16-NEXT: stp q6, q7, [x8, #96]
; CHECK-GI-FP16-NEXT: ret
%x = call <8 x i128> @llvm.fptoui.sat.v8f16.v8i128(<8 x half> %f)
>From ba82c32c440157f5e9b02c06f9baee497e6c97bd Mon Sep 17 00:00:00 2001
From: Nathaniel McCallum <nathaniel at mccallum.life>
Date: Tue, 11 Aug 2026 08:57:58 -0400
Subject: [PATCH 6/7] [GlobalISel] Add narrowScalar test for saturating
fp-to-int (NFC)
The result recorded here is wrong: narrowScalar accepts a request to narrow
G_FPTOSI_SAT and G_FPTOUI_SAT, which saturates to the bounds of the narrower
type rather than those of the result type.
---
.../GlobalISel/LegalizerHelperTest.cpp | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
index 3785bf5126eb5..632aa9b493281 100644
--- a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
@@ -247,6 +247,36 @@ TEST_F(AArch64GISelMITest, LowerBitCountingCTTZ1) {
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
}
+// FIXME: narrowing a saturating conversion is not valid -- it saturates to the
+// bounds of the narrower type, and the result recorded here is additionally
+// zero-extended rather than sign-extended.
+TEST_F(AArch64GISelMITest, NarrowScalarFPTOI_SAT) {
+ setUp();
+ if (!TM)
+ GTEST_SKIP();
+
+ // Declare your legalization info
+ DefineLegalizerInfo(A, {
+ getActionDefinitionsBuilder({G_FPTOSI_SAT, G_FPTOUI_SAT})
+ .legalFor({{s32, s32}});
+ });
+
+ LLT S16{LLT::scalar(16)};
+ LLT S128{LLT::scalar(128)};
+ auto Half = B.buildFPTrunc(S16, Copies[0]);
+ auto Signed = B.buildInstr(TargetOpcode::G_FPTOSI_SAT, {S128}, {Half});
+ auto Unsigned = B.buildInstr(TargetOpcode::G_FPTOUI_SAT, {S128}, {Half});
+
+ AInfo Info(MF->getSubtarget());
+ DummyGISelObserver Observer;
+ LegalizerHelper Helper(*MF, Info, Observer, B);
+
+ EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
+ Helper.narrowScalar(*Signed, 0, LLT::scalar(64)));
+ EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
+ Helper.narrowScalar(*Unsigned, 0, LLT::scalar(64)));
+}
+
// CTLZ scalar narrowing
TEST_F(AArch64GISelMITest, NarrowScalarCTLZ) {
setUp();
>From 210c9476d96f2fcb235dc1afcc6143f266f5ef4e Mon Sep 17 00:00:00 2001
From: Nathaniel McCallum <nathaniel at mccallum.life>
Date: Tue, 11 Aug 2026 08:59:41 -0400
Subject: [PATCH 7/7] [GlobalISel] Don't narrow saturating fp-to-int
conversions
narrowScalar dispatched G_FPTOSI_SAT and G_FPTOUI_SAT to narrowScalarFPTOI
alongside their non-saturating counterparts. That is sound only for the latter:
out-of-range results are poison there, so a conversion whose source range fits
in the narrower type can be performed at that width and extended. A saturating
conversion clamps to the bounds of its result type, so narrowing it saturates
to the wrong bounds.
The helper also derived signedness with
bool IsSigned = MI.getOpcode() == TargetOpcode::G_FPTOSI;
which is false for G_FPTOSI_SAT, so a signed saturating result was zero-extended
rather than sign-extended, turning every negative result into a large positive
one.
Reject these opcodes explicitly, so a target asking to narrow one gets a
legalization failure -- a hard error, or a fallback to SelectionDAG depending on
-global-isel-abort -- rather than silently wrong bounds. Nothing is lost: the
lowering expands the saturation at the result width and narrows the
non-saturating conversion inside it.
The two in-tree targets that requested this narrowing are fixed in the preceding
commits.
---
llvm/docs/GlobalISel/GenericOpcode.rst | 7 ++++++-
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 11 +++++++++--
.../CodeGen/GlobalISel/LegalizerHelperTest.cpp | 9 ++++-----
3 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index d2552b6c3a3f3..caf09b830acfe 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -575,7 +575,12 @@ Convert between integer and floating point.
G_FPTOSI_SAT, G_FPTOUI_SAT
^^^^^^^^^^^^^^^^^^^^^^^^^^
-Saturating convert between integer and floating point.
+Saturating convert between integer and floating point. Values outside the range
+of the result type saturate to its bounds, and NaN converts to zero.
+
+The saturation bounds are those of the result type, so these cannot be narrowed:
+converting at a narrower width saturates to the wrong bounds even when every
+finite value of the source fits in it.
G_FABS
^^^^^^
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index a6c5a267c87db..0bf7e52513ddf 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -2122,10 +2122,14 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
Observer.changedInstr(MI);
return Legalized;
}
- case TargetOpcode::G_FPTOUI:
- case TargetOpcode::G_FPTOSI:
case TargetOpcode::G_FPTOUI_SAT:
case TargetOpcode::G_FPTOSI_SAT:
+ // A saturating conversion clamps to the bounds of its result type, so it
+ // cannot be performed at a narrower width however small the range of the
+ // source is. lower() expands it and narrows the conversion inside.
+ return UnableToLegalize;
+ case TargetOpcode::G_FPTOUI:
+ case TargetOpcode::G_FPTOSI:
return narrowScalarFPTOI(MI, TypeIdx, NarrowTy);
case TargetOpcode::G_FPEXT:
if (TypeIdx != 0)
@@ -7472,6 +7476,9 @@ LegalizerHelper::narrowScalarFPTOI(MachineInstr &MI, unsigned TypeIdx,
// If all finite floats fit into the narrowed integer type, we can just swap
// out the result type. This is practically only useful for conversions from
// half to at least 16-bits, so just handle the one case.
+ //
+ // This is only valid because out-of-range results are poison here; see the
+ // saturating opcodes in narrowScalar().
if (SrcTy.getScalarType() != LLT::scalar(16) ||
NarrowTy.getScalarSizeInBits() < (IsSigned ? 17u : 16u))
return UnableToLegalize;
diff --git a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
index 632aa9b493281..7d56581aa0a02 100644
--- a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
@@ -247,9 +247,8 @@ TEST_F(AArch64GISelMITest, LowerBitCountingCTTZ1) {
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
}
-// FIXME: narrowing a saturating conversion is not valid -- it saturates to the
-// bounds of the narrower type, and the result recorded here is additionally
-// zero-extended rather than sign-extended.
+// Saturating fp-to-int conversions clamp to the bounds of their result type, so
+// they cannot be narrowed.
TEST_F(AArch64GISelMITest, NarrowScalarFPTOI_SAT) {
setUp();
if (!TM)
@@ -271,9 +270,9 @@ TEST_F(AArch64GISelMITest, NarrowScalarFPTOI_SAT) {
DummyGISelObserver Observer;
LegalizerHelper Helper(*MF, Info, Observer, B);
- EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
+ EXPECT_EQ(LegalizerHelper::LegalizeResult::UnableToLegalize,
Helper.narrowScalar(*Signed, 0, LLT::scalar(64)));
- EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
+ EXPECT_EQ(LegalizerHelper::LegalizeResult::UnableToLegalize,
Helper.narrowScalar(*Unsigned, 0, LLT::scalar(64)));
}
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