[llvm] [MISched] Reformat print of region header (PR #215540)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 11 05:34:02 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-powerpc
Author: Tomer Shafir (tomershafir)
<details>
<summary>Changes</summary>
---
Patch is 55.01 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/215540.diff
47 Files Affected:
- (modified) llvm/lib/CodeGen/MachineScheduler.cpp (+1-1)
- (modified) llvm/test/CodeGen/AArch64/aarch64-stp-cluster.ll (+10-10)
- (modified) llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll (+16-16)
- (modified) llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll (+4-4)
- (modified) llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/macro-fusion.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/scheduledag-constreg.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir (+2-2)
- (modified) llvm/test/CodeGen/ARM/cortex-a57-misched-alu.ll (+1-1)
- (modified) llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll (+1-1)
- (modified) llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir (+1-1)
- (modified) llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/cortex-a57-misched-stm.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/cortex-a57-misched-vfma.ll (+6-6)
- (modified) llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/cortex-a57-misched-vstm.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/cortexr52-misched-basic.ll (+1-1)
- (modified) llvm/test/CodeGen/ARM/misched-fp-basic.ll (+1-1)
- (modified) llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir (+1-1)
- (modified) llvm/test/CodeGen/ARM/misched-int-basic.mir (+1-1)
- (modified) llvm/test/CodeGen/ARM/postrasched.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/proc-resource-sched.ll (+1-1)
- (modified) llvm/test/CodeGen/ARM/single-issue-r52.mir (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/fence.ll (+4-4)
- (modified) llvm/test/CodeGen/PowerPC/fusion-load-store.ll (+19-19)
- (modified) llvm/test/CodeGen/PowerPC/macro-fusion.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/pr47155-47156.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/read-set-flm.ll (+6-6)
- (modified) llvm/test/CodeGen/PowerPC/scheduling-mem-dependency.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/disjoint.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/misched-load-clustering.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/misched-store-clustering.ll (+4-4)
- (modified) llvm/test/CodeGen/SystemZ/misched-prera-cmp-elim.mir (+2-2)
- (modified) llvm/test/CodeGen/SystemZ/misched-prera-latencies.mir (+7-7)
- (modified) llvm/test/CodeGen/SystemZ/misched-prera-loads.mir (+8-8)
- (modified) llvm/test/CodeGen/SystemZ/misched-prera-pdiffs.mir (+1-1)
- (modified) llvm/test/CodeGen/X86/fake-use-scheduler.mir (+2-2)
- (modified) llvm/test/CodeGen/X86/merge-store-dependency.ll (+1-1)
``````````diff
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 90800049f5769..9cebfa35af752 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -861,7 +861,7 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
continue;
}
auto DumpRegionHeader = [&] {
- dbgs() << "********** MI Scheduling **********\n";
+ dbgs() << "Current Schedule Region\n";
dbgs() << MF->getName() << ":" << printMBBReference(*MBB) << " "
<< MBB->getName() << "\n From: " << *I << " To: ";
if (RegionEnd != MBB->end())
diff --git a/llvm/test/CodeGen/AArch64/aarch64-stp-cluster.ll b/llvm/test/CodeGen/AArch64/aarch64-stp-cluster.ll
index d97d9d1e0e091..517e71483e795 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-stp-cluster.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-stp-cluster.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -aarch64-enable-stp-suppress=false -o - 2>&1 > /dev/null | FileCheck %s
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -force-fast-cluster -verify-misched -debug-only=machine-scheduler -aarch64-enable-stp-suppress=false -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK-FAST
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK-LABEL: stp_i64_scale:%bb.0
; CHECK:Cluster ld/st SU(3) - SU(4)
; CHECK:Cluster ld/st SU(2) - SU(5)
@@ -23,7 +23,7 @@ entry:
ret i64 %v
}
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK-LABEL: stp_i32_scale:%bb.0
; CHECK:Cluster ld/st SU(3) - SU(4)
; CHECK:Cluster ld/st SU(2) - SU(5)
@@ -44,7 +44,7 @@ entry:
ret i32 %v
}
-; CHECK:********** MI Scheduling **********
+; CHECK:Current Schedule Region
; CHECK-LABEL:stp_i64_unscale:%bb.0 entry
; CHECK:Cluster ld/st SU(2) - SU(5)
; CHECK:Cluster ld/st SU(3) - SU(4)
@@ -65,7 +65,7 @@ entry:
ret void
}
-; CHECK:********** MI Scheduling **********
+; CHECK:Current Schedule Region
; CHECK-LABEL:stp_i32_unscale:%bb.0 entry
; CHECK:Cluster ld/st SU(2) - SU(5)
; CHECK:Cluster ld/st SU(3) - SU(4)
@@ -86,7 +86,7 @@ entry:
ret void
}
-; CHECK:********** MI Scheduling **********
+; CHECK:Current Schedule Region
; CHECK-LABEL:stp_double:%bb.0
; CHECK:Cluster ld/st SU(3) - SU(4)
; CHECK:Cluster ld/st SU(2) - SU(5)
@@ -107,7 +107,7 @@ entry:
ret void
}
-; CHECK:********** MI Scheduling **********
+; CHECK:Current Schedule Region
; CHECK-LABEL:stp_float:%bb.0
; CHECK:Cluster ld/st SU(3) - SU(4)
; CHECK:Cluster ld/st SU(2) - SU(5)
@@ -128,7 +128,7 @@ entry:
ret void
}
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK-LABEL: stp_volatile:%bb.0
; CHECK-NOT: Cluster ld/st
; CHECK:SU(2): STRXui %1:gpr64, %0:gpr64common, 3 :: (volatile
@@ -148,7 +148,7 @@ entry:
ret i64 %v
}
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK-LABEL: stp_i64_with_ld:%bb.0
; CHECK:Cluster ld/st SU(5) - SU(10)
; CHECK:Cluster ld/st SU(15) - SU(20)
@@ -197,7 +197,7 @@ entry:
}
; Verify that the SU(2) and SU(4) are the preds of SU(3)
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK-LABEL: stp_missing_preds_edges:%bb.0
; CHECK:Cluster ld/st SU(3) - SU(5)
; CHECK: Copy Pred SU(4)
@@ -217,7 +217,7 @@ entry:
; Verify that the SU(4) and SU(7) can be clustered even with
; different preds
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK-LABEL: cluster_with_different_preds:%bb.0
; CHECK:Cluster ld/st SU(4) - SU(7)
; CHECK:SU(3): STRWui %2:gpr32, %0:gpr64common, 0 ::
diff --git a/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll b/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
index 13093cb2204ce..0292b40549463 100644
--- a/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
@@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m3 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; Test ldr clustering.
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK-LABEL: ldr_int:%bb.0
; CHECK: Cluster ld/st SU(1) - SU(2)
; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
@@ -18,7 +18,7 @@ define i32 @ldr_int(ptr %a) nounwind {
}
; Test ldpsw clustering
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK-LABEL: ldp_sext_int:%bb.0
; CHECK: Cluster ld/st SU(1) - SU(2)
; CHECK: SU(1): %{{[0-9]+}}:gpr64 = LDRSWui
@@ -34,7 +34,7 @@ define i64 @ldp_sext_int(ptr %p) nounwind {
}
; Test ldur clustering.
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK-LABEL: ldur_int:%bb.0
; CHECK: Cluster ld/st SU(1) - SU(2)
; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDURWi
@@ -49,7 +49,7 @@ define i32 @ldur_int(ptr %a) nounwind {
}
; Test sext + zext clustering.
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK-LABEL: ldp_half_sext_zext_int:%bb.0
; CHECK: Cluster ld/st SU(3) - SU(4)
; CHECK: SU(3): %{{[0-9]+}}:gpr64 = LDRSWui
@@ -67,7 +67,7 @@ define i64 @ldp_half_sext_zext_int(ptr %q, ptr %p) nounwind {
}
; Test zext + sext clustering.
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK-LABEL: ldp_half_zext_sext_int:%bb.0
; CHECK: Cluster ld/st SU(3) - SU(4)
; CHECK: SU(3): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
@@ -85,7 +85,7 @@ define i64 @ldp_half_zext_sext_int(ptr %q, ptr %p) nounwind {
}
; Verify we don't cluster volatile loads.
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK-LABEL: ldr_int_volatile:%bb.0
; CHECK-NOT: Cluster ld/st
; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
@@ -100,7 +100,7 @@ define i32 @ldr_int_volatile(ptr %a) nounwind {
}
; Test ldq clustering (no clustering for Exynos).
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK-LABEL: ldq_cluster:%bb.0
; CHECK: Cluster ld/st SU(1) - SU(3)
; CHECK: SU(1): %{{[0-9]+}}:fpr128 = LDRQui
@@ -114,7 +114,7 @@ define <4 x i32> @ldq_cluster(ptr %p) {
ret <4 x i32> %res
}
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK: LDURSi_LDRSui:%bb.0 entry
; CHECK: Cluster ld/st SU(3) - SU(4)
; CHECK: SU(3): %3:fpr32 = LDURSi %0:gpr64
@@ -132,7 +132,7 @@ entry:
; Test LDURQi / LDRQui clustering
;
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK: LDURQi_LDRQui:%bb.1 vector_body
;
; CHECK: Cluster ld/st SU(0) - SU(4)
@@ -173,7 +173,7 @@ exit:
; Test LDURDi / LDRDui clustering
;
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK: LDURDi_LDRDui:%bb.1 vector_body
;
; CHECK: Cluster ld/st SU(0) - SU(4)
@@ -212,7 +212,7 @@ exit:
ret void
}
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK: LDURXi_LDRXui:%bb.0 entry
; CHECK: Cluster ld/st SU(3) - SU(4)
; CHECK: SU(3): %{{[0-9]+}}:gpr64 = LDURXi
@@ -228,7 +228,7 @@ entry:
ret void
}
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK: STURWi_STRWui:%bb.0 entry
; CHECK: Cluster ld/st SU(3) - SU(4)
; CHECK: SU(3): STURWi %{{[0-9]+}}:gpr32
@@ -242,7 +242,7 @@ entry:
ret void
}
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK: STURXi_STRXui:%bb.0 entry
; CHECK: Cluster ld/st SU(3) - SU(4)
; CHECK: SU(3): STURXi %{{[0-9]+}}:gpr64
@@ -256,7 +256,7 @@ entry:
ret void
}
-; CHECK-A57: ********** MI Scheduling **********
+; CHECK-A57: Current Schedule Region
; CHECK-A57: STURSi_STRSui:%bb.0 entry
; CHECK-A57: Cluster ld/st SU(3) - SU(4)
; CHECK-A57: SU(3): STURSi %{{[0-9]+}}:fpr32
@@ -270,7 +270,7 @@ entry:
ret void
}
-; CHECK-A57: ********** MI Scheduling **********
+; CHECK-A57: Current Schedule Region
; CHECK-A57: STURDi_STRDui:%bb.0 entry
; CHECK-A57: Cluster ld/st SU(3) - SU(4)
; CHECK-A57: SU(3): STURDi %{{[0-9]+}}:fpr64
@@ -284,7 +284,7 @@ entry:
ret void
}
-; CHECK-A57: ********** MI Scheduling **********
+; CHECK-A57: Current Schedule Region
; CHECK-A57: STURQi_STRQui:%bb.0 entry
; CHECK-A57: Cluster ld/st SU(3) - SU(4)
; CHECK-A57: SU(3): STURQi %{{[0-9]+}}:fpr128
diff --git a/llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll b/llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
index c6cf2403135a7..1b272c15d890f 100644
--- a/llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
@@ -6,7 +6,7 @@
; much higher than the ADD instructions in order to hide latency. When not
; specifying a subtarget, the MADD will remain near the end of the block.
;
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK: main
; CHECK: *** Final schedule for %bb.2 ***
; CHECK: MADDWrrr
@@ -82,7 +82,7 @@ for.end: ; preds = %for.cond
; hide latency. Whereas normally there would only be a single FADDvvv_4s
; after it, this test checks to make sure there are more than one.
;
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK: neon4xfloat:%bb.0
; CHECK: *** Final schedule for %bb.0 ***
; CHECK: FDIVv4f32
@@ -128,7 +128,7 @@ declare { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2.v16i8.p0(ptr)
;
; Cortex-A53 machine model stalls on A53UnitFPMDS contention. Instructions that
; are otherwise ready are jammed in the pending queue.
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK: testResourceConflict
; CHECK: *** Final schedule for %bb.0 ***
; CHECK: BRK
@@ -176,7 +176,7 @@ declare void @llvm.trap()
; Regression test for PR20057: "permanent hazard"'
; Resource contention on LDST.
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK: testLdStConflict
; CHECK: *** Final schedule for %bb.1 ***
; CHECK: LD4Fourv2d
diff --git a/llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll b/llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
index bb1a6b02a63de..3b0a57182eae7 100644
--- a/llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
@@ -7,7 +7,7 @@
; loads consecutively for this case and will cause stalls.
;
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK: main:%bb.2
; CHECK: LDR
; CHECK: Latency : 4
@@ -16,7 +16,7 @@
; CHECK: LDR
; CHECK-NOT: LDR
; CHECK: {{.*}}
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
@main.x = private unnamed_addr constant [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 4
@main.y = private unnamed_addr constant [8 x i32] [i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2], align 4
diff --git a/llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll b/llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll
index 8af6b82204708..e0cb80ac564ef 100644
--- a/llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll
@@ -4,7 +4,7 @@
; For Cortex-A53, shiftable operands that are not actually shifted
; are not needed for an additional two cycles.
;
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK: shiftable
; CHECK: SU(2): %2:gpr64common = SUBXri %1:gpr64common, 20, 0
; CHECK: Successors:
diff --git a/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll b/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
index 061d1161ba133..4c8ec9f4b91ca 100644
--- a/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
@@ -3,7 +3,7 @@
;
; Test for bug in misched memory dependency calculation.
;
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK: misched_bug:%bb.0 entry
; CHECK: SU(2): %2:gpr32 = LDRWui %0:gpr64common, 1 :: (load (s32) from %ir.ptr1_plus1)
; CHECK: Successors:
diff --git a/llvm/test/CodeGen/AArch64/macro-fusion.ll b/llvm/test/CodeGen/AArch64/macro-fusion.ll
index b9a263fe2e23a..f6267eea3003b 100644
--- a/llvm/test/CodeGen/AArch64/macro-fusion.ll
+++ b/llvm/test/CodeGen/AArch64/macro-fusion.ll
@@ -5,7 +5,7 @@
; only 2 SU's are fused at most.
define signext i32 @test(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) {
entry:
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK-LABEL: %bb.0 entry
; CHECK: Macro fuse: SU([[SU4:[0-9]+]]) - SU([[SU5:[0-9]+]])
; CHECK: Bind SU([[SU1:[0-9]+]]) - SU([[SU4]])
diff --git a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
index 31e14e204daa9..14fe46c1a6385 100644
--- a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
+++ b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
@@ -103,7 +103,7 @@ body: |
# CHECK-EMPTY:
# CHECK-NEXT: # End machine code for function umull_and_v8i32.
# CHECK-EMPTY:
-# CHECK-NEXT: ********** MI Scheduling **********
+# CHECK-NEXT: Current Schedule Region
# CHECK-NEXT: umull_and_v8i32:%bb.0 entry
# CHECK-NEXT: From: %2:fpr128 = COPY $q2
# CHECK-NEXT: To: RET_ReallyLR implicit $q0, implicit $q1
diff --git a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
index c8bb44ca76697..7dec1260fff67 100644
--- a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
+++ b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
@@ -34,7 +34,7 @@ body: |
# CHECK-EMPTY:
# CHECK-NEXT: # End machine code for function f.
# CHECK-EMPTY:
-# CHECK-NEXT: ********** MI Scheduling **********
+# CHECK-NEXT: Current Schedule Region
# CHECK-NEXT: f:%bb.0
# CHECK-NEXT: From: $x3 = ADDXrr $x0, $x0
# CHECK-NEXT: To: End
diff --git a/llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir b/llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
index 17a6cf7e6faa9..3a04a8e7f66c8 100644
--- a/llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
+++ b/llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
@@ -2,7 +2,7 @@
# RUN: llc -mcpu=exynos-m5 -mtriple=aarch64 -enable-misched -passes=machine-scheduler -debug-only=machine-scheduler %s -o /dev/null 2>&1 | FileCheck %s
# REQUIRES: asserts
-# CHECK-LABEL: ********** MI Scheduling **********
+# CHECK-LABEL: Current Schedule Region
# CHECK: SU(0): %0:fpr128 = COPY $q1
# CHECK-NEXT: # preds left : 0
# CHECK-NEXT: # succs left : 1
diff --git a/llvm/test/CodeGen/AArch64/scheduledag-constreg.mir b/llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
index 66680af3f856b..d44ae89fc5ff0 100644
--- a/llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
+++ b/llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
@@ -7,7 +7,7 @@
---
# Check that the instructions are not dependent on each other, even though
# they all read/write to the zero register.
-# CHECK-LABEL: MI Scheduling
+# CHECK-LABEL: Current Schedule Region
# CHECK: SU(0): dead $wzr = SUBSWri $w1, 0, 0, implicit-def dead $nzcv
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
diff --git a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
index cbd3eed750010..f3cd49ab72dec 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
+++ b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
@@ -2,9 +2,9 @@
# RUN: llc -mtriple=amdgpu9.08 -passes=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s
# REQUIRES: asserts
-# CHECK: ********** MI Scheduling **********
+# CHECK: Current Schedule Region
# CHECK-NEXT: test_get_liveins:%bb.0
-# CHECK: ********** MI Scheduling **********
+# CHECK: Current Schedule Region
# CHECK-NEXT: test_get_liveins:%bb.1
# CHECK: Region live-in pressure: VGPRs: 1 AGPRs: 0, SGPRs: 0, LVGPR WT: 0, LSGPR WT: 0
# CHECK: ScheduleDAGMILive::schedule starting
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-alu.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-alu.ll
index 7d50a2023ed81..9f9a9d9c86acc 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-alu.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-alu.ll
@@ -4,7 +4,7 @@
; Check the latency for ALU shifted operand variants.
;
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK: foo:%bb.0 entry
; ALU, basic - 1 cyc I0/I1
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll
index ec4e37f0ba804..672da5b8f9e50 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll
@@ -5,7 +5,7 @@
; Check the latency for instructions for both generic and cortex-a57.
; SDIV should be scheduled at the block's begin (20 cyc of independent M unit).
;
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK: foo:%bb.0 entry
; GENERIC: LDRi12
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
index 0e49a334e5a5b..34ec9cf665983 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
@@ -6,9 +6,9 @@
@b = dso_local global i32 0, align 4
@c = dso_local global i32 0, align 4
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; We need second, post-ra scheduling to have LDM instruction combined from single-loads
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK: LDMIA_UPD
; CHECK: rdefs left
; CHECK-NEXT: Latency : 4
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll
index 359936320c605..f079341a40664 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll
@@ -1,9 +1,9 @@
; REQUIRES: asserts
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; We need second, post-ra scheduling to have LDM instruction combined from single-loads
-; CHECK: ********** MI Scheduling **********
+; CHECK: Current Schedule Region
; CHECK: LDMIA
; CHECK: rdefs left
; CHECK-NEXT: Latency : 3
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir b/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir
index 2753796e7b90e..b6cb3b6d99659 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir
@@ -1,7 +1,7 @@
# REQUIRES: asserts
# RUN: llc -mcpu=cortex-a57 -mtriple=thumb -enable-misched -run-pass=machine-scheduler -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s
-# CHECK-LABEL: ********** MI Scheduling **********
+# CHECK-LABEL: Current Schedule Region
# CHECK: %[[RES:[0-9]+]]:rgpr = t2MLA
# CHECK-NEXT: # preds left
# CHECK-NEXT: # succs left
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll
index 773ac326942b0..a9cc50f35fae9 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll
@@ -2,9 +2,9 @@
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; N=3 STMIA_UPD should have latency 2cyc and writeback latency 1cyc
-; CHECK: ********** M...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/215540
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