[llvm] 54ec0a3 - [X86] Add test coverage for #215223 (#215502)

[via llvm-commits]

Author: Simon Pilgrim
Date: 2026-08-11T10:00:16Z
New Revision: 54ec0a39adafbb588ab6612a0824ef39e9e51ff4

URL: https://github.com/llvm/llvm-project/commit/54ec0a39adafbb588ab6612a0824ef39e9e51ff4
DIFF: https://github.com/llvm/llvm-project/commit/54ec0a39adafbb588ab6612a0824ef39e9e51ff4.diff

LOG: [X86] Add test coverage for #215223 (#215502)

Most concerning is the different (poison) result on SSE2 targets, but
the failure for SimplifyDemandedBits to correctly do its thing for AVX+
is terrible as well.

Added: 
    llvm/test/CodeGen/X86/pr215223.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/pr215223.ll b/llvm/test/CodeGen/X86/pr215223.ll
new file mode 100644
index 0000000000000..f0fd74acd308b
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr215223.ll
@@ -0,0 +1,73 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64    | FileCheck %s --check-prefixes=SSE2
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE42
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX2
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX512
+
+define i32 @PR215223(i64 %a0){
+; SSE2-LABEL: PR215223:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    retq
+;
+; SSE42-LABEL: PR215223:
+; SSE42:       # %bb.0:
+; SSE42-NEXT:    movl $1, %eax
+; SSE42-NEXT:    retq
+;
+; AVX2-LABEL: PR215223:
+; AVX2:       # %bb.0:
+; AVX2-NEXT:    cmpq $1, %rdi
+; AVX2-NEXT:    movl $1047803978, %eax # imm = 0x3E74384A
+; AVX2-NEXT:    sbbl $0, %eax
+; AVX2-NEXT:    vmovd %eax, %xmm0
+; AVX2-NEXT:    vpbroadcastd %xmm0, %xmm0
+; AVX2-NEXT:    vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX2-NEXT:    vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
+; AVX2-NEXT:    vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
+; AVX2-NEXT:    vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT:    vpor %xmm1, %xmm3, %xmm1
+; AVX2-NEXT:    vpor %xmm2, %xmm0, %xmm0
+; AVX2-NEXT:    vpor %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1]
+; AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; AVX2-NEXT:    vpor %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; AVX2-NEXT:    vpor %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vmovd %xmm0, %eax
+; AVX2-NEXT:    retq
+;
+; AVX512-LABEL: PR215223:
+; AVX512:       # %bb.0:
+; AVX512-NEXT:    cmpq $1, %rdi
+; AVX512-NEXT:    movl $1047803978, %eax # imm = 0x3E74384A
+; AVX512-NEXT:    sbbl $0, %eax
+; AVX512-NEXT:    vpbroadcastd %eax, %xmm0
+; AVX512-NEXT:    vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX512-NEXT:    vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
+; AVX512-NEXT:    vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
+; AVX512-NEXT:    vpor %xmm1, %xmm3, %xmm1
+; AVX512-NEXT:    vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT:    vpor %xmm2, %xmm0, %xmm0
+; AVX512-NEXT:    vpternlogd {{.*#+}} xmm0 = m32bcst & (xmm0 | xmm1)
+; AVX512-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; AVX512-NEXT:    vpor %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; AVX512-NEXT:    vpor %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vmovd %xmm0, %eax
+; AVX512-NEXT:    retq
+  %i1 = icmp eq i64 %a0, 0
+  %i2 = select i1 %i1, i32 1047803977, i32 1047803978
+  %i3 = insertelement <4 x i32> poison, i32 %i2, i64 0
+  %i4 = shufflevector <4 x i32> %i3, <4 x i32> poison, <4 x i32> zeroinitializer
+  %i5 = lshr <4 x i32> %i4, <i32 0, i32 1, i32 2, i32 3>
+  %i6 = lshr <4 x i32> %i4, <i32 4, i32 5, i32 6, i32 7>
+  %i7 = lshr <4 x i32> %i4, <i32 8, i32 9, i32 10, i32 11>
+  %i8 = or <4 x i32> %i7, %i5
+  %i9 = lshr <4 x i32> %i4, <i32 12, i32 13, i32 14, i32 15>
+  %i10 = or <4 x i32> %i9, %i6
+  %i11 = or <4 x i32> %i10, %i8
+  %i12 = and <4 x i32> %i11, splat (i32 1)
+  %i13 = tail call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %i12)
+  ret i32 %i13
+}