[llvm] 0a371a6 - [AMDGPU] Add custom lowering of llvm.convert.to.arbitrary.fp for FP8 (#213813)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 11 01:49:13 PDT 2026
Author: Dmitry Sidorov
Date: 2026-08-11T10:49:07+02:00
New Revision: 0a371a634026212e4c8b96fdc53d8b60c3d188a9
URL: https://github.com/llvm/llvm-project/commit/0a371a634026212e4c8b96fdc53d8b60c3d188a9
DIFF: https://github.com/llvm/llvm-project/commit/0a371a634026212e4c8b96fdc53d8b60c3d188a9.diff
LOG: [AMDGPU] Add custom lowering of llvm.convert.to.arbitrary.fp for FP8 (#213813)
Lower ISD::CONVERT_TO_ARBITRARY_FP to the packed hardware conversions on
subtargets that have the OCP fp8 formats.
An f32 source becomes V_CVT_PK_FP8_F32 or V_CVT_PK_BF8_F32. An f16
source becomes V_CVT_PK_FP8_F16 or V_CVT_PK_BF8_F16, which only gfx1250
and later have. A scalar conversion converts one lane and leaves the
other unused, a v2 conversion fills both lanes of the packed result.
Assisted-by: Claude-Opus-5
Added:
llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-fnuz.ll
llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
Modified:
llvm/include/llvm/Target/TargetSelectionDAG.td
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.h
llvm/lib/Target/AMDGPU/SIInstrInfo.td
llvm/lib/Target/AMDGPU/VOP1Instructions.td
llvm/lib/Target/AMDGPU/VOP3Instructions.td
llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
Removed:
################################################################################
diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index 37b7b8716bcd8..acf6ac8571fd4 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -178,6 +178,10 @@ def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
def SDTConvertFromArbitraryFPOp : SDTypeProfile<1, 2, [
SDTCisFP<0>, SDTCisInt<1>, SDTCisInt<2>, SDTCisSameNumEltsAs<0, 1>
]>;
+def SDTConvertToArbitraryFPOp : SDTypeProfile<1, 4, [
+ SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>, SDTCisInt<3>, SDTCisInt<4>,
+ SDTCisSameNumEltsAs<0, 1>
+]>;
def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>
]>;
@@ -651,6 +655,8 @@ def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
def convert_from_arbitrary_fp : SDNode<"ISD::CONVERT_FROM_ARBITRARY_FP",
SDTConvertFromArbitraryFPOp>;
+def convert_to_arbitrary_fp : SDNode<"ISD::CONVERT_TO_ARBITRARY_FP",
+ SDTConvertToArbitraryFPOp>;
def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
def fp_to_sint_sat : SDNode<"ISD::FP_TO_SINT_SAT" , SDTFPToIntSatOp>;
@@ -1279,11 +1285,16 @@ class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm,
class TImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm,
SDNode ImmNode = timm> : ImmLeaf<vt, pred, xform, ImmNode>;
-// llvm.convert.from.arbitrary.fp format-selector predicates.
+// llvm.convert.{from,to}.arbitrary.fp format-selector predicates.
// Only OCP formats are matched here; FNUZ formats use the generic expansion.
def Float8E4M3FN : TImmLeaf<i32, [{ return Imm == APFloatBase::S_Float8E4M3FN; }]>;
def Float8E5M2 : TImmLeaf<i32, [{ return Imm == APFloatBase::S_Float8E5M2; }]>;
+// llvm.convert.to.arbitrary.fp rounding-mode and saturation selectors.
+def NearestTiesToEven : TImmLeaf<i32,
+ [{ return Imm == static_cast<int>(RoundingMode::NearestTiesToEven); }]>;
+def FPNoSaturation : TImmLeaf<i32, [{ return Imm == 0; }]>;
+
// An ImmLeaf where the `Imm` in the C++ predicate is an `APInt`.
//
// This is useful when you need to zero-extend the immediate instead of
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index fb5c4279af4b7..c04bcfb0388f2 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -1060,6 +1060,11 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
setOperationAction(ISD::CONVERT_FROM_ARBITRARY_FP, {MVT::f32, MVT::v2f32},
Custom);
setOperationAction(ISD::CONVERT_FROM_ARBITRARY_FP, MVT::v2i8, Custom);
+
+ // i8 result promotes to i16, wider vectors split down to v2i8, and v2i8 is
+ // handled in ReplaceNodeResults before the legalizer splits it per lane.
+ setOperationAction(ISD::CONVERT_TO_ARBITRARY_FP, {MVT::i16, MVT::v2i8},
+ Custom);
}
if (Subtarget->hasFP8F16ConversionInsts()) {
@@ -7681,6 +7686,8 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
return LowerINTRINSIC_WO_CHAIN(Op, DAG);
case ISD::CONVERT_FROM_ARBITRARY_FP:
return LowerCONVERT_FROM_ARBITRARY_FP(Op, DAG);
+ case ISD::CONVERT_TO_ARBITRARY_FP:
+ return LowerCONVERT_TO_ARBITRARY_FP(Op, DAG);
case ISD::INTRINSIC_W_CHAIN:
return LowerINTRINSIC_W_CHAIN(Op, DAG);
case ISD::INTRINSIC_VOID:
@@ -8337,6 +8344,11 @@ void SITargetLowering::ReplaceNodeResults(SDNode *N,
Results.push_back(Res);
return;
}
+ case ISD::CONVERT_TO_ARBITRARY_FP: {
+ if (SDValue Res = LowerCONVERT_TO_ARBITRARY_FP(SDValue(N, 0), DAG))
+ Results.push_back(Res);
+ return;
+ }
case ISD::INTRINSIC_WO_CHAIN: {
unsigned IID = N->getConstantOperandVal(0);
switch (IID) {
@@ -11079,6 +11091,76 @@ SITargetLowering::LowerCONVERT_FROM_ARBITRARY_FP(SDValue Op,
return SDValue();
}
+SDValue SITargetLowering::lowerToFP8(SDValue Op, bool IsBF8,
+ SelectionDAG &DAG) const {
+ SDLoc SL(Op);
+ SDValue Src = Op.getOperand(0);
+ EVT ResVT = Op.getValueType();
+ bool IsF16 = Src.getValueType().getScalarType() == MVT::f16;
+ assert((!IsF16 || Subtarget->hasF16FP8ConversionInsts()) &&
+ "f16 -> fp8/bf8 conversion requires F16FP8ConversionInsts");
+ assert((!ResVT.isVector() || ResVT == MVT::v2i8) &&
+ "only the v2i8 vector result is custom lowered");
+
+ if (IsF16) {
+ unsigned Opc =
+ IsBF8 ? AMDGPUISD::CVT_PK_BF8_F16 : AMDGPUISD::CVT_PK_FP8_F16;
+ SDValue Bytes = DAG.getNode(Opc, SL, MVT::i16, Src);
+ return DAG.getNode(ISD::BITCAST, SL, ResVT, Bytes);
+ }
+
+ unsigned Opc = IsBF8 ? AMDGPUISD::CVT_PK_BF8_F32 : AMDGPUISD::CVT_PK_FP8_F32;
+ SDValue PoisonI32 = DAG.getPOISON(MVT::i32);
+ SDValue WordSel = DAG.getTargetConstant(0, SL, MVT::i1);
+
+ if (!ResVT.isVector()) {
+ // Convert one lane, the second is unused. Feed it the same source so the
+ // instruction does not read an undefined register.
+ SDValue Packed =
+ DAG.getNode(Opc, SL, MVT::i32, Src, Src, PoisonI32, WordSel);
+ return DAG.getAnyExtOrTrunc(Packed, SL, ResVT);
+ }
+
+ SDValue A = DAG.getExtractVectorElt(SL, MVT::f32, Src, 0);
+ SDValue B = DAG.getExtractVectorElt(SL, MVT::f32, Src, 1);
+ SDValue Packed = DAG.getNode(Opc, SL, MVT::i32, A, B, PoisonI32, WordSel);
+ SDValue Bytes = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Packed);
+ return DAG.getNode(ISD::BITCAST, SL, ResVT, Bytes);
+}
+
+SDValue
+SITargetLowering::LowerCONVERT_TO_ARBITRARY_FP(SDValue Op,
+ SelectionDAG &DAG) const {
+ // Only the OCP fp8 formats E4M3FN and E5M2 map to HW conversions, everything
+ // else uses the generic expansion.
+ APFloatBase::Semantics Sem =
+ static_cast<APFloatBase::Semantics>(Op.getConstantOperandVal(1));
+ if (Sem != APFloatBase::S_Float8E4M3FN && Sem != APFloatBase::S_Float8E5M2)
+ return SDValue();
+ bool IsBF8 = Sem == APFloatBase::S_Float8E5M2;
+
+ // The packed HW conversions round to nearest-even and never saturate.
+ if (static_cast<RoundingMode>(Op.getConstantOperandVal(2)) !=
+ RoundingMode::NearestTiesToEven)
+ return SDValue();
+ if (Op.getConstantOperandVal(3) != 0)
+ return SDValue();
+
+ EVT SrcEltVT = Op.getOperand(0).getValueType().getScalarType();
+ // The f32 form is built here rather than by a tablegen pattern because the
+ // HW result is i32 while the node result is i16 after the i8 promotion.
+ if (SrcEltVT == MVT::f32)
+ return lowerToFP8(Op, IsBF8, DAG);
+ if (SrcEltVT == MVT::f16 && Subtarget->hasF16FP8ConversionInsts()) {
+ // A scalar conversion is selected from the generic node by tablegen, only
+ // the illegal v2i8 result type needs lowering here.
+ if (!Op.getValueType().isVector())
+ return Op;
+ return lowerToFP8(Op, IsBF8, DAG);
+ }
+ return SDValue();
+}
+
SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h
index 64d71f09edc33..f3733ada688a5 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h
@@ -107,6 +107,8 @@ class SITargetLowering final : public AMDGPUTargetLowering {
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerCONVERT_FROM_ARBITRARY_FP(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerFromFP8(SDValue Op, bool IsBF8, SelectionDAG &DAG) const;
+ SDValue LowerCONVERT_TO_ARBITRARY_FP(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerToFP8(SDValue Op, bool IsBF8, SelectionDAG &DAG) const;
// The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
// (the offset that is included in bounds checking and swizzling, to be split
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 5baf52dd12407..0268afb2e494c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -331,6 +331,17 @@ def cvt_from_fp8 : PatFrag<(ops node:$src),
def cvt_from_bf8 : PatFrag<(ops node:$src),
(convert_from_arbitrary_fp node:$src, Float8E5M2)>;
+// The packed HW conversions round to nearest-even and never saturate, so only
+// those forms of convert_to_arbitrary_fp are matched here.
+def cvt_to_fp8 : PatFrag<(ops node:$src),
+ (convert_to_arbitrary_fp node:$src, Float8E4M3FN,
+ NearestTiesToEven,
+ FPNoSaturation)>;
+def cvt_to_bf8 : PatFrag<(ops node:$src),
+ (convert_to_arbitrary_fp node:$src, Float8E5M2,
+ NearestTiesToEven,
+ FPNoSaturation)>;
+
def AMDGPUcvt_pk_f32_fp8 : SDNode<"AMDGPUISD::CVT_PK_F32_FP8",
SDTypeProfile<1, 1, [SDTCisVT<0, v2f32>, SDTCisVT<1, i32>]>>;
def AMDGPUcvt_pk_f32_bf8 : SDNode<"AMDGPUISD::CVT_PK_F32_BF8",
@@ -345,6 +356,28 @@ def cvt_pk_f16_fp8 : PatFrags<(ops node:$src),
def cvt_pk_f16_bf8 : PatFrags<(ops node:$src),
[(int_amdgcn_cvt_pk_f16_bf8 node:$src), (AMDGPUcvt_pk_f16_bf8 node:$src)]>;
+def AMDGPUcvt_pk_fp8_f32 : SDNode<"AMDGPUISD::CVT_PK_FP8_F32",
+ SDTypeProfile<1, 4, [SDTCisVT<0, i32>, SDTCisVT<1, f32>, SDTCisVT<2, f32>,
+ SDTCisVT<3, i32>, SDTCisVT<4, i1>]>>;
+def AMDGPUcvt_pk_bf8_f32 : SDNode<"AMDGPUISD::CVT_PK_BF8_F32",
+ SDTypeProfile<1, 4, [SDTCisVT<0, i32>, SDTCisVT<1, f32>, SDTCisVT<2, f32>,
+ SDTCisVT<3, i32>, SDTCisVT<4, i1>]>>;
+def AMDGPUcvt_pk_fp8_f16 : SDNode<"AMDGPUISD::CVT_PK_FP8_F16",
+ SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, v2f16>]>>;
+def AMDGPUcvt_pk_bf8_f16 : SDNode<"AMDGPUISD::CVT_PK_BF8_F16",
+ SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, v2f16>]>>;
+
+def cvt_pk_fp8_f32 : PatFrags<(ops node:$src0, node:$src1, node:$old, node:$sel),
+ [(int_amdgcn_cvt_pk_fp8_f32 node:$src0, node:$src1, node:$old, node:$sel),
+ (AMDGPUcvt_pk_fp8_f32 node:$src0, node:$src1, node:$old, node:$sel)]>;
+def cvt_pk_bf8_f32 : PatFrags<(ops node:$src0, node:$src1, node:$old, node:$sel),
+ [(int_amdgcn_cvt_pk_bf8_f32 node:$src0, node:$src1, node:$old, node:$sel),
+ (AMDGPUcvt_pk_bf8_f32 node:$src0, node:$src1, node:$old, node:$sel)]>;
+def cvt_pk_fp8_f16 : PatFrags<(ops node:$src),
+ [(int_amdgcn_cvt_pk_fp8_f16 node:$src), (AMDGPUcvt_pk_fp8_f16 node:$src)]>;
+def cvt_pk_bf8_f16 : PatFrags<(ops node:$src),
+ [(int_amdgcn_cvt_pk_bf8_f16 node:$src), (AMDGPUcvt_pk_bf8_f16 node:$src)]>;
+
//===----------------------------------------------------------------------===//
// ValueType helpers
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index af02b9a5e5f03..054539611b38c 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -1234,12 +1234,34 @@ let ReadsModeReg = 0 in {
VOP1_CVT_PK_F8_F16_Profile<VSrc_NoInline_v2f16>,
VOP1_CVT_PK_F8_F16_True16_Profile<VSrc_NoInline_v2f16>,
VOP1_CVT_PK_F8_F16_Fake16_Profile<VSrc_NoInline_v2f16>,
- int_amdgcn_cvt_pk_fp8_f16>;
+ cvt_pk_fp8_f16>;
defm V_CVT_PK_BF8_F16 : VOP1Inst_t16_with_profiles<"v_cvt_pk_bf8_f16",
VOP1_CVT_PK_F8_F16_Profile<VSrc_NoInline_v2f16>,
VOP1_CVT_PK_F8_F16_True16_Profile<VSrc_NoInline_v2f16>,
VOP1_CVT_PK_F8_F16_Fake16_Profile<VSrc_NoInline_v2f16>,
- int_amdgcn_cvt_pk_bf8_f16>;
+ cvt_pk_bf8_f16>;
+}
+
+// A scalar conversion converts the low lane and leaves the high one undefined.
+// The vector form is custom lowered instead, its <2 x i8> result type has to
+// be legalized first.
+let OtherPredicates = [HasOCPFP8ConversionInsts] in {
+let True16Predicate = UseRealTrue16Insts in {
+ def : GCNPat<(i16 (cvt_to_fp8 (f16 VGPR_16:$src))),
+ (V_CVT_PK_FP8_F16_t16_e64 0,
+ (REG_SEQUENCE VGPR_32, $src, lo16, (f16 (IMPLICIT_DEF)), hi16), 0)>;
+ def : GCNPat<(i16 (cvt_to_bf8 (f16 VGPR_16:$src))),
+ (V_CVT_PK_BF8_F16_t16_e64 0,
+ (REG_SEQUENCE VGPR_32, $src, lo16, (f16 (IMPLICIT_DEF)), hi16), 0)>;
+}
+let True16Predicate = UseFakeTrue16Insts in {
+ def : GCNPat<(i16 (cvt_to_fp8 f16:$src)),
+ (V_CVT_PK_FP8_F16_fake16_e64 0,
+ (v2f16 (COPY_TO_REGCLASS $src, VGPR_32)), 0)>;
+ def : GCNPat<(i16 (cvt_to_bf8 f16:$src)),
+ (V_CVT_PK_BF8_F16_fake16_e64 0,
+ (v2f16 (COPY_TO_REGCLASS $src, VGPR_32)), 0)>;
+}
}
}
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 219bd4805903e..7fc252a65d065 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -898,24 +898,24 @@ let OtherPredicates = [HasFP8ConversionInsts] in {
foreach Index = [0, -1] in {
let True16Predicate = NotHasTrue16BitInsts in {
let OtherPredicates = [HasFP8ConversionInsts, NotHasFP8E5M3Insts] in
- def : Cvt_PK_F8_F32_Pat<int_amdgcn_cvt_pk_fp8_f32, Index, V_CVT_PK_FP8_F32_e64>;
- def : Cvt_PK_F8_F32_Pat<int_amdgcn_cvt_pk_bf8_f32, Index, V_CVT_PK_BF8_F32_e64>;
+ def : Cvt_PK_F8_F32_Pat<cvt_pk_fp8_f32, Index, V_CVT_PK_FP8_F32_e64>;
+ def : Cvt_PK_F8_F32_Pat<cvt_pk_bf8_f32, Index, V_CVT_PK_BF8_F32_e64>;
}
let True16Predicate = UseFakeTrue16Insts in {
- def : Cvt_PK_F8_F32_Pat<int_amdgcn_cvt_pk_fp8_f32, Index, V_CVT_PK_FP8_F32_fake16_e64>;
- def : Cvt_PK_F8_F32_Pat<int_amdgcn_cvt_pk_bf8_f32, Index, V_CVT_PK_BF8_F32_fake16_e64>;
+ def : Cvt_PK_F8_F32_Pat<cvt_pk_fp8_f32, Index, V_CVT_PK_FP8_F32_fake16_e64>;
+ def : Cvt_PK_F8_F32_Pat<cvt_pk_bf8_f32, Index, V_CVT_PK_BF8_F32_fake16_e64>;
let OtherPredicates = [HasFP8ConversionInsts, HasFP8E5M3Insts] in {
- def : Cvt_PK_F8_F32_E5M3_Pat<int_amdgcn_cvt_pk_fp8_f32, Index, V_CVT_PK_FP8_F32_gfx1250_fake16_e64, DSTCLAMP.NONE>;
+ def : Cvt_PK_F8_F32_E5M3_Pat<cvt_pk_fp8_f32, Index, V_CVT_PK_FP8_F32_gfx1250_fake16_e64, DSTCLAMP.NONE>;
def : Cvt_PK_F8_F32_E5M3_Pat<int_amdgcn_cvt_pk_fp8_f32_e5m3, Index, V_CVT_PK_FP8_F32_gfx1250_fake16_e64, DSTCLAMP.ENABLE>;
}
}
}
let True16Predicate = UseRealTrue16Insts in {
-defm : Cvt_PK_F8_F32_t16_Pat<int_amdgcn_cvt_pk_fp8_f32, V_CVT_PK_FP8_F32_t16_e64>;
-defm : Cvt_PK_F8_F32_t16_Pat<int_amdgcn_cvt_pk_bf8_f32, V_CVT_PK_BF8_F32_t16_e64>;
+defm : Cvt_PK_F8_F32_t16_Pat<cvt_pk_fp8_f32, V_CVT_PK_FP8_F32_t16_e64>;
+defm : Cvt_PK_F8_F32_t16_Pat<cvt_pk_bf8_f32, V_CVT_PK_BF8_F32_t16_e64>;
let OtherPredicates = [HasFP8ConversionInsts, HasFP8E5M3Insts] in {
- defm : Cvt_PK_F8_F32_E5M3_t16_Pat<int_amdgcn_cvt_pk_fp8_f32, V_CVT_PK_FP8_F32_gfx1250_t16_e64, DSTCLAMP.NONE>;
+ defm : Cvt_PK_F8_F32_E5M3_t16_Pat<cvt_pk_fp8_f32, V_CVT_PK_FP8_F32_gfx1250_t16_e64, DSTCLAMP.NONE>;
defm : Cvt_PK_F8_F32_E5M3_t16_Pat<int_amdgcn_cvt_pk_fp8_f32_e5m3, V_CVT_PK_FP8_F32_gfx1250_t16_e64, DSTCLAMP.ENABLE>;
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
new file mode 100644
index 0000000000000..d4288ae2362e7
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
@@ -0,0 +1,2383 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=amdgpu12.50-amd-amdhsa -mattr=+real-true16 | FileCheck -check-prefix=GFX1250-TRUE16 %s
+; RUN: llc < %s -mtriple=amdgpu12.50-amd-amdhsa -mattr=-real-true16 | FileCheck -check-prefix=GFX1250-FAKE16 %s
+; RUN: llc < %s -mtriple=amdgpu9.50-amd-amdhsa | FileCheck -check-prefix=GFX950 %s
+; RUN: llc < %s -mtriple=amdgpu13.10-amd-amdhsa | FileCheck -check-prefix=GFX1310 %s
+
+; llvm.convert.to.arbitrary.fp to OCP FP8 E4M3FN and BF8 E5M2 from f16, lowered
+; to the packed v_cvt_pk_{fp8,bf8}_f16 HW instructions on the subtargets that
+; have them. gfx950 has no f16 conversion so it uses the generic expansion.
+
+define i8 @to_fp8_f16(half %x) {
+; GFX1250-TRUE16-LABEL: to_fp8_f16:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v0.l, v0
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_fp8_f16:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v0, v0
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX950-LABEL: to_fp8_f16:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v3, v0
+; GFX950-NEXT: v_sub_u16_e32 v4, 2, v3
+; GFX950-NEXT: v_frexp_mant_f16_e32 v1, v0
+; GFX950-NEXT: s_movk_i32 s0, 0x400
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x3ff
+; GFX950-NEXT: v_min_u16_e32 v4, 15, v4
+; GFX950-NEXT: v_bitop3_b16 v2, v1, s0, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v7, v4, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, v4, v2
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, v7, v2
+; GFX950-NEXT: v_lshlrev_b16_e64 v7, v7, 1
+; GFX950-NEXT: v_and_b32_e32 v8, 0x3ff, v1
+; GFX950-NEXT: v_add_u16_e32 v7, -1, v7
+; GFX950-NEXT: v_bitop3_b16 v7, v8, v7, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
+; GFX950-NEXT: v_and_b32_e32 v6, 1, v5
+; GFX950-NEXT: s_movk_i32 s0, 0x80
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v7, v6 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, 7, v8
+; GFX950-NEXT: v_and_b32_e32 v7, 1, v6
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX950-NEXT: v_add_u16_e32 v2, v5, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
+; GFX950-NEXT: v_and_b32_sdwa v5, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v5, v2, v4 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v4, 6, v1
+; GFX950-NEXT: v_and_b32_e32 v1, 63, v1
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v4, v1, v7 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v1, v6, v1
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v3, v3, v4
+; GFX950-NEXT: v_add_u16_e32 v3, 6, v3
+; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v4, 3, v3
+; GFX950-NEXT: v_bitop3_b16 v1, v5, v1, v4 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x7f
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_f16:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v0, v0
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call i8 @llvm.convert.to.arbitrary.fp.i8.f16(half %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
+ ret i8 %r
+}
+
+define i8 @to_bf8_f16(half %x) {
+; GFX1250-TRUE16-LABEL: to_bf8_f16:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v0.l, v0
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_bf8_f16:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f16_e64 v0, v0
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX950-LABEL: to_bf8_f16:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v3, v0
+; GFX950-NEXT: v_sub_u16_e32 v4, -5, v3
+; GFX950-NEXT: v_frexp_mant_f16_e32 v1, v0
+; GFX950-NEXT: s_movk_i32 s0, 0x400
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x3ff
+; GFX950-NEXT: v_min_u16_e32 v4, 15, v4
+; GFX950-NEXT: v_bitop3_b16 v2, v1, s0, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v7, v4, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, v4, v2
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, v7, v2
+; GFX950-NEXT: v_lshlrev_b16_e64 v7, v7, 1
+; GFX950-NEXT: v_and_b32_e32 v8, 0x3ff, v1
+; GFX950-NEXT: v_add_u16_e32 v7, -1, v7
+; GFX950-NEXT: v_bitop3_b16 v7, v8, v7, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
+; GFX950-NEXT: v_and_b32_e32 v6, 1, v5
+; GFX950-NEXT: s_movk_i32 s2, 0x7c
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v7, v6 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
+; GFX950-NEXT: v_mov_b32_e32 v7, 1
+; GFX950-NEXT: v_and_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX950-NEXT: v_add_u16_e32 v2, v5, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v2
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, 8, v0
+; GFX950-NEXT: v_and_b32_e32 v6, 0x80, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 4, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v6, v2, v4 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v4, 7, v1
+; GFX950-NEXT: v_and_b32_e32 v1, 0x7f, v1
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v4, v1, v7 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v3, v3, v4
+; GFX950-NEXT: v_add_u16_e32 v3, 14, v3
+; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v4, 2, v3
+; GFX950-NEXT: v_bitop3_b16 v4, v6, v1, v4 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v3
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 30, v3
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v1
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 30, v3
+; GFX950-NEXT: v_mov_b32_e32 v1, 0x80
+; GFX950-NEXT: v_bitop3_b16 v1, v5, s2, v1 bitop3:0xec
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v1, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
+; GFX950-NEXT: s_movk_i32 s0, 0x204
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX950-NEXT: v_cmp_class_f16_e64 vcc, v0, s0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x7e
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1310-LABEL: to_bf8_f16:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_bf8_f16_e32 v0, v0
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call i8 @llvm.convert.to.arbitrary.fp.i8.f16(half %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
+ ret i8 %r
+}
+
+define <2 x i8> @to_fp8_v2f16(<2 x half> %x) {
+; GFX1250-TRUE16-LABEL: to_fp8_v2f16:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v0.l, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v1.l, 8, v0.l
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_fp8_v2f16:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v0, v0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v1, 8, v0
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX950-LABEL: to_fp8_v2f16:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v4, v0
+; GFX950-NEXT: v_sub_u16_e32 v5, 2, v4
+; GFX950-NEXT: v_frexp_mant_f16_e32 v1, v0
+; GFX950-NEXT: s_movk_i32 s0, 0x400
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x3ff
+; GFX950-NEXT: v_min_u16_e32 v5, 15, v5
+; GFX950-NEXT: v_bitop3_b16 v3, v1, s0, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v8, v5, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, v5, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v8, v3
+; GFX950-NEXT: v_lshlrev_b16_e64 v8, v8, 1
+; GFX950-NEXT: v_and_b32_e32 v9, 0x3ff, v1
+; GFX950-NEXT: v_add_u16_e32 v8, -1, v8
+; GFX950-NEXT: v_bitop3_b16 v8, v9, v8, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
+; GFX950-NEXT: v_and_b32_e32 v7, 1, v6
+; GFX950-NEXT: s_movk_i32 s1, 0x80
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v3, v8, v7 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, 7, v9
+; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
+; GFX950-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX950-NEXT: v_add_u16_e32 v3, v6, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
+; GFX950-NEXT: v_and_b32_sdwa v6, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v6, v3, v5 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, 6, v1
+; GFX950-NEXT: v_and_b32_e32 v1, 63, v1
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v5, v1, v8 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v1, v7, v1
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v4, v4, v5
+; GFX950-NEXT: v_add_u16_e32 v4, 6, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v5, 3, v4
+; GFX950-NEXT: v_bitop3_b16 v1, v6, v1, v5 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v4
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
+; GFX950-NEXT: v_bitop3_b16 v2, v4, s0, v2 bitop3:0xec
+; GFX950-NEXT: v_and_b32_e32 v10, 0x3ff, v4
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
+; GFX950-NEXT: v_sub_u16_e32 v6, 2, v5
+; GFX950-NEXT: v_min_u16_e32 v6, 15, v6
+; GFX950-NEXT: v_sub_u16_e64 v9, v6, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, v6, v2
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, v9, v2
+; GFX950-NEXT: v_lshlrev_b16_e64 v9, v9, 1
+; GFX950-NEXT: v_add_u16_e32 v9, -1, v9
+; GFX950-NEXT: v_mov_b32_e32 v3, 0x7f
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
+; GFX950-NEXT: v_bitop3_b16 v9, v10, v9, s0 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: s_movk_i32 s0, 0xff
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v9, v8 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, 7, v10
+; GFX950-NEXT: v_and_b32_e32 v9, 1, v8
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX950-NEXT: v_add_u16_e32 v2, v7, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
+; GFX950-NEXT: v_lshrrev_b32_e32 v7, 31, v0
+; GFX950-NEXT: v_lshlrev_b16_e32 v7, 7, v7
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v7, v2, v6 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, 6, v4
+; GFX950-NEXT: v_and_b32_e32 v4, 63, v4
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v6, v4, v9 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v4, v8, v4
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v5, v6
+; GFX950-NEXT: v_add_u16_e32 v5, 6, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v6, 3, v5
+; GFX950-NEXT: v_bitop3_b16 v4, v7, v4, v6 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v5
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX950-NEXT: v_mov_b32_e32 v4, 0
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v4 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v0, 8, v2
+; GFX950-NEXT: v_bitop3_b16 v0, v1, v0, s0 bitop3:0xec
+; GFX950-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_v2f16:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v0, v0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1310-NEXT: v_lshrrev_b16 v1, 8, v0
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <2 x i8> @llvm.convert.to.arbitrary.fp.v2i8.v2f16(<2 x half> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
+ ret <2 x i8> %r
+}
+
+define <2 x i8> @to_bf8_v2f16(<2 x half> %x) {
+; GFX1250-TRUE16-LABEL: to_bf8_v2f16:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v0.l, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v1.l, 8, v0.l
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_bf8_v2f16:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f16_e64 v0, v0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v1, 8, v0
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX950-LABEL: to_bf8_v2f16:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v4, v0
+; GFX950-NEXT: v_sub_u16_e32 v5, -5, v4
+; GFX950-NEXT: v_frexp_mant_f16_e32 v1, v0
+; GFX950-NEXT: s_movk_i32 s2, 0x400
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x3ff
+; GFX950-NEXT: v_min_u16_e32 v5, 15, v5
+; GFX950-NEXT: v_bitop3_b16 v3, v1, s2, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v8, v5, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, v5, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v8, v3
+; GFX950-NEXT: v_lshlrev_b16_e64 v8, v8, 1
+; GFX950-NEXT: v_and_b32_e32 v9, 0x3ff, v1
+; GFX950-NEXT: v_add_u16_e32 v8, -1, v8
+; GFX950-NEXT: v_bitop3_b16 v8, v9, v8, s2 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
+; GFX950-NEXT: v_and_b32_e32 v7, 1, v6
+; GFX950-NEXT: s_movk_i32 s3, 0x7c
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v3, v8, v7 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5
+; GFX950-NEXT: v_mov_b32_e32 v8, 1
+; GFX950-NEXT: v_and_b32_sdwa v10, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX950-NEXT: v_add_u16_e32 v3, v6, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, 8, v0
+; GFX950-NEXT: v_and_b32_e32 v7, 0x80, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 4, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v7, v3, v5 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, 7, v1
+; GFX950-NEXT: v_and_b32_e32 v1, 0x7f, v1
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v5, v1, v10 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v4, v4, v5
+; GFX950-NEXT: v_add_u16_e32 v4, 14, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v5, 2, v4
+; GFX950-NEXT: v_bitop3_b16 v5, v7, v1, v5 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v4
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 30, v4
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v1
+; GFX950-NEXT: v_mov_b32_e32 v1, 0x80
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 30, v4
+; GFX950-NEXT: v_bitop3_b16 v1, v6, s3, v1 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e32 v6, -5, v5
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_min_u16_e32 v6, 15, v6
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
+; GFX950-NEXT: v_bitop3_b16 v2, v4, s2, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v10, v6, 1 clamp
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX950-NEXT: s_movk_i32 s3, 0x204
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, v6, v2
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, v10, v2
+; GFX950-NEXT: v_lshlrev_b16_e64 v10, v10, 1
+; GFX950-NEXT: v_cmp_class_f16_e64 vcc, v0, s3
+; GFX950-NEXT: v_and_b32_e32 v11, 0x3ff, v4
+; GFX950-NEXT: v_add_u16_e32 v10, -1, v10
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX950-NEXT: v_mov_b32_e32 v3, 0x7e
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
+; GFX950-NEXT: v_bitop3_b16 v10, v11, v10, s2 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v9, 1, v7
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_and_b32_sdwa v8, v11, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v10, v9 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX950-NEXT: v_add_u16_e32 v2, v7, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v2
+; GFX950-NEXT: v_lshrrev_b32_e32 v7, 31, v0
+; GFX950-NEXT: v_lshlrev_b16_e32 v7, 7, v7
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 4, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v7, v2, v6 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, 7, v4
+; GFX950-NEXT: v_and_b32_e32 v4, 0x7f, v4
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v6, v4, v8 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_sdwa v4, v11, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v4
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v5, v6
+; GFX950-NEXT: v_add_u16_e32 v5, 14, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v6, 2, v5
+; GFX950-NEXT: v_bitop3_b16 v6, v7, v4, v6 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v5
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 30, v5
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v4
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 30, v5
+; GFX950-NEXT: v_or_b32_e32 v4, 0x7c, v7
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_mov_b32_e32 v5, 0
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v5 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
+; GFX950-NEXT: v_cmp_class_f16_sdwa s[0:1], v0, s3 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v0, 8, v2
+; GFX950-NEXT: s_movk_i32 s0, 0xff
+; GFX950-NEXT: v_bitop3_b16 v0, v1, v0, s0 bitop3:0xec
+; GFX950-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1310-LABEL: to_bf8_v2f16:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_bf8_f16_e32 v0, v0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1310-NEXT: v_lshrrev_b16 v1, 8, v0
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <2 x i8> @llvm.convert.to.arbitrary.fp.v2i8.v2f16(<2 x half> %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
+ ret <2 x i8> %r
+}
+
+define <3 x i8> @to_fp8_v3f16(<3 x half> %x) {
+; GFX1250-TRUE16-LABEL: to_fp8_v3f16:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v2.h, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v2.l, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_fp8_v3f16:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v0, v0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v2, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
+; GFX1250-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX950-LABEL: to_fp8_v3f16:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v5, v0
+; GFX950-NEXT: v_sub_u16_e32 v6, 2, v5
+; GFX950-NEXT: v_frexp_mant_f16_e32 v3, v0
+; GFX950-NEXT: s_movk_i32 s0, 0x400
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x3ff
+; GFX950-NEXT: v_min_u16_e32 v6, 15, v6
+; GFX950-NEXT: v_bitop3_b16 v4, v3, s0, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v9, v6, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, v6, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v4, v9, v4
+; GFX950-NEXT: v_lshlrev_b16_e64 v9, v9, 1
+; GFX950-NEXT: v_and_b32_e32 v10, 0x3ff, v3
+; GFX950-NEXT: v_add_u16_e32 v9, -1, v9
+; GFX950-NEXT: v_bitop3_b16 v9, v10, v9, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
+; GFX950-NEXT: s_movk_i32 s1, 0x80
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v4, v9, v8 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, 7, v10
+; GFX950-NEXT: v_and_b32_e32 v9, 1, v8
+; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX950-NEXT: v_add_u16_e32 v4, v7, v4
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
+; GFX950-NEXT: v_and_b32_sdwa v7, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_movk_i32 s2, 0xff
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v7, v4, v6 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, 6, v3
+; GFX950-NEXT: v_and_b32_e32 v3, 63, v3
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v6, v3, v9 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v3, v8, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v5, v6
+; GFX950-NEXT: v_add_u16_e32 v5, 6, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v6, 3, v5
+; GFX950-NEXT: v_bitop3_b16 v3, v7, v3, v6 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v5
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v6, v5, s0, v2 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
+; GFX950-NEXT: v_and_b32_e32 v12, 0x3ff, v5
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v7, vcc
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_sub_u16_e32 v8, 2, v7
+; GFX950-NEXT: v_min_u16_e32 v8, 15, v8
+; GFX950-NEXT: v_sub_u16_e64 v11, v8, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, v8, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, v11, v6
+; GFX950-NEXT: v_lshlrev_b16_e64 v11, v11, 1
+; GFX950-NEXT: v_add_u16_e32 v11, -1, v11
+; GFX950-NEXT: v_mov_b32_e32 v3, 0x7f
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
+; GFX950-NEXT: v_bitop3_b16 v11, v12, v11, s0 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v10, 1, v9
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v6, v11, v10 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, 7, v12
+; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX950-NEXT: v_add_u16_e32 v6, v9, v6
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
+; GFX950-NEXT: v_lshrrev_b32_e32 v9, 31, v0
+; GFX950-NEXT: v_lshlrev_b16_e32 v9, 7, v9
+; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v9, v6, v8 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, 6, v5
+; GFX950-NEXT: v_and_b32_e32 v5, 63, v5
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v8, v5, v11 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v5, v10, v5
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v7, v7, v8
+; GFX950-NEXT: v_add_u16_e32 v7, 6, v7
+; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v8, 3, v7
+; GFX950-NEXT: v_bitop3_b16 v5, v9, v5, v8 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v7
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v8, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; GFX950-NEXT: v_mov_b32_e32 v6, 0
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v6 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: v_sub_u16_e32 v9, 2, v8
+; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v5, 8, v0
+; GFX950-NEXT: v_bitop3_b16 v0, v4, v5, s2 bitop3:0xec
+; GFX950-NEXT: v_frexp_mant_f16_e32 v4, v1
+; GFX950-NEXT: v_bitop3_b16 v7, v4, s0, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v12, v9, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, v9, v7
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, v12, v7
+; GFX950-NEXT: v_lshlrev_b16_e64 v12, v12, 1
+; GFX950-NEXT: v_and_b32_e32 v13, 0x3ff, v4
+; GFX950-NEXT: v_add_u16_e32 v12, -1, v12
+; GFX950-NEXT: v_bitop3_b16 v12, v13, v12, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v7, v12, v11 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v13
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
+; GFX950-NEXT: v_add_u16_e32 v7, v10, v7
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v7
+; GFX950-NEXT: v_and_b32_sdwa v10, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v10, v7, v9 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v4
+; GFX950-NEXT: v_and_b32_e32 v4, 63, v4
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v9, v4, v12 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v4, v11, v4
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v8, v8, v9
+; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v9, 3, v8
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v4, v10, v4, v9 bitop3:0xfe
+; GFX950-NEXT: v_sub_u16_e32 v9, 2, v8
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1
+; GFX950-NEXT: v_bitop3_b16 v2, v7, s0, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v12, v9, 1 clamp
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, v9, v2
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, v12, v2
+; GFX950-NEXT: v_lshlrev_b16_e64 v12, v12, 1
+; GFX950-NEXT: v_and_b32_e32 v13, 0x3ff, v7
+; GFX950-NEXT: v_add_u16_e32 v12, -1, v12
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v1, v1
+; GFX950-NEXT: v_bitop3_b16 v12, v13, v12, s0 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v12, v11 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v13
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX950-NEXT: v_add_u16_e32 v2, v10, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
+; GFX950-NEXT: v_lshrrev_b32_e32 v10, 31, v1
+; GFX950-NEXT: v_lshlrev_b16_e32 v10, 7, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v10, v2, v9 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v7
+; GFX950-NEXT: v_and_b32_e32 v7, 63, v7
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v9, v7, v12 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v7, v11, v7
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v7
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v8, v8, v9
+; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v9, 3, v8
+; GFX950-NEXT: v_bitop3_b16 v7, v10, v7, v9 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v1, v6 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_bitop3_b16 v2, v4, v1, s2 bitop3:0xec
+; GFX950-NEXT: v_lshl_or_b32 v1, v2, 16, v5
+; GFX950-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_v3f16:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v0, v0
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v2, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_and_b32_e32 v1, 0xffff, v0
+; GFX1310-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1310-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <3 x i8> @llvm.convert.to.arbitrary.fp.v3i8.v3f16(<3 x half> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
+ ret <3 x i8> %r
+}
+
+define <3 x i8> @to_bf8_v3f16(<3 x half> %x) {
+; GFX1250-TRUE16-LABEL: to_bf8_v3f16:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v2.h, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v2.l, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_bf8_v3f16:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f16_e64 v0, v0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f16_e64 v2, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
+; GFX1250-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX950-LABEL: to_bf8_v3f16:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v5, v0
+; GFX950-NEXT: v_sub_u16_e32 v6, -5, v5
+; GFX950-NEXT: v_frexp_mant_f16_e32 v4, v0
+; GFX950-NEXT: s_movk_i32 s2, 0x400
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x3ff
+; GFX950-NEXT: v_min_u16_e32 v6, 15, v6
+; GFX950-NEXT: v_bitop3_b16 v3, v4, s2, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v9, v6, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, v6, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v9, v3
+; GFX950-NEXT: v_lshlrev_b16_e64 v9, v9, 1
+; GFX950-NEXT: v_and_b32_e32 v10, 0x3ff, v4
+; GFX950-NEXT: v_add_u16_e32 v9, -1, v9
+; GFX950-NEXT: v_bitop3_b16 v9, v10, v9, s2 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
+; GFX950-NEXT: s_movk_i32 s3, 0x7c
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v3, v9, v8 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 7, v4
+; GFX950-NEXT: v_and_b32_e32 v4, 0x7f, v4
+; GFX950-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX950-NEXT: v_add_u16_e32 v3, v7, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, 8, v0
+; GFX950-NEXT: v_and_b32_e32 v8, 0x80, v7
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 4, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v8, v3, v6 bitop3:0xfe
+; GFX950-NEXT: v_mov_b32_e32 v3, 1
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
+; GFX950-NEXT: v_and_b32_sdwa v11, v10, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_movk_i32 s4, 0x204
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v9, v4, v11 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_sdwa v4, v10, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v4
+; GFX950-NEXT: s_movk_i32 s5, 0xff
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v5, v9
+; GFX950-NEXT: v_add_u16_e32 v5, 14, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v9, 2, v5
+; GFX950-NEXT: v_bitop3_b16 v9, v8, v4, v9 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v5
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 30, v5
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v4
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 30, v5
+; GFX950-NEXT: v_mov_b32_e32 v5, 0x80
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v4, v7, s3, v5 bitop3:0xec
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_sub_u16_e32 v10, -5, v9
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v4, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_min_u16_e32 v10, 15, v10
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; GFX950-NEXT: v_bitop3_b16 v8, v7, s2, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v13, v10, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, v10, v8
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, v13, v8
+; GFX950-NEXT: v_lshlrev_b16_e64 v13, v13, 1
+; GFX950-NEXT: v_cmp_class_f16_e64 vcc, v0, s4
+; GFX950-NEXT: v_and_b32_e32 v14, 0x3ff, v7
+; GFX950-NEXT: v_add_u16_e32 v13, -1, v13
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v4, vcc
+; GFX950-NEXT: v_mov_b32_e32 v4, 0x7e
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
+; GFX950-NEXT: v_bitop3_b16 v13, v14, v13, s2 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v4, v6, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v8, v8, v13, v12 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_and_b32_sdwa v12, v14, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
+; GFX950-NEXT: v_add_u16_e32 v8, v11, v8
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v8
+; GFX950-NEXT: v_lshrrev_b32_e32 v11, 31, v0
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 7, v11
+; GFX950-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 4, vcc
+; GFX950-NEXT: v_bitop3_b16 v8, v11, v8, v10 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, 7, v7
+; GFX950-NEXT: v_and_b32_e32 v7, 0x7f, v7
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v10, v7, v12 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_sdwa v7, v14, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v7
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v9, v9, v10
+; GFX950-NEXT: v_add_u16_e32 v9, 14, v9
+; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v10, 2, v9
+; GFX950-NEXT: v_bitop3_b16 v10, v11, v7, v10 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v9
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 30, v9
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v7
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 30, v9
+; GFX950-NEXT: v_or_b32_e32 v7, 0x7c, v11
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_mov_b32_e32 v9, 0
+; GFX950-NEXT: v_cndmask_b32_e32 v8, v8, v7, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v9 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v10, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
+; GFX950-NEXT: v_cmp_class_f16_sdwa s[0:1], v0, s4 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: v_sub_u16_e32 v11, -5, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v7, v8, v7, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v7, 8, v0
+; GFX950-NEXT: v_bitop3_b16 v0, v6, v7, s5 bitop3:0xec
+; GFX950-NEXT: v_frexp_mant_f16_e32 v6, v1
+; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
+; GFX950-NEXT: v_bitop3_b16 v8, v6, s2, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v8
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, v14, v8
+; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
+; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v6
+; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s2 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v8, v8, v14, v13 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: v_and_b32_sdwa v14, v15, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
+; GFX950-NEXT: v_add_u16_e32 v8, v12, v8
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v8
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, 8, v1
+; GFX950-NEXT: v_and_b32_e32 v13, 0x80, v12
+; GFX950-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 4, vcc
+; GFX950-NEXT: v_bitop3_b16 v8, v13, v8, v11 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v6
+; GFX950-NEXT: v_and_b32_e32 v6, 0x7f, v6
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: v_bitop3_b16 v5, v12, s3, v5 bitop3:0xec
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v11, v6, v14 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_sdwa v6, v15, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v10, v10, v11
+; GFX950-NEXT: v_add_u16_e32 v10, 14, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 2, v10
+; GFX950-NEXT: v_bitop3_b16 v11, v13, v6, v11 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 30, v10
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v6
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 30, v10
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v8, v5, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_sub_u16_e32 v10, -5, v8
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc
+; GFX950-NEXT: v_cmp_class_f16_e64 vcc, v1, s4
+; GFX950-NEXT: v_min_u16_e32 v10, 15, v10
+; GFX950-NEXT: v_sub_u16_e64 v13, v10, 1 clamp
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v2, v6, s2, v2 bitop3:0xec
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, v10, v2
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, v13, v2
+; GFX950-NEXT: v_lshlrev_b16_e64 v13, v13, 1
+; GFX950-NEXT: v_and_b32_e32 v14, 0x3ff, v6
+; GFX950-NEXT: v_add_u16_e32 v13, -1, v13
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v1, v1
+; GFX950-NEXT: v_bitop3_b16 v13, v14, v13, s2 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v4, v5, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: v_and_b32_sdwa v3, v14, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v13, v12 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX950-NEXT: v_add_u16_e32 v2, v11, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v2
+; GFX950-NEXT: v_lshrrev_b32_e32 v11, 31, v1
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 7, v11
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 4, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v11, v2, v10 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, 7, v6
+; GFX950-NEXT: v_and_b32_e32 v6, 0x7f, v6
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v10, v6, v3 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_sdwa v3, v14, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v6, v8, v6
+; GFX950-NEXT: v_add_u16_e32 v6, 14, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v8, 2, v6
+; GFX950-NEXT: v_bitop3_b16 v8, v11, v3, v8 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v6
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 30, v6
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v3
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 30, v6
+; GFX950-NEXT: v_or_b32_e32 v3, 0x7c, v11
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v1, v9 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v11, vcc
+; GFX950-NEXT: v_cmp_class_f16_sdwa s[0:1], v1, s4 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_sdwa v1, v4, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_bitop3_b16 v2, v5, v1, s5 bitop3:0xec
+; GFX950-NEXT: v_lshl_or_b32 v1, v2, 16, v7
+; GFX950-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1310-LABEL: to_bf8_v3f16:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_bf8_f16_e32 v0, v0
+; GFX1310-NEXT: v_cvt_pk_bf8_f16_e32 v2, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_and_b32_e32 v1, 0xffff, v0
+; GFX1310-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1310-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <3 x i8> @llvm.convert.to.arbitrary.fp.v3i8.v3f16(<3 x half> %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
+ ret <3 x i8> %r
+}
+
+define <4 x i8> @to_fp8_v4f16(<4 x half> %x) {
+; GFX1250-TRUE16-LABEL: to_fp8_v4f16:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v2.h, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v2.l, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX1250-TRUE16-NEXT: v_dual_lshlrev_b32 v0, 16, v1 :: v_dual_lshrrev_b32 v1, 8, v2
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_fp8_v4f16:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v0, v0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v2, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
+; GFX1250-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_dual_lshlrev_b32 v3, 16, v2 :: v_dual_lshrrev_b32 v1, 8, v1
+; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX950-LABEL: to_fp8_v4f16:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v5, v0
+; GFX950-NEXT: v_sub_u16_e32 v6, 2, v5
+; GFX950-NEXT: v_frexp_mant_f16_e32 v3, v0
+; GFX950-NEXT: s_movk_i32 s0, 0x400
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x3ff
+; GFX950-NEXT: v_min_u16_e32 v6, 15, v6
+; GFX950-NEXT: v_bitop3_b16 v4, v3, s0, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v9, v6, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, v6, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v4, v9, v4
+; GFX950-NEXT: v_lshlrev_b16_e64 v9, v9, 1
+; GFX950-NEXT: v_and_b32_e32 v10, 0x3ff, v3
+; GFX950-NEXT: v_add_u16_e32 v9, -1, v9
+; GFX950-NEXT: v_bitop3_b16 v9, v10, v9, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
+; GFX950-NEXT: s_movk_i32 s1, 0x80
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v4, v9, v8 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, 7, v10
+; GFX950-NEXT: v_and_b32_e32 v9, 1, v8
+; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX950-NEXT: v_add_u16_e32 v4, v7, v4
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
+; GFX950-NEXT: v_and_b32_sdwa v7, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_movk_i32 s2, 0xff
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v7, v4, v6 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, 6, v3
+; GFX950-NEXT: v_and_b32_e32 v3, 63, v3
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v6, v3, v9 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v3, v8, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v5, v6
+; GFX950-NEXT: v_add_u16_e32 v5, 6, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v6, 3, v5
+; GFX950-NEXT: v_bitop3_b16 v3, v7, v3, v6 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v5
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v6, v5, s0, v2 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
+; GFX950-NEXT: v_and_b32_e32 v12, 0x3ff, v5
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v7, vcc
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_sub_u16_e32 v8, 2, v7
+; GFX950-NEXT: v_min_u16_e32 v8, 15, v8
+; GFX950-NEXT: v_sub_u16_e64 v11, v8, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, v8, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, v11, v6
+; GFX950-NEXT: v_lshlrev_b16_e64 v11, v11, 1
+; GFX950-NEXT: v_add_u16_e32 v11, -1, v11
+; GFX950-NEXT: v_mov_b32_e32 v3, 0x7f
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
+; GFX950-NEXT: v_bitop3_b16 v11, v12, v11, s0 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v10, 1, v9
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v6, v11, v10 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, 7, v12
+; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX950-NEXT: v_add_u16_e32 v6, v9, v6
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
+; GFX950-NEXT: v_lshrrev_b32_e32 v9, 31, v0
+; GFX950-NEXT: v_lshlrev_b16_e32 v9, 7, v9
+; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v9, v6, v8 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, 6, v5
+; GFX950-NEXT: v_and_b32_e32 v5, 63, v5
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v8, v5, v11 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v5, v10, v5
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v7, v7, v8
+; GFX950-NEXT: v_add_u16_e32 v7, 6, v7
+; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v8, 3, v7
+; GFX950-NEXT: v_bitop3_b16 v5, v9, v5, v8 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v7
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v8, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; GFX950-NEXT: v_mov_b32_e32 v6, 0
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v6 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: v_sub_u16_e32 v9, 2, v8
+; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v5, 8, v0
+; GFX950-NEXT: v_bitop3_b16 v0, v4, v5, s2 bitop3:0xec
+; GFX950-NEXT: v_frexp_mant_f16_e32 v4, v1
+; GFX950-NEXT: v_bitop3_b16 v7, v4, s0, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v12, v9, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, v9, v7
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, v12, v7
+; GFX950-NEXT: v_lshlrev_b16_e64 v12, v12, 1
+; GFX950-NEXT: v_and_b32_e32 v13, 0x3ff, v4
+; GFX950-NEXT: v_add_u16_e32 v12, -1, v12
+; GFX950-NEXT: v_bitop3_b16 v12, v13, v12, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v7, v12, v11 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v13
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
+; GFX950-NEXT: v_add_u16_e32 v7, v10, v7
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v7
+; GFX950-NEXT: v_and_b32_sdwa v10, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v10, v7, v9 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v4
+; GFX950-NEXT: v_and_b32_e32 v4, 63, v4
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v9, v4, v12 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v4, v11, v4
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v8, v8, v9
+; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v9, 3, v8
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v4, v10, v4, v9 bitop3:0xfe
+; GFX950-NEXT: v_sub_u16_e32 v9, 2, v8
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1
+; GFX950-NEXT: v_bitop3_b16 v2, v7, s0, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v12, v9, 1 clamp
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, v9, v2
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, v12, v2
+; GFX950-NEXT: v_lshlrev_b16_e64 v12, v12, 1
+; GFX950-NEXT: v_and_b32_e32 v13, 0x3ff, v7
+; GFX950-NEXT: v_add_u16_e32 v12, -1, v12
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v1, v1
+; GFX950-NEXT: v_bitop3_b16 v12, v13, v12, s0 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v12, v11 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v13
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX950-NEXT: v_add_u16_e32 v2, v10, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
+; GFX950-NEXT: v_lshrrev_b32_e32 v10, 31, v1
+; GFX950-NEXT: v_lshlrev_b16_e32 v10, 7, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v10, v2, v9 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v7
+; GFX950-NEXT: v_and_b32_e32 v7, 63, v7
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v9, v7, v12 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v7, v11, v7
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v7
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v8, v8, v9
+; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v9, 3, v8
+; GFX950-NEXT: v_bitop3_b16 v7, v10, v7, v9 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v1, v6 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v1, 8, v1
+; GFX950-NEXT: v_bitop3_b16 v2, v4, v1, s2 bitop3:0xec
+; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX950-NEXT: v_lshl_or_b32 v1, v2, 16, v5
+; GFX950-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX950-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_v4f16:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v0, v0
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v2, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_and_b32_e32 v1, 0xffff, v0
+; GFX1310-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_dual_lshlrev_b32 v3, 16, v2 :: v_dual_lshrrev_b32 v1, 8, v1
+; GFX1310-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <4 x i8> @llvm.convert.to.arbitrary.fp.v4i8.v4f16(<4 x half> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
+ ret <4 x i8> %r
+}
+define <4 x i8> @to_bf8_v4f16(<4 x half> %x) {
+; GFX1250-TRUE16-LABEL: to_bf8_v4f16:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v2.h, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v2.l, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX1250-TRUE16-NEXT: v_dual_lshlrev_b32 v0, 16, v1 :: v_dual_lshrrev_b32 v1, 8, v2
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_bf8_v4f16:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f16_e64 v0, v0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f16_e64 v2, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
+; GFX1250-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_dual_lshlrev_b32 v3, 16, v2 :: v_dual_lshrrev_b32 v1, 8, v1
+; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX950-LABEL: to_bf8_v4f16:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v5, v0
+; GFX950-NEXT: v_sub_u16_e32 v6, -5, v5
+; GFX950-NEXT: v_frexp_mant_f16_e32 v4, v0
+; GFX950-NEXT: s_movk_i32 s2, 0x400
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x3ff
+; GFX950-NEXT: v_min_u16_e32 v6, 15, v6
+; GFX950-NEXT: v_bitop3_b16 v3, v4, s2, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v9, v6, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, v6, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v9, v3
+; GFX950-NEXT: v_lshlrev_b16_e64 v9, v9, 1
+; GFX950-NEXT: v_and_b32_e32 v10, 0x3ff, v4
+; GFX950-NEXT: v_add_u16_e32 v9, -1, v9
+; GFX950-NEXT: v_bitop3_b16 v9, v10, v9, s2 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
+; GFX950-NEXT: s_movk_i32 s3, 0x7c
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v3, v9, v8 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 7, v4
+; GFX950-NEXT: v_and_b32_e32 v4, 0x7f, v4
+; GFX950-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX950-NEXT: v_add_u16_e32 v3, v7, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, 8, v0
+; GFX950-NEXT: v_and_b32_e32 v8, 0x80, v7
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 4, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v8, v3, v6 bitop3:0xfe
+; GFX950-NEXT: v_mov_b32_e32 v3, 1
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
+; GFX950-NEXT: v_and_b32_sdwa v11, v10, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_movk_i32 s4, 0x204
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v9, v4, v11 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_sdwa v4, v10, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v4
+; GFX950-NEXT: s_movk_i32 s5, 0xff
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v5, v9
+; GFX950-NEXT: v_add_u16_e32 v5, 14, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v9, 2, v5
+; GFX950-NEXT: v_bitop3_b16 v9, v8, v4, v9 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v5
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 30, v5
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v4
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 30, v5
+; GFX950-NEXT: v_mov_b32_e32 v5, 0x80
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v4, v7, s3, v5 bitop3:0xec
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_sub_u16_e32 v10, -5, v9
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v4, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_min_u16_e32 v10, 15, v10
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; GFX950-NEXT: v_bitop3_b16 v8, v7, s2, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v13, v10, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, v10, v8
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, v13, v8
+; GFX950-NEXT: v_lshlrev_b16_e64 v13, v13, 1
+; GFX950-NEXT: v_cmp_class_f16_e64 vcc, v0, s4
+; GFX950-NEXT: v_and_b32_e32 v14, 0x3ff, v7
+; GFX950-NEXT: v_add_u16_e32 v13, -1, v13
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v4, vcc
+; GFX950-NEXT: v_mov_b32_e32 v4, 0x7e
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
+; GFX950-NEXT: v_bitop3_b16 v13, v14, v13, s2 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v4, v6, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v8, v8, v13, v12 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_and_b32_sdwa v12, v14, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
+; GFX950-NEXT: v_add_u16_e32 v8, v11, v8
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v8
+; GFX950-NEXT: v_lshrrev_b32_e32 v11, 31, v0
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 7, v11
+; GFX950-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 4, vcc
+; GFX950-NEXT: v_bitop3_b16 v8, v11, v8, v10 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, 7, v7
+; GFX950-NEXT: v_and_b32_e32 v7, 0x7f, v7
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v10, v7, v12 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_sdwa v7, v14, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v7
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v9, v9, v10
+; GFX950-NEXT: v_add_u16_e32 v9, 14, v9
+; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v10, 2, v9
+; GFX950-NEXT: v_bitop3_b16 v10, v11, v7, v10 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v9
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 30, v9
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v7
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 30, v9
+; GFX950-NEXT: v_or_b32_e32 v7, 0x7c, v11
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_mov_b32_e32 v9, 0
+; GFX950-NEXT: v_cndmask_b32_e32 v8, v8, v7, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v9 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v10, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
+; GFX950-NEXT: v_cmp_class_f16_sdwa s[0:1], v0, s4 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: v_sub_u16_e32 v11, -5, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v7, v8, v7, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v7, 8, v0
+; GFX950-NEXT: v_bitop3_b16 v0, v6, v7, s5 bitop3:0xec
+; GFX950-NEXT: v_frexp_mant_f16_e32 v6, v1
+; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
+; GFX950-NEXT: v_bitop3_b16 v8, v6, s2, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v8
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, v14, v8
+; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
+; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v6
+; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s2 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v8, v8, v14, v13 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: v_and_b32_sdwa v14, v15, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
+; GFX950-NEXT: v_add_u16_e32 v8, v12, v8
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v8
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, 8, v1
+; GFX950-NEXT: v_and_b32_e32 v13, 0x80, v12
+; GFX950-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 4, vcc
+; GFX950-NEXT: v_bitop3_b16 v8, v13, v8, v11 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v6
+; GFX950-NEXT: v_and_b32_e32 v6, 0x7f, v6
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: v_bitop3_b16 v5, v12, s3, v5 bitop3:0xec
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v11, v6, v14 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_sdwa v6, v15, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v10, v10, v11
+; GFX950-NEXT: v_add_u16_e32 v10, 14, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 2, v10
+; GFX950-NEXT: v_bitop3_b16 v11, v13, v6, v11 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 30, v10
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v6
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 30, v10
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v8, v5, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_sub_u16_e32 v10, -5, v8
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc
+; GFX950-NEXT: v_cmp_class_f16_e64 vcc, v1, s4
+; GFX950-NEXT: v_min_u16_e32 v10, 15, v10
+; GFX950-NEXT: v_sub_u16_e64 v13, v10, 1 clamp
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v2, v6, s2, v2 bitop3:0xec
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, v10, v2
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, v13, v2
+; GFX950-NEXT: v_lshlrev_b16_e64 v13, v13, 1
+; GFX950-NEXT: v_and_b32_e32 v14, 0x3ff, v6
+; GFX950-NEXT: v_add_u16_e32 v13, -1, v13
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v1, v1
+; GFX950-NEXT: v_bitop3_b16 v13, v14, v13, s2 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v4, v5, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: v_and_b32_sdwa v3, v14, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v13, v12 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX950-NEXT: v_add_u16_e32 v2, v11, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v2
+; GFX950-NEXT: v_lshrrev_b32_e32 v11, 31, v1
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 7, v11
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 4, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v11, v2, v10 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, 7, v6
+; GFX950-NEXT: v_and_b32_e32 v6, 0x7f, v6
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v10, v6, v3 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_sdwa v3, v14, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v6, v8, v6
+; GFX950-NEXT: v_add_u16_e32 v6, 14, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v8, 2, v6
+; GFX950-NEXT: v_bitop3_b16 v8, v11, v3, v8 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v6
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 30, v6
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v3
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 30, v6
+; GFX950-NEXT: v_or_b32_e32 v3, 0x7c, v11
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v1, v9 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v11, vcc
+; GFX950-NEXT: v_cmp_class_f16_sdwa s[0:1], v1, s4 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v1, 8, v1
+; GFX950-NEXT: v_bitop3_b16 v2, v5, v1, s5 bitop3:0xec
+; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX950-NEXT: v_lshl_or_b32 v1, v2, 16, v7
+; GFX950-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX950-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1310-LABEL: to_bf8_v4f16:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_bf8_f16_e32 v0, v0
+; GFX1310-NEXT: v_cvt_pk_bf8_f16_e32 v2, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_and_b32_e32 v1, 0xffff, v0
+; GFX1310-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_dual_lshlrev_b32 v3, 16, v2 :: v_dual_lshrrev_b32 v1, 8, v1
+; GFX1310-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <4 x i8> @llvm.convert.to.arbitrary.fp.v4i8.v4f16(<4 x half> %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
+ ret <4 x i8> %r
+}
+
+define i8 @to_fp8_f16_towardzero(half %x) {
+; GFX1250-TRUE16-LABEL: to_fp8_f16_towardzero:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.h, v0.l
+; GFX1250-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.h, v0.l
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0x400
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_and_b16 v1.l, 0x3ff, v0.h
+; GFX1250-TRUE16-NEXT: v_sub_nc_u16 v2.h, 2, v1.h
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.h, v0.h, v2.l, 0x3ff bitop3:0xec
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v1.l, 7, v1.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_min_u16 v2.l, v2.h, 15
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v1.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v0.h, v2.l, v0.h
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v2.l, 8, v0.l
+; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s0, 7, v0.h
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1250-TRUE16-NEXT: v_and_b16 v2.l, 0x80, v2.l
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, 0, vcc_lo
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.h, v1.h, v3.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, 0, s0
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v2.h, 0, 8, s0
+; GFX1250-TRUE16-NEXT: v_cmp_eq_f16_e64 s0, 0, v0.l
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.h, v1.h, 6
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.h, v2.l, v0.h, v2.h bitop3:0xfe
+; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v3.l, 3, v1.h
+; GFX1250-TRUE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v1.h
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v2.l, v1.l, v3.l bitop3:0xfe
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v0.h, vcc_lo
+; GFX1250-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.l, s0
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.h, vcc_lo
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_fp8_f16_towardzero:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_frexp_mant_f16_e32 v1, v0
+; GFX1250-FAKE16-NEXT: v_frexp_exp_i16_f16_e32 v3, v0
+; GFX1250-FAKE16-NEXT: s_movk_i32 s0, 0x400
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 0x3ff, v1
+; GFX1250-FAKE16-NEXT: v_sub_nc_u16 v4, 2, v3
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v1, v1, s0, 0x3ff bitop3:0xec
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v2, 7, v2
+; GFX1250-FAKE16-NEXT: v_min_u16 v4, v4, 15
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v2
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v1, v4, v1
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v4, 8, v0
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v1
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v4, 0x80, v4
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v3, v3, v5
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc_lo
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v3, v3, 6
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v1, v4, v1, v5 bitop3:0xfe
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 3, v3
+; GFX1250-FAKE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v3
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v2, v4, v2, v6 bitop3:0xfe
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v0
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7f, v1, vcc_lo
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX950-LABEL: to_fp8_f16_towardzero:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v3, v0
+; GFX950-NEXT: v_frexp_mant_f16_e32 v1, v0
+; GFX950-NEXT: s_movk_i32 s0, 0x400
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x3ff
+; GFX950-NEXT: v_sub_u16_e32 v4, 2, v3
+; GFX950-NEXT: v_bitop3_b16 v2, v1, s0, v2 bitop3:0xec
+; GFX950-NEXT: v_min_u16_e32 v4, 15, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, v4, v2
+; GFX950-NEXT: v_and_b32_e32 v1, 0x3ff, v1
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
+; GFX950-NEXT: s_movk_i32 s0, 0x80
+; GFX950-NEXT: v_lshrrev_b16_e32 v1, 7, v1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc
+; GFX950-NEXT: v_and_b32_sdwa v5, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v1
+; GFX950-NEXT: v_bitop3_b16 v2, v5, v2, v4 bitop3:0xfe
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v3, v3, v4
+; GFX950-NEXT: v_add_u16_e32 v3, 6, v3
+; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v4, 3, v3
+; GFX950-NEXT: v_bitop3_b16 v1, v5, v1, v4 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x7f
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_f16_towardzero:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_frexp_mant_f16_e32 v1, v0
+; GFX1310-NEXT: v_frexp_exp_i16_f16_e32 v3, v0
+; GFX1310-NEXT: s_movk_i32 s0, 0x400
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_and_b32_e32 v2, 0x3ff, v1
+; GFX1310-NEXT: v_sub_nc_u16 v4, 2, v3
+; GFX1310-NEXT: v_bitop3_b16 v1, v1, s0, 0x3ff bitop3:0xec
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_lshrrev_b16 v2, 7, v2
+; GFX1310-NEXT: v_min_u16 v4, v4, 15
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v2
+; GFX1310-NEXT: v_lshrrev_b16 v1, v4, v1
+; GFX1310-NEXT: v_lshrrev_b16 v4, 8, v0
+; GFX1310-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v1
+; GFX1310-NEXT: v_and_b32_e32 v4, 0x80, v4
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_add_nc_u16 v3, v3, v5
+; GFX1310-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
+; GFX1310-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc_lo
+; GFX1310-NEXT: v_add_nc_u16 v3, v3, 6
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_bitop3_b16 v1, v4, v1, v5 bitop3:0xfe
+; GFX1310-NEXT: v_lshlrev_b16 v6, 3, v3
+; GFX1310-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v3
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_bitop3_b16 v2, v4, v2, v6 bitop3:0xfe
+; GFX1310-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1310-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX1310-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v0
+; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0x7f, v1, vcc_lo
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call i8 @llvm.convert.to.arbitrary.fp.i8.f16(half %x, metadata !"Float8E4M3FN", metadata !"round.towardzero", i1 false)
+ ret i8 %r
+}
+
+define <2 x i8> @to_fp8_v2f16_saturate(<2 x half> %x) {
+; GFX1250-TRUE16-LABEL: to_fp8_v2f16_saturate:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.h, v0.l
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0x400
+; GFX1250-TRUE16-NEXT: v_frexp_mant_f16_e32 v2.l, v0.l
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v0
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v2.h, 8, v0.l
+; GFX1250-TRUE16-NEXT: v_sub_nc_u16 v3.l, 2, v1.h
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.h, v2.l, v1.l, 0x3ff bitop3:0xec
+; GFX1250-TRUE16-NEXT: v_and_b16 v4.l, 0x3ff, v2.l
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v5.l, 6, v2.l
+; GFX1250-TRUE16-NEXT: v_min_u16 v3.l, v3.l, 15
+; GFX1250-TRUE16-NEXT: v_and_b16 v2.l, v2.l, 63
+; GFX1250-TRUE16-NEXT: v_frexp_mant_f16_e32 v5.h, v12.l
+; GFX1250-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v6.l, v12.l
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v6.h, 7, v4.l
+; GFX1250-TRUE16-NEXT: v_sub_nc_u16 v7.l, v3.l, 1 clamp
+; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2.l
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v5.h, v1.l, 0x3ff bitop3:0xec
+; GFX1250-TRUE16-NEXT: v_sub_nc_u16 v2.l, 2, v6.l
+; GFX1250-TRUE16-NEXT: v_and_b16 v7.h, 0x3ff, v5.h
+; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v8.l, v7.l, 1
+; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v8.h, 6, v5.h
+; GFX1250-TRUE16-NEXT: v_and_b16 v5.h, v5.h, 63
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v9.l, v3.l, v3.h
+; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v3.l, v8.l, -1
+; GFX1250-TRUE16-NEXT: v_min_u16 v2.l, v2.l, 15
+; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
+; GFX1250-TRUE16-NEXT: v_and_b16 v8.l, v6.h, 1
+; GFX1250-TRUE16-NEXT: v_and_b16 v5.h, v9.l, 1
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.l, v4.l, v3.l, 0x400 bitop3:0xc8
+; GFX1250-TRUE16-NEXT: v_sub_nc_u16 v4.l, v2.l, 1 clamp
+; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v5.l, v5.l, v10.l, v8.l bitop3:0xe0
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v3.h, v7.l, v3.h
+; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.l
+; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v3.l, v4.l, 1
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v9.h, 7, v7.h
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v5.l, v6.h, v5.l
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v7.l, v2.l, v1.l
+; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v3.l, v3.l, -1
+; GFX1250-TRUE16-NEXT: v_and_b16 v10.l, v9.h, 1
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s0, 7, v5.l
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v1.l, v4.l, v1.l
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v8.l, v13.l
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.l, v7.h, v3.l, 0x400 bitop3:0xc8
+; GFX1250-TRUE16-NEXT: v_and_b16 v4.h, 0x80, v2.h
+; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.h, v3.h, v8.l, v5.h bitop3:0xe0
+; GFX1250-TRUE16-NEXT: v_and_b16 v5.h, v7.l, 1
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v13.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v3.h, 0, v3.h, vcc_lo
+; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.l, v8.h, v11.l, v10.l bitop3:0xe0
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.h, v1.h, v4.l
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.l, 0, s0
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v3.h, v9.l, v3.h
+; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v3.l, v9.h, v3.l
+; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2.l
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.h, v1.h, 6
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s1, 7, v3.h
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v8.l, v14.l
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s2, 7, v3.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v5.l, 3, v1.h
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v2.l, v3.h, 0, s1
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v1.l, v8.l, v5.h bitop3:0xe0
+; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 1, s2
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v3.h, 0, 8, s1
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s1, 6, v4.l
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s2
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, 0, v1.l, vcc_lo
+; GFX1250-TRUE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v1.h
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v2.l, v4.h, v2.l, v3.h bitop3:0xfe
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.h, v4.h, v4.l, v5.l bitop3:0xfe
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v5.l, v6.l, v8.l
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.l, v7.l, v1.l
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 31, v0
+; GFX1250-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 15, v1.h
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v2.l, v3.h, v2.l, vcc_lo
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v0.h, v5.l, 6
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s0, 7, v1.l
+; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v5.l, 7, v6.l
+; GFX1250-TRUE16-NEXT: s_and_b32 s3, s3, s1
+; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v5.h, 3, v0.h
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, 0, s0
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v4.l, 0, 8, s0
+; GFX1250-TRUE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v0.h
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s0, 6, v3.l
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.h, v5.l, v3.l, v5.h bitop3:0xfe
+; GFX1250-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 15, v0.h
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v5.l, v1.l, v4.l bitop3:0xfe
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s2, 15, v0.h
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0x7e
+; GFX1250-TRUE16-NEXT: s_and_b32 s0, s1, s0
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v1.l, vcc_lo
+; GFX1250-TRUE16-NEXT: v_or_b16 v1.l, 0x7e, v5.l
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 15, v1.h
+; GFX1250-TRUE16-NEXT: s_or_b32 s0, s2, s0
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.h, v2.h, v3.l, 0x80 bitop3:0xec
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v1.l, s0
+; GFX1250-TRUE16-NEXT: v_cmp_eq_f16_e64 s0, 0, v12.l
+; GFX1250-TRUE16-NEXT: s_or_b32 s1, vcc_lo, s3
+; GFX1250-TRUE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0.l
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v1.h, s1
+; GFX1250-TRUE16-NEXT: v_cmp_class_f16_e64 s1, v0.l, 0x204
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s0
+; GFX1250-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v12.l, 0x204
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v4.h, vcc_lo
+; GFX1250-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v12.l, v12.l
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v1.l, s0
+; GFX1250-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v0.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.h, s1
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7f, v0.h, vcc_lo
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7f, v1.l, s0
+; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v0.h
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, 0xff bitop3:0xec
+; GFX1250-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v0.h
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_fp8_v2f16_saturate:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_frexp_exp_i16_f16_e32 v2, v0
+; GFX1250-FAKE16-NEXT: v_frexp_mant_f16_e32 v1, v0
+; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX1250-FAKE16-NEXT: s_movk_i32 s0, 0x400
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v3, 8, v0
+; GFX1250-FAKE16-NEXT: v_sub_nc_u16 v6, 2, v2
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v5, v1, s0, 0x3ff bitop3:0xec
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v7, 0x3ff, v1
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v8, 6, v1
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v1, 63, v1
+; GFX1250-FAKE16-NEXT: v_min_u16 v6, v6, 15
+; GFX1250-FAKE16-NEXT: v_frexp_mant_f16_e32 v9, v4
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v11, 7, v7
+; GFX1250-FAKE16-NEXT: v_frexp_exp_i16_f16_e32 v10, v4
+; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v1
+; GFX1250-FAKE16-NEXT: v_sub_nc_u16 v13, v6, 1 clamp
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v12, v9, s0, 0x3ff bitop3:0xec
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v15, 0x3ff, v9
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v16, 6, v9
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v9, 63, v9
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v17, v13, 1
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v18, v6, v5
+; GFX1250-FAKE16-NEXT: v_sub_nc_u16 v14, 2, v10
+; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v17, v17, -1
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v5, v13, v5
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v21, 1, v18
+; GFX1250-FAKE16-NEXT: v_min_u16 v14, v14, 15
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v7, v7, v17, 0x400 bitop3:0xc8
+; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e64 s0, 0, v6
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v20, 7, v15
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v13, v14, v12
+; GFX1250-FAKE16-NEXT: s_movk_i32 s4, 0x7e
+; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v5, v5, v7, v21 bitop3:0xe0
+; GFX1250-FAKE16-NEXT: v_dual_cndmask_b32 v5, 0, v5, s0 :: v_dual_bitop2_b32 v19, 1, v11 bitop3:0x40
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v1, v8, v1, v19 bitop3:0xe0
+; GFX1250-FAKE16-NEXT: v_sub_nc_u16 v8, v14, 1 clamp
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v5, v18, v5
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v1, v11, v1
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v19, v8, 1
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v11, 1, v13
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v8, v8, v12
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v1
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v7, v19, -1
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v6, v15, v7, 0x400 bitop3:0xc8
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v2, v2, v7
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v7, 0x80, v3
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v3, v3, s4, 0x80 bitop3:0xec
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v2, v2, 6
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v6, v8, v6, v11 bitop3:0xe0
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v14
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v12, 3, v2
+; GFX1250-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 15, v2
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v5, v7, v5, v8 bitop3:0xfe
+; GFX1250-FAKE16-NEXT: v_dual_cndmask_b32 v6, 0, v6, vcc_lo :: v_dual_bitop2_b32 v17, 1, v20 bitop3:0x40
+; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 6, v1
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v9, v16, v9, v17 bitop3:0xe0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v6, v13, v6
+; GFX1250-FAKE16-NEXT: s_and_b32 s3, s1, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 15, v2
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v9, v20, v9
+; GFX1250-FAKE16-NEXT: s_or_b32 vcc_lo, vcc_lo, s3
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e64 s0, 7, v9
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v9, v9, 0, s0
+; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e64 s0, 7, v6
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v8, v10, v11
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v10, v7, v1, v12 bitop3:0xfe
+; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 31, v0
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v6, v6, 0, s0
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v11, 0, 8, s0
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v8, v8, 6
+; GFX1250-FAKE16-NEXT: v_cmp_gt_i16_e64 s0, 1, v2
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v1, 7, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v12, 3, v8
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v5, v10, v5, s0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v6, v1, v6, v11 bitop3:0xfe
+; GFX1250-FAKE16-NEXT: v_cmp_gt_i16_e64 s2, 1, v8
+; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e64 s0, 6, v9
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v10, v1, v9, v12 bitop3:0xfe
+; GFX1250-FAKE16-NEXT: v_cmp_eq_u16_e64 s1, 15, v8
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v3, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v2, v10, v6, s2
+; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e64 s2, 15, v8
+; GFX1250-FAKE16-NEXT: v_or_b32_e32 v6, 0x7e, v1
+; GFX1250-FAKE16-NEXT: s_and_b32 s0, s1, s0
+; GFX1250-FAKE16-NEXT: s_or_b32 s0, s2, s0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 0x204
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 0x204
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v4
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7f, v1, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7f, v2, vcc_lo
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v1
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v2, 0xff bitop3:0xec
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX950-LABEL: to_fp8_v2f16_saturate:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v4, v0
+; GFX950-NEXT: v_sub_u16_e32 v5, 2, v4
+; GFX950-NEXT: v_frexp_mant_f16_e32 v1, v0
+; GFX950-NEXT: s_movk_i32 s2, 0x400
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x3ff
+; GFX950-NEXT: v_min_u16_e32 v5, 15, v5
+; GFX950-NEXT: v_bitop3_b16 v3, v1, s2, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v8, v5, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, v5, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v8, v3
+; GFX950-NEXT: v_lshlrev_b16_e64 v8, v8, 1
+; GFX950-NEXT: v_and_b32_e32 v9, 0x3ff, v1
+; GFX950-NEXT: v_add_u16_e32 v8, -1, v8
+; GFX950-NEXT: v_bitop3_b16 v8, v9, v8, s2 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
+; GFX950-NEXT: v_and_b32_e32 v7, 1, v6
+; GFX950-NEXT: s_movk_i32 s3, 0x7e
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v3, v8, v7 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, 7, v9
+; GFX950-NEXT: v_and_b32_e32 v9, 1, v8
+; GFX950-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX950-NEXT: v_add_u16_e32 v3, v6, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, 8, v0
+; GFX950-NEXT: v_and_b32_e32 v7, 0x80, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v7, v3, v5 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, 6, v1
+; GFX950-NEXT: v_and_b32_e32 v1, 63, v1
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v5, v1, v9 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v1, v8, v1
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v4, v4, v5
+; GFX950-NEXT: v_add_u16_e32 v4, 6, v4
+; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v5, 3, v4
+; GFX950-NEXT: v_bitop3_b16 v5, v7, v1, v5 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v4
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 15, v4
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 6, v1
+; GFX950-NEXT: v_mov_b32_e32 v1, 0x80
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 15, v4
+; GFX950-NEXT: v_bitop3_b16 v1, v6, s3, v1 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e32 v6, 2, v5
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_min_u16_e32 v6, 15, v6
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
+; GFX950-NEXT: v_bitop3_b16 v2, v4, s2, v2 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v9, v6, 1 clamp
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX950-NEXT: s_movk_i32 s3, 0x204
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, v6, v2
+; GFX950-NEXT: v_lshrrev_b16_e32 v2, v9, v2
+; GFX950-NEXT: v_lshlrev_b16_e64 v9, v9, 1
+; GFX950-NEXT: v_cmp_class_f16_e64 vcc, v0, s3
+; GFX950-NEXT: v_and_b32_e32 v10, 0x3ff, v4
+; GFX950-NEXT: v_add_u16_e32 v9, -1, v9
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX950-NEXT: v_mov_b32_e32 v3, 0x7f
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
+; GFX950-NEXT: v_bitop3_b16 v9, v10, v9, s2 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v9, v8 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, 7, v10
+; GFX950-NEXT: v_and_b32_e32 v9, 1, v8
+; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX950-NEXT: v_add_u16_e32 v2, v7, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
+; GFX950-NEXT: v_lshrrev_b32_e32 v7, 31, v0
+; GFX950-NEXT: v_lshlrev_b16_e32 v7, 7, v7
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v7, v2, v6 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, 6, v4
+; GFX950-NEXT: v_and_b32_e32 v4, 63, v4
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v6, v4, v9 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v4, v8, v4
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v5, v6
+; GFX950-NEXT: v_add_u16_e32 v5, 6, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v6, 3, v5
+; GFX950-NEXT: v_bitop3_b16 v6, v7, v4, v6 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v5
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 15, v5
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 6, v4
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 15, v5
+; GFX950-NEXT: v_or_b32_e32 v4, 0x7e, v7
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_mov_b32_e32 v5, 0
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v5 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
+; GFX950-NEXT: v_cmp_class_f16_sdwa s[0:1], v0, s3 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v0, 8, v2
+; GFX950-NEXT: s_movk_i32 s0, 0xff
+; GFX950-NEXT: v_bitop3_b16 v0, v1, v0, s0 bitop3:0xec
+; GFX950-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_v2f16_saturate:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_frexp_exp_i16_f16_e32 v2, v0
+; GFX1310-NEXT: v_frexp_mant_f16_e32 v1, v0
+; GFX1310-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX1310-NEXT: s_movk_i32 s0, 0x400
+; GFX1310-NEXT: v_lshrrev_b16 v3, 8, v0
+; GFX1310-NEXT: v_sub_nc_u16 v6, 2, v2
+; GFX1310-NEXT: v_bitop3_b16 v5, v1, s0, 0x3ff bitop3:0xec
+; GFX1310-NEXT: v_and_b32_e32 v7, 0x3ff, v1
+; GFX1310-NEXT: v_lshrrev_b16 v8, 6, v1
+; GFX1310-NEXT: v_and_b32_e32 v1, 63, v1
+; GFX1310-NEXT: v_min_u16 v6, v6, 15
+; GFX1310-NEXT: v_frexp_mant_f16_e32 v9, v4
+; GFX1310-NEXT: v_lshrrev_b16 v11, 7, v7
+; GFX1310-NEXT: v_frexp_exp_i16_f16_e32 v10, v4
+; GFX1310-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v1
+; GFX1310-NEXT: v_sub_nc_u16 v13, v6, 1 clamp
+; GFX1310-NEXT: v_bitop3_b16 v12, v9, s0, 0x3ff bitop3:0xec
+; GFX1310-NEXT: v_and_b32_e32 v15, 0x3ff, v9
+; GFX1310-NEXT: v_lshrrev_b16 v16, 6, v9
+; GFX1310-NEXT: v_and_b32_e32 v9, 63, v9
+; GFX1310-NEXT: v_lshlrev_b16 v17, v13, 1
+; GFX1310-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1310-NEXT: v_lshrrev_b16 v18, v6, v5
+; GFX1310-NEXT: v_sub_nc_u16 v14, 2, v10
+; GFX1310-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9
+; GFX1310-NEXT: v_add_nc_u16 v17, v17, -1
+; GFX1310-NEXT: v_lshrrev_b16 v5, v13, v5
+; GFX1310-NEXT: v_and_b32_e32 v21, 1, v18
+; GFX1310-NEXT: v_min_u16 v14, v14, 15
+; GFX1310-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1310-NEXT: v_bitop3_b16 v7, v7, v17, 0x400 bitop3:0xc8
+; GFX1310-NEXT: v_cmp_ne_u16_e64 s0, 0, v6
+; GFX1310-NEXT: v_lshrrev_b16 v20, 7, v15
+; GFX1310-NEXT: v_lshrrev_b16 v13, v14, v12
+; GFX1310-NEXT: s_movk_i32 s4, 0x7e
+; GFX1310-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7
+; GFX1310-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_bitop3_b16 v5, v5, v7, v21 bitop3:0xe0
+; GFX1310-NEXT: v_dual_cndmask_b32 v5, 0, v5, s0 :: v_dual_bitop2_b32 v19, 1, v11 bitop3:0x40
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_bitop3_b16 v1, v8, v1, v19 bitop3:0xe0
+; GFX1310-NEXT: v_sub_nc_u16 v8, v14, 1 clamp
+; GFX1310-NEXT: v_add_nc_u16 v5, v18, v5
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_add_nc_u16 v1, v11, v1
+; GFX1310-NEXT: v_lshlrev_b16 v19, v8, 1
+; GFX1310-NEXT: v_and_b32_e32 v11, 1, v13
+; GFX1310-NEXT: v_lshrrev_b16 v8, v8, v12
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v1
+; GFX1310-NEXT: v_add_nc_u16 v7, v19, -1
+; GFX1310-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_bitop3_b16 v6, v15, v7, 0x400 bitop3:0xc8
+; GFX1310-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1310-NEXT: v_add_nc_u16 v2, v2, v7
+; GFX1310-NEXT: v_and_b32_e32 v7, 0x80, v3
+; GFX1310-NEXT: v_bitop3_b16 v3, v3, s4, 0x80 bitop3:0xec
+; GFX1310-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5
+; GFX1310-NEXT: v_add_nc_u16 v2, v2, 6
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1310-NEXT: v_bitop3_b16 v6, v8, v6, v11 bitop3:0xe0
+; GFX1310-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
+; GFX1310-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc_lo
+; GFX1310-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v14
+; GFX1310-NEXT: v_lshlrev_b16 v12, 3, v2
+; GFX1310-NEXT: v_cmp_eq_u16_e64 s1, 15, v2
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_bitop3_b16 v5, v7, v5, v8 bitop3:0xfe
+; GFX1310-NEXT: v_dual_cndmask_b32 v6, 0, v6, vcc_lo :: v_dual_bitop2_b32 v17, 1, v20 bitop3:0x40
+; GFX1310-NEXT: v_cmp_lt_i16_e32 vcc_lo, 6, v1
+; GFX1310-NEXT: v_bitop3_b16 v9, v16, v9, v17 bitop3:0xe0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_add_nc_u16 v6, v13, v6
+; GFX1310-NEXT: s_and_b32 s3, s1, vcc_lo
+; GFX1310-NEXT: v_cmp_lt_i16_e32 vcc_lo, 15, v2
+; GFX1310-NEXT: v_add_nc_u16 v9, v20, v9
+; GFX1310-NEXT: s_or_b32 vcc_lo, vcc_lo, s3
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_cmp_lt_i16_e64 s0, 7, v9
+; GFX1310-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
+; GFX1310-NEXT: v_cndmask_b32_e64 v9, v9, 0, s0
+; GFX1310-NEXT: v_cmp_lt_i16_e64 s0, 7, v6
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_add_nc_u16 v8, v10, v11
+; GFX1310-NEXT: v_bitop3_b16 v10, v7, v1, v12 bitop3:0xfe
+; GFX1310-NEXT: v_lshrrev_b32_e32 v1, 31, v0
+; GFX1310-NEXT: v_cndmask_b32_e64 v6, v6, 0, s0
+; GFX1310-NEXT: v_cndmask_b32_e64 v11, 0, 8, s0
+; GFX1310-NEXT: v_add_nc_u16 v8, v8, 6
+; GFX1310-NEXT: v_cmp_gt_i16_e64 s0, 1, v2
+; GFX1310-NEXT: v_lshlrev_b16 v1, 7, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_lshlrev_b16 v12, 3, v8
+; GFX1310-NEXT: v_cndmask_b32_e64 v5, v10, v5, s0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1310-NEXT: v_bitop3_b16 v6, v1, v6, v11 bitop3:0xfe
+; GFX1310-NEXT: v_cmp_gt_i16_e64 s2, 1, v8
+; GFX1310-NEXT: v_cmp_lt_i16_e64 s0, 6, v9
+; GFX1310-NEXT: v_bitop3_b16 v10, v1, v9, v12 bitop3:0xfe
+; GFX1310-NEXT: v_cmp_eq_u16_e64 s1, 15, v8
+; GFX1310-NEXT: v_cndmask_b32_e32 v5, v5, v3, vcc_lo
+; GFX1310-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1310-NEXT: v_cndmask_b32_e64 v2, v10, v6, s2
+; GFX1310-NEXT: v_cmp_lt_i16_e64 s2, 15, v8
+; GFX1310-NEXT: v_or_b32_e32 v6, 0x7e, v1
+; GFX1310-NEXT: s_and_b32 s0, s1, s0
+; GFX1310-NEXT: s_or_b32 s0, s2, s0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1310-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1310-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0
+; GFX1310-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc_lo
+; GFX1310-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 0x204
+; GFX1310-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX1310-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 0x204
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX1310-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v4
+; GFX1310-NEXT: v_cndmask_b32_e32 v1, 0x7f, v1, vcc_lo
+; GFX1310-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0x7f, v2, vcc_lo
+; GFX1310-NEXT: v_lshlrev_b16 v2, 8, v1
+; GFX1310-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1310-NEXT: v_bitop3_b16 v0, v0, v2, 0xff bitop3:0xec
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <2 x i8> @llvm.convert.to.arbitrary.fp.v2i8.v2f16(<2 x half> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 true)
+ ret <2 x i8> %r
+}
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-fnuz.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-fnuz.ll
new file mode 100644
index 0000000000000..e97e1d2a8dd80
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-fnuz.ll
@@ -0,0 +1,134 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=amdgpu9.42-amd-amdhsa | FileCheck -check-prefix=GFX942 %s
+
+; gfx942 has fp8 conversion instructions, but for the FNUZ formats rather than
+; OCP, so an OCP conversion must not select them and uses the generic expansion
+; instead. The subtargets with the OCP formats are covered by
+; float-to-arbitrary-fp-fp8-hw.ll.
+
+define i8 @to_fp8_f32(float %x) {
+; GFX942-LABEL: to_fp8_f32:
+; GFX942: ; %bb.0:
+; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
+; GFX942-NEXT: v_frexp_mant_f32_e32 v1, v0
+; GFX942-NEXT: v_sub_u32_e32 v4, 15, v3
+; GFX942-NEXT: v_and_b32_e32 v2, 0x7fffff, v1
+; GFX942-NEXT: v_min_u32_e32 v4, 31, v4
+; GFX942-NEXT: v_or_b32_e32 v2, 0x800000, v2
+; GFX942-NEXT: v_sub_u32_e64 v6, v4, 1 clamp
+; GFX942-NEXT: v_bfe_u32 v7, v2, 0, v6
+; GFX942-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
+; GFX942-NEXT: v_lshrrev_b32_e32 v5, v4, v2
+; GFX942-NEXT: v_lshrrev_b32_e32 v2, v6, v2
+; GFX942-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX942-NEXT: v_and_or_b32 v7, v5, 1, v7
+; GFX942-NEXT: v_and_b32_e32 v2, v2, v7
+; GFX942-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX942-NEXT: s_movk_i32 s0, 0x80
+; GFX942-NEXT: v_bfe_u32 v6, v1, 20, 3
+; GFX942-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX942-NEXT: v_add_u32_e32 v2, v5, v2
+; GFX942-NEXT: v_cmp_lt_i32_e32 vcc, 7, v2
+; GFX942-NEXT: v_and_b32_sdwa v5, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX942-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc
+; GFX942-NEXT: v_or3_b32 v2, v5, v4, v2
+; GFX942-NEXT: v_and_b32_e32 v4, 0x7ffff, v1
+; GFX942-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX942-NEXT: v_lshrrev_b32_e32 v1, 19, v1
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX942-NEXT: v_and_or_b32 v4, v6, 1, v4
+; GFX942-NEXT: v_and_b32_e32 v1, v1, v4
+; GFX942-NEXT: v_add_u32_e32 v1, v6, v1
+; GFX942-NEXT: v_cmp_lt_i32_e32 vcc, 7, v1
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX942-NEXT: v_addc_co_u32_e32 v3, vcc, 6, v3, vcc
+; GFX942-NEXT: v_lshlrev_b32_e32 v4, 3, v3
+; GFX942-NEXT: v_or3_b32 v1, v5, v4, v1
+; GFX942-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX942-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0x7f
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX942-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX942-NEXT: s_setpc_b64 s[30:31]
+ %r = call i8 @llvm.convert.to.arbitrary.fp.i8.f32(float %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
+ ret i8 %r
+}
+
+define i8 @to_bf8_f32(float %x) {
+; GFX942-LABEL: to_bf8_f32:
+; GFX942: ; %bb.0:
+; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
+; GFX942-NEXT: v_frexp_mant_f32_e32 v1, v0
+; GFX942-NEXT: v_sub_u32_e32 v4, 8, v3
+; GFX942-NEXT: v_and_b32_e32 v2, 0x7fffff, v1
+; GFX942-NEXT: v_min_u32_e32 v4, 31, v4
+; GFX942-NEXT: v_or_b32_e32 v2, 0x800000, v2
+; GFX942-NEXT: v_sub_u32_e64 v6, v4, 1 clamp
+; GFX942-NEXT: v_bfe_u32 v7, v2, 0, v6
+; GFX942-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
+; GFX942-NEXT: v_lshrrev_b32_e32 v5, v4, v2
+; GFX942-NEXT: v_lshrrev_b32_e32 v2, v6, v2
+; GFX942-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX942-NEXT: v_and_or_b32 v7, v5, 1, v7
+; GFX942-NEXT: v_and_b32_e32 v2, v2, v7
+; GFX942-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX942-NEXT: s_movk_i32 s0, 0x80
+; GFX942-NEXT: v_bfe_u32 v6, v1, 21, 2
+; GFX942-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX942-NEXT: v_add_u32_e32 v2, v5, v2
+; GFX942-NEXT: v_cmp_lt_i32_e32 vcc, 3, v2
+; GFX942-NEXT: v_and_b32_sdwa v5, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX942-NEXT: v_cndmask_b32_e64 v4, 0, 4, vcc
+; GFX942-NEXT: v_or3_b32 v2, v5, v4, v2
+; GFX942-NEXT: v_and_b32_e32 v4, 0xfffff, v1
+; GFX942-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX942-NEXT: v_lshrrev_b32_e32 v1, 20, v1
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX942-NEXT: v_and_or_b32 v4, v6, 1, v4
+; GFX942-NEXT: v_and_b32_e32 v1, v1, v4
+; GFX942-NEXT: v_add_u32_e32 v1, v6, v1
+; GFX942-NEXT: v_cmp_lt_i32_e32 vcc, 3, v1
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX942-NEXT: v_addc_co_u32_e32 v3, vcc, 14, v3, vcc
+; GFX942-NEXT: v_lshlrev_b32_e32 v4, 2, v3
+; GFX942-NEXT: v_or3_b32 v4, v5, v4, v1
+; GFX942-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
+; GFX942-NEXT: v_cmp_eq_u32_e64 s[0:1], 30, v3
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX942-NEXT: v_cmp_lt_i32_e32 vcc, 3, v1
+; GFX942-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX942-NEXT: v_cmp_lt_i32_e32 vcc, 30, v3
+; GFX942-NEXT: v_or_b32_e32 v1, 0x7c, v5
+; GFX942-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX942-NEXT: v_cndmask_b32_e32 v2, v2, v1, vcc
+; GFX942-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
+; GFX942-NEXT: s_movk_i32 s0, 0x204
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX942-NEXT: v_cmp_class_f32_e64 vcc, v0, s0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX942-NEXT: v_mov_b32_e32 v2, 0x7e
+; GFX942-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX942-NEXT: s_setpc_b64 s[30:31]
+ %r = call i8 @llvm.convert.to.arbitrary.fp.i8.f32(float %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
+ ret i8 %r
+}
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
new file mode 100644
index 0000000000000..a098aff6afd72
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
@@ -0,0 +1,1896 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=amdgpu9.50-amd-amdhsa | FileCheck -check-prefix=GFX950 %s
+; RUN: llc < %s -mtriple=amdgpu12.00-amd-amdhsa | FileCheck -check-prefix=GFX1200 %s
+; RUN: llc < %s -mtriple=amdgpu12.50-amd-amdhsa -mattr=+real-true16 | FileCheck -check-prefixes=GFX1250,GFX1250-TRUE16 %s
+; RUN: llc < %s -mtriple=amdgpu12.50-amd-amdhsa -mattr=-real-true16 | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
+; RUN: llc < %s -mtriple=amdgpu13.10-amd-amdhsa | FileCheck -check-prefix=GFX1310 %s
+
+; llvm.convert.to.arbitrary.fp to OCP FP8 E4M3FN and BF8 E5M2 from f32, lowered
+; to the packed v_cvt_pk_{fp8,bf8}_f32 HW instructions. The FNUZ subtargets are
+; covered by float-to-arbitrary-fp-fp8-fnuz.ll.
+
+define i8 @to_fp8_f32(float %x) {
+; GFX950-LABEL: to_fp8_f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_fp8_f32:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v0
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: to_fp8_f32:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v0
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_fp8_f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_f32:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call i8 @llvm.convert.to.arbitrary.fp.i8.f32(float %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
+ ret i8 %r
+}
+
+define i8 @to_bf8_f32(float %x) {
+; GFX950-LABEL: to_bf8_f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cvt_pk_bf8_f32 v0, v0, v0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_bf8_f32:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v0
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: to_bf8_f32:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v0
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_bf8_f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v0, v0, v0
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_bf8_f32:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_bf8_f32 v0, v0, v0
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call i8 @llvm.convert.to.arbitrary.fp.i8.f32(float %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
+ ret i8 %r
+}
+
+define <2 x i8> @to_fp8_v2f32(<2 x float> %x) {
+; GFX950-LABEL: to_fp8_v2f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v0, v0, v1
+; GFX950-NEXT: v_lshrrev_b16_e32 v1, 8, v0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_fp8_v2f32:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT: v_lshrrev_b16 v1.l, 8, v0.l
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: to_fp8_v2f32:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v1
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v1.l, 8, v0.l
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_fp8_v2f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v0, v0, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v1, 8, v0
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_v2f32:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v0, v0, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1310-NEXT: v_lshrrev_b16 v1, 8, v0
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <2 x i8> @llvm.convert.to.arbitrary.fp.v2i8.v2f32(<2 x float> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
+ ret <2 x i8> %r
+}
+
+define <2 x i8> @to_bf8_v2f32(<2 x float> %x) {
+; GFX950-LABEL: to_bf8_v2f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cvt_pk_bf8_f32 v0, v0, v1
+; GFX950-NEXT: v_lshrrev_b16_e32 v1, 8, v0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_bf8_v2f32:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT: v_lshrrev_b16 v1.l, 8, v0.l
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: to_bf8_v2f32:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v1
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v1.l, 8, v0.l
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_bf8_v2f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v0, v0, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v1, 8, v0
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_bf8_v2f32:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_bf8_f32 v0, v0, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1310-NEXT: v_lshrrev_b16 v1, 8, v0
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <2 x i8> @llvm.convert.to.arbitrary.fp.v2i8.v2f32(<2 x float> %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
+ ret <2 x i8> %r
+}
+
+define <3 x i8> @to_fp8_v3f32(<3 x float> %x) {
+; GFX950-LABEL: to_fp8_v3f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v1, v1, v1
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v2, v2, v2
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_fp8_v3f32:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v0
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v1.l, v1, v1
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v2.l, v2, v2
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: to_fp8_v3f32:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v1.l, v1, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v2.l, v2, v2
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_fp8_v3f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v1, v1, v1
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v2, v2, v2
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_v3f32:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v1, v1, v1
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v2, v2, v2
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <3 x i8> @llvm.convert.to.arbitrary.fp.v3i8.v3f32(<3 x float> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
+ ret <3 x i8> %r
+}
+
+define <3 x i8> @to_bf8_v3f32(<3 x float> %x) {
+; GFX950-LABEL: to_bf8_v3f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cvt_pk_bf8_f32 v0, v0, v0
+; GFX950-NEXT: v_cvt_pk_bf8_f32 v1, v1, v1
+; GFX950-NEXT: v_cvt_pk_bf8_f32 v2, v2, v2
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_bf8_v3f32:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v0
+; GFX1200-NEXT: v_cvt_pk_bf8_f32 v1.l, v1, v1
+; GFX1200-NEXT: v_cvt_pk_bf8_f32 v2.l, v2, v2
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: to_bf8_v3f32:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v1.l, v1, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v2.l, v2, v2
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_bf8_v3f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v0, v0, v0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v1, v1, v1
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v2, v2, v2
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_bf8_v3f32:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_bf8_f32 v0, v0, v0
+; GFX1310-NEXT: v_cvt_pk_bf8_f32 v1, v1, v1
+; GFX1310-NEXT: v_cvt_pk_bf8_f32 v2, v2, v2
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <3 x i8> @llvm.convert.to.arbitrary.fp.v3i8.v3f32(<3 x float> %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
+ ret <3 x i8> %r
+}
+
+define <4 x i8> @to_fp8_v4f32(<4 x float> %x) {
+; GFX950-LABEL: to_fp8_v4f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v2, v2, v3
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v0, v0, v1
+; GFX950-NEXT: s_mov_b32 s0, 0xff00
+; GFX950-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX950-NEXT: v_and_or_b32 v1, v0, s0, v1
+; GFX950-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX950-NEXT: v_bfe_u32 v3, v2, 8, 8
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_fp8_v4f32:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v2.l, v2, v3
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX1200-NEXT: v_bfe_u32 v3, v2, 8, 8
+; GFX1200-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: to_fp8_v4f32:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v2.l, v2, v3
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v1
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX1250-TRUE16-NEXT: v_bfe_u32 v3, v2, 8, 8
+; GFX1250-TRUE16-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_fp8_v4f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v2, v2, v3
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v0, v0, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX1250-FAKE16-NEXT: v_bfe_u32 v3, v2, 8, 8
+; GFX1250-FAKE16-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_v4f32:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v2, v2, v3
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v0, v0, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX1310-NEXT: v_bfe_u32 v3, v2, 8, 8
+; GFX1310-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1310-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <4 x i8> @llvm.convert.to.arbitrary.fp.v4i8.v4f32(<4 x float> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
+ ret <4 x i8> %r
+}
+
+define <4 x i8> @to_bf8_v4f32(<4 x float> %x) {
+; GFX950-LABEL: to_bf8_v4f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cvt_pk_bf8_f32 v2, v2, v3
+; GFX950-NEXT: v_cvt_pk_bf8_f32 v0, v0, v1
+; GFX950-NEXT: s_mov_b32 s0, 0xff00
+; GFX950-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX950-NEXT: v_and_or_b32 v1, v0, s0, v1
+; GFX950-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX950-NEXT: v_bfe_u32 v3, v2, 8, 8
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_bf8_v4f32:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_cvt_pk_bf8_f32 v2.l, v2, v3
+; GFX1200-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX1200-NEXT: v_bfe_u32 v3, v2, 8, 8
+; GFX1200-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: to_bf8_v4f32:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v2.l, v2, v3
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v1
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX1250-TRUE16-NEXT: v_bfe_u32 v3, v2, 8, 8
+; GFX1250-TRUE16-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_bf8_v4f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v2, v2, v3
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v0, v0, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX1250-FAKE16-NEXT: v_bfe_u32 v3, v2, 8, 8
+; GFX1250-FAKE16-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_bf8_v4f32:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_bf8_f32 v2, v2, v3
+; GFX1310-NEXT: v_cvt_pk_bf8_f32 v0, v0, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX1310-NEXT: v_bfe_u32 v3, v2, 8, 8
+; GFX1310-NEXT: v_and_or_b32 v1, 0xff00, v0, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1310-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <4 x i8> @llvm.convert.to.arbitrary.fp.v4i8.v4f32(<4 x float> %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
+ ret <4 x i8> %r
+}
+
+; Saturation is not implemented by the HW conversion, so it uses the generic
+; expansion.
+define i8 @to_fp8_f32_saturate(float %x) {
+; GFX950-LABEL: to_fp8_f32_saturate:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX950-NEXT: v_sub_u32_e32 v2, 15, v1
+; GFX950-NEXT: v_frexp_mant_f32_e32 v3, v0
+; GFX950-NEXT: v_min_u32_e32 v2, 31, v2
+; GFX950-NEXT: v_and_b32_e32 v4, 0x7fffff, v3
+; GFX950-NEXT: v_or_b32_e32 v5, 0x800000, v4
+; GFX950-NEXT: v_sub_u32_e64 v7, v2, 1 clamp
+; GFX950-NEXT: v_lshrrev_b32_e32 v8, v7, v5
+; GFX950-NEXT: v_bfe_u32 v7, v5, 0, v7
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
+; GFX950-NEXT: v_bfe_u32 v6, v5, v2, 1
+; GFX950-NEXT: s_movk_i32 s0, 0x80
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v6, v8, v7, v6 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX950-NEXT: v_lshrrev_b32_e32 v2, v2, v5
+; GFX950-NEXT: v_and_b32_e32 v7, 0x7ffff, v3
+; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX950-NEXT: v_add_u32_e32 v2, v2, v6
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v2
+; GFX950-NEXT: v_and_b32_sdwa v6, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX950-NEXT: v_bfe_u32 v4, v4, 20, 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
+; GFX950-NEXT: v_or3_b32 v2, v6, v5, v2
+; GFX950-NEXT: v_lshrrev_b32_e32 v5, 19, v3
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v4, v5, v7, v4 bitop3:0xe0
+; GFX950-NEXT: v_bfe_u32 v3, v3, 20, 3
+; GFX950-NEXT: v_add_u32_e32 v3, v3, v4
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_addc_co_u32_e32 v1, vcc, 6, v1, vcc
+; GFX950-NEXT: v_lshlrev_b32_e32 v4, 3, v1
+; GFX950-NEXT: v_or3_b32 v4, v6, v4, v3
+; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
+; GFX950-NEXT: v_cmp_eq_u32_e64 s[0:1], 15, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 6, v3
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 15, v1
+; GFX950-NEXT: v_or_b32_e32 v1, 0x7e, v6
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v1, vcc
+; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
+; GFX950-NEXT: s_movk_i32 s0, 0x204
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX950-NEXT: v_cmp_class_f32_e64 vcc, v0, s0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x7f
+; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_fp8_f32_saturate:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX1200-NEXT: v_frexp_mant_f32_e32 v3, v0
+; GFX1200-NEXT: s_mov_b32 s0, 0x7fffff
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_sub_nc_u32_e32 v2, 15, v1
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_and_or_b32 v4, v3, s0, 0x800000
+; GFX1200-NEXT: v_and_b32_e32 v6, 0x7ffff, v3
+; GFX1200-NEXT: v_bfe_u32 v8, v3, 20, 3
+; GFX1200-NEXT: v_lshrrev_b32_e32 v3, 19, v3
+; GFX1200-NEXT: v_min_u32_e32 v2, 31, v2
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
+; GFX1200-NEXT: v_sub_nc_u32_e64 v5, v2, 1 clamp
+; GFX1200-NEXT: v_lshrrev_b32_e32 v9, v2, v4
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_bfe_u32 v7, v4, 0, v5
+; GFX1200-NEXT: v_lshrrev_b32_e32 v4, v5, v4
+; GFX1200-NEXT: v_and_or_b32 v6, v8, 1, v6
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX1200-NEXT: v_and_or_b32 v5, v9, 1, v7
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_and_b32_e32 v4, v4, v5
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_dual_cndmask_b32 v2, 0, v4 :: v_dual_and_b32 v3, v3, v6
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_add_nc_u32_e32 v3, v8, v3
+; GFX1200-NEXT: v_lshrrev_b32_e32 v4, 24, v0
+; GFX1200-NEXT: v_add_nc_u32_e32 v2, v9, v2
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v3
+; GFX1200-NEXT: v_and_b32_e32 v4, 0x80, v4
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
+; GFX1200-NEXT: v_add_co_ci_u32_e64 v1, null, 6, v1, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 3, v1
+; GFX1200-NEXT: v_cmp_gt_i32_e64 s2, 1, v1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 6, v3
+; GFX1200-NEXT: v_or3_b32 v5, v4, v5, v3
+; GFX1200-NEXT: v_cmp_eq_u32_e64 s0, 15, v1
+; GFX1200-NEXT: v_cmp_lt_i32_e64 s1, 15, v1
+; GFX1200-NEXT: v_or3_b32 v2, v4, v6, v2
+; GFX1200-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_cndmask_b32_e64 v1, v5, v2, s2
+; GFX1200-NEXT: v_or_b32_e32 v2, 0x7e, v4
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_or_b32 vcc_lo, s1, s0
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX1200-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x204
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0x7f, v1, vcc_lo
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: to_fp8_f32_saturate:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX1250-NEXT: v_frexp_mant_f32_e32 v2, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1250-NEXT: v_dual_sub_nc_u32 v3, 15, v1 :: v_dual_lshrrev_b32 v8, 19, v2
+; GFX1250-NEXT: v_and_b32_e32 v4, 0x7fffff, v2
+; GFX1250-NEXT: v_and_b32_e32 v7, 0x7ffff, v2
+; GFX1250-NEXT: v_bfe_u32 v2, v2, 20, 3
+; GFX1250-NEXT: v_min_u32_e32 v3, 31, v3
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-NEXT: v_or_b32_e32 v5, 0x800000, v4
+; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
+; GFX1250-NEXT: v_bfe_u32 v4, v4, 20, 1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-NEXT: v_sub_nc_u32_e64 v6, v3, 1 clamp
+; GFX1250-NEXT: v_bfe_u32 v10, v5, v3, 1
+; GFX1250-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_bfe_u32 v9, v5, 0, v6
+; GFX1250-NEXT: v_dual_lshrrev_b32 v6, v6, v5 :: v_dual_lshrrev_b32 v5, v3, v5
+; GFX1250-NEXT: v_bitop3_b32 v4, v8, v7, v4 bitop3:0xe0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9
+; GFX1250-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
+; GFX1250-NEXT: v_bitop3_b32 v6, v6, v9, v10 bitop3:0xe0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_dual_cndmask_b32 v3, 0, v6 :: v_dual_add_nc_u32 v2, v2, v4
+; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_dual_lshrrev_b32 v4, 24, v0 :: v_dual_add_nc_u32 v3, v5, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, 6, v1, vcc_lo
+; GFX1250-NEXT: v_and_b32_e32 v4, 0x80, v4
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v3
+; GFX1250-NEXT: v_cmp_eq_u32_e64 s0, 15, v1
+; GFX1250-NEXT: v_cmp_lt_i32_e64 s1, 15, v1
+; GFX1250-NEXT: v_cmp_gt_i32_e64 s2, 1, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
+; GFX1250-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc_lo
+; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 6, v2
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: v_or3_b32 v3, v4, v6, v3
+; GFX1250-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX1250-NEXT: s_or_b32 vcc_lo, s1, s0
+; GFX1250-NEXT: v_lshlrev_b32_e32 v5, 3, v1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_or3_b32 v5, v4, v5, v2
+; GFX1250-NEXT: v_or_b32_e32 v2, 0x7e, v4
+; GFX1250-NEXT: v_cndmask_b32_e64 v1, v5, v3, s2
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX1250-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
+; GFX1250-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX1250-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x204
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX1250-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX1250-NEXT: v_cndmask_b32_e32 v0, 0x7f, v1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_f32_saturate:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX1310-NEXT: v_frexp_mant_f32_e32 v2, v0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_dual_sub_nc_u32 v3, 15, v1 :: v_dual_lshrrev_b32 v8, 19, v2
+; GFX1310-NEXT: v_and_b32_e32 v4, 0x7fffff, v2
+; GFX1310-NEXT: v_and_b32_e32 v7, 0x7ffff, v2
+; GFX1310-NEXT: v_bfe_u32 v2, v2, 20, 3
+; GFX1310-NEXT: v_min_u32_e32 v3, 31, v3
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_or_b32_e32 v5, 0x800000, v4
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
+; GFX1310-NEXT: v_bfe_u32 v4, v4, 20, 1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_sub_nc_u32_e64 v6, v3, 1 clamp
+; GFX1310-NEXT: v_bfe_u32 v10, v5, v3, 1
+; GFX1310-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_bfe_u32 v9, v5, 0, v6
+; GFX1310-NEXT: v_dual_lshrrev_b32 v6, v6, v5 :: v_dual_lshrrev_b32 v5, v3, v5
+; GFX1310-NEXT: v_bitop3_b32 v4, v8, v7, v4 bitop3:0xe0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9
+; GFX1310-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
+; GFX1310-NEXT: v_bitop3_b32 v6, v6, v9, v10 bitop3:0xe0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_dual_cndmask_b32 v3, 0, v6 :: v_dual_add_nc_u32 v2, v2, v4
+; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_dual_lshrrev_b32 v4, 24, v0 :: v_dual_add_nc_u32 v3, v5, v3
+; GFX1310-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX1310-NEXT: v_add_co_ci_u32_e64 v1, null, 6, v1, vcc_lo
+; GFX1310-NEXT: v_and_b32_e32 v4, 0x80, v4
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v3
+; GFX1310-NEXT: v_cmp_eq_u32_e64 s0, 15, v1
+; GFX1310-NEXT: v_cmp_lt_i32_e64 s1, 15, v1
+; GFX1310-NEXT: v_cmp_gt_i32_e64 s2, 1, v1
+; GFX1310-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
+; GFX1310-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc_lo
+; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 6, v2
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1310-NEXT: v_or3_b32 v3, v4, v6, v3
+; GFX1310-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX1310-NEXT: s_or_b32 vcc_lo, s1, s0
+; GFX1310-NEXT: v_lshlrev_b32_e32 v5, 3, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_or3_b32 v5, v4, v5, v2
+; GFX1310-NEXT: v_or_b32_e32 v2, 0x7e, v4
+; GFX1310-NEXT: v_cndmask_b32_e64 v1, v5, v3, s2
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX1310-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
+; GFX1310-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX1310-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x204
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0x7f, v1, vcc_lo
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call i8 @llvm.convert.to.arbitrary.fp.i8.f32(float %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 true)
+ ret i8 %r
+}
+
+; Only round-to-nearest-even maps to the HW conversion.
+define i8 @to_fp8_f32_towardzero(float %x) {
+; GFX950-LABEL: to_fp8_f32_towardzero:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_mant_f32_e32 v1, v0
+; GFX950-NEXT: v_bfe_u32 v2, v1, 20, 3
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v2
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v4, v0
+; GFX950-NEXT: v_and_b32_e32 v1, 0x7fffff, v1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_addc_co_u32_e32 v5, vcc, 6, v4, vcc
+; GFX950-NEXT: v_sub_u32_e32 v4, 15, v4
+; GFX950-NEXT: v_or_b32_e32 v1, 0x800000, v1
+; GFX950-NEXT: v_min_u32_e32 v4, 31, v4
+; GFX950-NEXT: v_lshrrev_b32_e32 v1, v4, v1
+; GFX950-NEXT: s_movk_i32 s0, 0x80
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 7, v1
+; GFX950-NEXT: v_and_b32_sdwa v3, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX950-NEXT: v_lshlrev_b32_e32 v6, 3, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 8, vcc
+; GFX950-NEXT: v_or3_b32 v2, v3, v6, v2
+; GFX950-NEXT: v_or3_b32 v1, v3, v4, v1
+; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
+; GFX950-NEXT: v_mov_b32_e32 v2, 0x7f
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_fp8_f32_towardzero:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX1200-NEXT: v_frexp_mant_f32_e32 v2, v0
+; GFX1200-NEXT: s_mov_b32 s0, 0x7fffff
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_sub_nc_u32_e32 v3, 15, v1
+; GFX1200-NEXT: v_bfe_u32 v4, v2, 20, 3
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_and_or_b32 v2, v2, s0, 0x800000
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_min_u32_e32 v3, 31, v3
+; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v4
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-NEXT: v_lshrrev_b32_e32 v2, v3, v2
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b32_e32 v3, 24, v0
+; GFX1200-NEXT: v_add_co_ci_u32_e64 v1, null, 6, v1, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_and_b32_e32 v3, 0x80, v3
+; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 3, v1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
+; GFX1200-NEXT: v_or3_b32 v4, v3, v5, v4
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_or3_b32 v2, v3, v6, v2
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0x7f, v1, vcc_lo
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: to_fp8_f32_towardzero:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_frexp_mant_f32_e32 v2, v0
+; GFX1250-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX1250-NEXT: s_mov_b32 s0, 0x7fffff
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_bfe_u32 v4, v2, 20, 3
+; GFX1250-NEXT: v_sub_nc_u32_e32 v3, 15, v1
+; GFX1250-NEXT: v_and_or_b32 v2, v2, s0, 0x800000
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v4
+; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, 6, v1, vcc_lo
+; GFX1250-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX1250-NEXT: v_lshlrev_b32_e32 v5, 3, v1
+; GFX1250-NEXT: v_min_u32_e32 v3, 31, v3
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_dual_lshrrev_b32 v2, v3, v2 :: v_dual_lshrrev_b32 v3, 24, v0
+; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_and_b32_e32 v3, 0x80, v3
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX1250-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc_lo
+; GFX1250-NEXT: v_or3_b32 v4, v3, v5, v4
+; GFX1250-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_or3_b32 v2, v3, v6, v2
+; GFX1250-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo
+; GFX1250-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX1250-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX1250-NEXT: v_cndmask_b32_e32 v0, 0x7f, v1, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_f32_towardzero:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_frexp_mant_f32_e32 v2, v0
+; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX1310-NEXT: s_mov_b32 s0, 0x7fffff
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_bfe_u32 v4, v2, 20, 3
+; GFX1310-NEXT: v_sub_nc_u32_e32 v3, 15, v1
+; GFX1310-NEXT: v_and_or_b32 v2, v2, s0, 0x800000
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v4
+; GFX1310-NEXT: v_add_co_ci_u32_e64 v1, null, 6, v1, vcc_lo
+; GFX1310-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX1310-NEXT: v_lshlrev_b32_e32 v5, 3, v1
+; GFX1310-NEXT: v_min_u32_e32 v3, 31, v3
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_dual_lshrrev_b32 v2, v3, v2 :: v_dual_lshrrev_b32 v3, 24, v0
+; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v2
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_and_b32_e32 v3, 0x80, v3
+; GFX1310-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX1310-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc_lo
+; GFX1310-NEXT: v_or3_b32 v4, v3, v5, v4
+; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_or3_b32 v2, v3, v6, v2
+; GFX1310-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo
+; GFX1310-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0x7f, v1, vcc_lo
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call i8 @llvm.convert.to.arbitrary.fp.i8.f32(float %x, metadata !"Float8E4M3FN", metadata !"round.towardzero", i1 false)
+ ret i8 %r
+}
+
+; FP4 has no unscaled HW conversion, only the scalef32 family, so it uses the
+; generic expansion.
+define i4 @to_fp4_f32(float %x) {
+; GFX950-LABEL: to_fp4_f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX950-NEXT: v_sub_u32_e32 v2, 23, v1
+; GFX950-NEXT: v_frexp_mant_f32_e32 v3, v0
+; GFX950-NEXT: v_min_u32_e32 v2, 31, v2
+; GFX950-NEXT: v_and_b32_e32 v4, 0x7fffff, v3
+; GFX950-NEXT: v_or_b32_e32 v4, 0x800000, v4
+; GFX950-NEXT: v_sub_u32_e64 v6, v2, 1 clamp
+; GFX950-NEXT: v_lshrrev_b32_e32 v7, v6, v4
+; GFX950-NEXT: v_bfe_u32 v6, v4, 0, v6
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; GFX950-NEXT: v_bfe_u32 v5, v4, v2, 1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b32 v5, v7, v6, v5 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX950-NEXT: v_lshrrev_b32_e32 v2, v2, v4
+; GFX950-NEXT: v_and_b32_e32 v6, 0x1fffff, v3
+; GFX950-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GFX950-NEXT: v_add_u32_e32 v2, v2, v5
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 1, v2
+; GFX950-NEXT: v_lshrrev_b32_e32 v5, 28, v0
+; GFX950-NEXT: v_and_b32_e32 v5, 8, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 2, vcc
+; GFX950-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; GFX950-NEXT: v_or3_b32 v2, v5, v4, v2
+; GFX950-NEXT: v_lshrrev_b32_e32 v4, 21, v3
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bfe_u32 v3, v3, 22, 1
+; GFX950-NEXT: v_bitop3_b32 v4, v4, v6, v3 bitop3:0xe0
+; GFX950-NEXT: v_add_u32_e32 v3, v3, v4
+; GFX950-NEXT: v_cmp_lt_i32_e32 vcc, 1, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX950-NEXT: v_lshlrev_b32_e32 v4, 1, v1
+; GFX950-NEXT: v_or3_b32 v3, v5, v4, v3
+; GFX950-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
+; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v1, v5, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_fp4_f32:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX1200-NEXT: v_frexp_mant_f32_e32 v3, v0
+; GFX1200-NEXT: s_mov_b32 s0, 0x7fffff
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_sub_nc_u32_e32 v2, 23, v1
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_and_or_b32 v4, v3, s0, 0x800000
+; GFX1200-NEXT: v_bfe_u32 v8, v3, 22, 1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_min_u32_e32 v2, 31, v2
+; GFX1200-NEXT: v_sub_nc_u32_e64 v5, v2, 1 clamp
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_lshrrev_b32_e32 v9, v2, v4
+; GFX1200-NEXT: v_bfe_u32 v6, v4, 0, v5
+; GFX1200-NEXT: v_lshrrev_b32_e32 v4, v5, v4
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX1200-NEXT: v_and_or_b32 v5, v9, 1, v6
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_and_b32_e32 v4, v4, v5
+; GFX1200-NEXT: v_and_b32_e32 v7, 0x1fffff, v3
+; GFX1200-NEXT: v_lshrrev_b32_e32 v3, 21, v3
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_or_b32_e32 v6, v7, v8
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b32_e32 v4, 28, v0
+; GFX1200-NEXT: v_add_nc_u32_e32 v2, v9, v2
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_and_b32_e32 v4, 8, v4
+; GFX1200-NEXT: v_and_b32_e32 v3, v3, v6
+; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 1, v2
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_add_nc_u32_e32 v3, v8, v3
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v5, 0, 2, s0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 1, v3
+; GFX1200-NEXT: v_or3_b32 v2, v4, v5, v2
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_lshlrev_b32_e32 v6, 1, v1
+; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
+; GFX1200-NEXT: v_or3_b32 v3, v4, v6, v3
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc_lo
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: to_fp4_f32:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX1250-NEXT: v_frexp_mant_f32_e32 v3, v0
+; GFX1250-NEXT: s_mov_b32 s0, 0x7fffff
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1250-NEXT: v_dual_sub_nc_u32 v2, 23, v1 :: v_dual_lshrrev_b32 v6, 21, v3
+; GFX1250-NEXT: v_and_or_b32 v4, v3, s0, 0x800000
+; GFX1250-NEXT: v_and_b32_e32 v8, 0x1fffff, v3
+; GFX1250-NEXT: v_bfe_u32 v3, v3, 22, 1
+; GFX1250-NEXT: v_min_u32_e32 v2, 31, v2
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_sub_nc_u32_e64 v5, v2, 1 clamp
+; GFX1250-NEXT: v_bfe_u32 v9, v4, v2, 1
+; GFX1250-NEXT: v_bfe_u32 v7, v4, 0, v5
+; GFX1250-NEXT: v_dual_lshrrev_b32 v5, v5, v4 :: v_dual_lshrrev_b32 v4, v2, v4
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
+; GFX1250-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX1250-NEXT: v_bitop3_b32 v5, v5, v7, v9 bitop3:0xe0
+; GFX1250-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_bitop3_b32 v6, v6, v8, v3 bitop3:0xe0
+; GFX1250-NEXT: v_dual_cndmask_b32 v2, 0, v5 :: v_dual_add_nc_u32 v3, v3, v6
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_dual_add_nc_u32 v2, v4, v2 :: v_dual_lshrrev_b32 v4, 28, v0
+; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 1, v3
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1250-NEXT: v_cmp_lt_i32_e64 s0, 1, v2
+; GFX1250-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX1250-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
+; GFX1250-NEXT: v_and_b32_e32 v4, 8, v4
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX1250-NEXT: v_cndmask_b32_e64 v5, 0, 2, s0
+; GFX1250-NEXT: v_lshlrev_b32_e32 v6, 1, v1
+; GFX1250-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_or3_b32 v2, v4, v5, v2
+; GFX1250-NEXT: v_or3_b32 v3, v4, v6, v3
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
+; GFX1250-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
+; GFX1250-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_fp4_f32:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX1310-NEXT: v_frexp_mant_f32_e32 v3, v0
+; GFX1310-NEXT: s_mov_b32 s0, 0x7fffff
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_dual_sub_nc_u32 v2, 23, v1 :: v_dual_lshrrev_b32 v6, 21, v3
+; GFX1310-NEXT: v_and_or_b32 v4, v3, s0, 0x800000
+; GFX1310-NEXT: v_and_b32_e32 v8, 0x1fffff, v3
+; GFX1310-NEXT: v_bfe_u32 v3, v3, 22, 1
+; GFX1310-NEXT: v_min_u32_e32 v2, 31, v2
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_sub_nc_u32_e64 v5, v2, 1 clamp
+; GFX1310-NEXT: v_bfe_u32 v9, v4, v2, 1
+; GFX1310-NEXT: v_bfe_u32 v7, v4, 0, v5
+; GFX1310-NEXT: v_dual_lshrrev_b32 v5, v5, v4 :: v_dual_lshrrev_b32 v4, v2, v4
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
+; GFX1310-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX1310-NEXT: v_bitop3_b32 v5, v5, v7, v9 bitop3:0xe0
+; GFX1310-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_bitop3_b32 v6, v6, v8, v3 bitop3:0xe0
+; GFX1310-NEXT: v_dual_cndmask_b32 v2, 0, v5 :: v_dual_add_nc_u32 v3, v3, v6
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_dual_add_nc_u32 v2, v4, v2 :: v_dual_lshrrev_b32 v4, 28, v0
+; GFX1310-NEXT: v_cmp_lt_i32_e32 vcc_lo, 1, v3
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_cmp_lt_i32_e64 s0, 1, v2
+; GFX1310-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX1310-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
+; GFX1310-NEXT: v_and_b32_e32 v4, 8, v4
+; GFX1310-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX1310-NEXT: v_cndmask_b32_e64 v5, 0, 2, s0
+; GFX1310-NEXT: v_lshlrev_b32_e32 v6, 1, v1
+; GFX1310-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_or3_b32 v2, v4, v5, v2
+; GFX1310-NEXT: v_or3_b32 v3, v4, v6, v3
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
+; GFX1310-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
+; GFX1310-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc_lo
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call i4 @llvm.convert.to.arbitrary.fp.i4.f32(float %x, metadata !"Float4E2M1FN", metadata !"round.tonearest", i1 false)
+ ret i4 %r
+}
+
+; f64 source has no HW conversion, so it uses the generic expansion.
+define i8 @to_fp8_f64(double %x) {
+; GFX950-LABEL: to_fp8_f64:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1]
+; GFX950-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX950-NEXT: v_sub_co_u32_e32 v4, vcc, 37, v2
+; GFX950-NEXT: v_frexp_mant_f64_e32 v[10:11], v[0:1]
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_subb_co_u32_e32 v5, vcc, 0, v3, vcc
+; GFX950-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[4:5]
+; GFX950-NEXT: v_and_b32_e32 v14, 0xfffff, v11
+; GFX950-NEXT: v_or_b32_e32 v13, 0x100000, v14
+; GFX950-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v4, 63, v4, vcc
+; GFX950-NEXT: v_cmp_lt_u64_e32 vcc, 1, v[4:5]
+; GFX950-NEXT: v_mov_b32_e32 v12, v10
+; GFX950-NEXT: v_mov_b32_e32 v7, 0
+; GFX950-NEXT: v_cndmask_b32_e32 v6, 1, v4, vcc
+; GFX950-NEXT: v_add_u32_e32 v6, -1, v6
+; GFX950-NEXT: v_lshlrev_b64 v[8:9], v6, 1
+; GFX950-NEXT: v_lshl_add_u64 v[8:9], v[8:9], 0, -1
+; GFX950-NEXT: v_and_b32_e32 v9, v13, v9
+; GFX950-NEXT: v_and_b32_e32 v8, v10, v8
+; GFX950-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
+; GFX950-NEXT: v_lshrrev_b64 v[8:9], v4, v[12:13]
+; GFX950-NEXT: v_and_b32_e32 v16, 1, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
+; GFX950-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX950-NEXT: v_lshrrev_b64 v[12:13], v6, v[12:13]
+; GFX950-NEXT: v_and_b32_e32 v6, v12, v15
+; GFX950-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX950-NEXT: s_movk_i32 s1, 0x80
+; GFX950-NEXT: s_mov_b32 s0, 0
+; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX950-NEXT: v_lshl_add_u64 v[4:5], v[8:9], 0, v[6:7]
+; GFX950-NEXT: v_cmp_lt_i64_e32 vcc, 3, v[4:5]
+; GFX950-NEXT: v_and_b32_sdwa v8, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 4, vcc
+; GFX950-NEXT: v_or3_b32 v9, v8, v5, v4
+; GFX950-NEXT: v_and_b32_e32 v5, 0x1ffff, v11
+; GFX950-NEXT: v_mov_b32_e32 v4, v10
+; GFX950-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX950-NEXT: v_bfe_u32 v5, v14, 18, 1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX950-NEXT: v_lshrrev_b32_e32 v5, 17, v11
+; GFX950-NEXT: v_and_b32_e32 v6, v5, v4
+; GFX950-NEXT: v_bfe_u32 v4, v11, 18, 2
+; GFX950-NEXT: v_mov_b32_e32 v5, v7
+; GFX950-NEXT: v_lshl_add_u64 v[4:5], v[4:5], 0, v[6:7]
+; GFX950-NEXT: v_cmp_lt_i64_e32 vcc, 3, v[4:5]
+; GFX950-NEXT: v_mov_b32_e32 v7, s0
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 0, v[6:7]
+; GFX950-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 0, 14
+; GFX950-NEXT: v_lshlrev_b64 v[6:7], 2, v[2:3]
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX950-NEXT: v_or_b32_e32 v6, v6, v4
+; GFX950-NEXT: v_cmp_gt_i64_e32 vcc, 1, v[2:3]
+; GFX950-NEXT: v_cmp_eq_u64_e64 s[0:1], 30, v[2:3]
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
+; GFX950-NEXT: v_cmp_lt_i64_e32 vcc, 3, v[4:5]
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i64_e32 vcc, 30, v[2:3]
+; GFX950-NEXT: v_or_b32_e32 v2, 0x7c, v8
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v6, v2, vcc
+; GFX950-NEXT: v_cmp_eq_f64_e32 vcc, 0, v[0:1]
+; GFX950-NEXT: s_movk_i32 s0, 0x204
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX950-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], s0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; GFX950-NEXT: v_mov_b32_e32 v3, 0x7e
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_fp8_f64:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
+; GFX1200-NEXT: v_frexp_mant_f64_e32 v[2:3], v[0:1]
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; GFX1200-NEXT: v_sub_co_u32 v4, vcc_lo, 37, v12
+; GFX1200-NEXT: v_dual_mov_b32 v6, v2 :: v_dual_and_b32 v9, 0xfffff, v3
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_sub_co_ci_u32_e64 v5, null, 0, v13, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b32_e32 v15, 17, v3
+; GFX1200-NEXT: v_bfe_u32 v17, v3, 18, 2
+; GFX1200-NEXT: v_bfe_u32 v11, v9, 18, 1
+; GFX1200-NEXT: v_cmp_gt_u64_e32 vcc_lo, 63, v[4:5]
+; GFX1200-NEXT: v_or_b32_e32 v9, 0x100000, v9
+; GFX1200-NEXT: v_and_b32_e32 v7, 0x1ffff, v3
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_dual_cndmask_b32 v5, 0, v5 :: v_dual_cndmask_b32 v4, 63, v4
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_cmp_lt_u64_e32 vcc_lo, 1, v[4:5]
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e32 v8, 1, v4, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
+; GFX1200-NEXT: v_add_nc_u32_e32 v14, -1, v8
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_lshlrev_b64_e64 v[6:7], v14, 1
+; GFX1200-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_add_co_u32 v11, vcc_lo, v6, -1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_add_co_ci_u32_e64 v16, null, -1, v7, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_and_b32_e32 v10, v15, v10
+; GFX1200-NEXT: v_mov_b32_e32 v8, v2
+; GFX1200-NEXT: v_and_b32_e32 v2, v2, v11
+; GFX1200-NEXT: v_and_b32_e32 v3, v9, v16
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_add_co_u32 v10, s0, v17, v10
+; GFX1200-NEXT: v_lshrrev_b64 v[6:7], v4, v[8:9]
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3]
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_add_co_ci_u32_e64 v11, null, 0, 0, s0
+; GFX1200-NEXT: v_lshrrev_b64 v[2:3], v14, v[8:9]
+; GFX1200-NEXT: v_and_b32_e32 v15, 1, v6
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i64_e32 vcc_lo, 3, v[10:11]
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-NEXT: v_or_b32_e32 v8, v16, v15
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v3, v11, 0, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b32_e32 v11, 24, v1
+; GFX1200-NEXT: v_and_b32_e32 v2, v2, v8
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_add_co_u32 v8, s0, v12, v9
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v13, s0
+; GFX1200-NEXT: v_cmp_ne_u64_e64 s0, 0, v[4:5]
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0
+; GFX1200-NEXT: v_add_co_u32 v4, s0, v8, 14
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v9, s0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_add_co_u32 v6, s0, v6, v2
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, s0
+; GFX1200-NEXT: v_lshlrev_b64_e32 v[8:9], 2, v[4:5]
+; GFX1200-NEXT: v_and_b32_e32 v9, 0x80, v11
+; GFX1200-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_cmp_lt_i64_e64 s0, 3, v[6:7]
+; GFX1200-NEXT: v_cmp_gt_i64_e64 s2, 1, v[4:5]
+; GFX1200-NEXT: v_cmp_lt_i64_e64 s1, 30, v[4:5]
+; GFX1200-NEXT: v_or_b32_e32 v7, v8, v9
+; GFX1200-NEXT: v_cmp_lt_i64_e32 vcc_lo, 3, v[2:3]
+; GFX1200-NEXT: v_or_b32_e32 v3, 0x7c, v9
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v6, v6, 0, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 4, s0
+; GFX1200-NEXT: v_or_b32_e32 v7, v7, v2
+; GFX1200-NEXT: v_cmp_eq_u64_e64 s0, 30, v[4:5]
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_or3_b32 v6, v9, v8, v6
+; GFX1200-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v2, v7, v6, s2
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_or_b32 vcc_lo, s1, s0
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f64_e32 vcc_lo, 0, v[0:1]
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
+; GFX1200-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x204
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0x7e, v2, vcc_lo
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: to_fp8_f64:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1]
+; GFX1250-NEXT: v_frexp_mant_f64_e32 v[6:7], v[0:1]
+; GFX1250-NEXT: s_mov_b32 s0, 0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_dual_mov_b32 v10, v6 :: v_dual_ashrrev_i32 v3, 31, v2
+; GFX1250-NEXT: v_and_b32_e32 v15, 0xfffff, v7
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_sub_nc_u64_e32 v[4:5], 37, v[2:3]
+; GFX1250-NEXT: v_or_b32_e32 v11, 0x100000, v15
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_min_u64 v[4:5], v[4:5], 63
+; GFX1250-NEXT: v_sub_nc_u32_e64 v14, v4, 1 clamp
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_lshrrev_b64 v[12:13], v4, v[10:11]
+; GFX1250-NEXT: v_lshlrev_b64_e64 v[8:9], v14, 1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_and_b32_e32 v16, 1, v12
+; GFX1250-NEXT: v_add_nc_u64_e32 v[8:9], -1, v[8:9]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_and_b32_e32 v9, v11, v9
+; GFX1250-NEXT: v_and_b32_e32 v8, v6, v8
+; GFX1250-NEXT: v_lshrrev_b64 v[10:11], v14, v[10:11]
+; GFX1250-NEXT: v_lshrrev_b32_e32 v14, 17, v7
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[8:9]
+; GFX1250-NEXT: v_and_b32_e32 v9, 0x1ffff, v7
+; GFX1250-NEXT: v_mov_b32_e32 v8, v6
+; GFX1250-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
+; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[8:9]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_bitop2_b32 v6, v17, v16 bitop3:0x54
+; GFX1250-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1250-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
+; GFX1250-NEXT: v_dual_mov_b32 v5, v9 :: v_dual_bitop2_b32 v6, v10, v6 bitop3:0x40
+; GFX1250-NEXT: v_bfe_u32 v10, v15, 18, 1
+; GFX1250-NEXT: v_bfe_u32 v4, v7, 18, 2
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_cndmask_b32_e32 v8, 0, v6, vcc_lo
+; GFX1250-NEXT: v_or_b32_e32 v10, v11, v10
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_add_nc_u64_e32 v[6:7], v[12:13], v[8:9]
+; GFX1250-NEXT: v_dual_lshrrev_b32 v10, 24, v1 :: v_dual_bitop2_b32 v8, v14, v10 bitop3:0x40
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1250-NEXT: v_add_nc_u64_e32 v[4:5], v[4:5], v[8:9]
+; GFX1250-NEXT: v_mov_b32_e32 v9, s0
+; GFX1250-NEXT: v_cmp_lt_i64_e64 s0, 3, v[6:7]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-NEXT: v_and_b32_e32 v7, 0x80, v10
+; GFX1250-NEXT: v_cmp_lt_i64_e32 vcc_lo, 3, v[4:5]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_cndmask_b32_e64 v6, v6, 0, s0
+; GFX1250-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX1250-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
+; GFX1250-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], v[2:3], v[8:9]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_cmp_lt_i64_e32 vcc_lo, 3, v[4:5]
+; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], 14, v[2:3]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_lshlrev_b64_e32 v[8:9], 2, v[2:3]
+; GFX1250-NEXT: v_cndmask_b32_e64 v9, 0, 4, s0
+; GFX1250-NEXT: v_cmp_gt_i64_e64 s2, 1, v[2:3]
+; GFX1250-NEXT: v_cmp_eq_u64_e64 s0, 30, v[2:3]
+; GFX1250-NEXT: v_cmp_lt_i64_e64 s1, 30, v[2:3]
+; GFX1250-NEXT: v_or_b32_e32 v3, 0x7c, v7
+; GFX1250-NEXT: v_or_b32_e32 v8, v8, v7
+; GFX1250-NEXT: v_or3_b32 v6, v7, v9, v6
+; GFX1250-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_or_b32_e32 v8, v8, v4
+; GFX1250-NEXT: s_or_b32 vcc_lo, s1, s0
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, v8, v6, s2
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX1250-NEXT: v_cmp_eq_f64_e32 vcc_lo, 0, v[0:1]
+; GFX1250-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX1250-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x204
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX1250-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GFX1250-NEXT: v_cndmask_b32_e32 v0, 0x7e, v2, vcc_lo
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_f64:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
+; GFX1310-NEXT: v_frexp_mant_f64_e32 v[2:3], v[0:1]
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; GFX1310-NEXT: v_sub_co_u32 v4, vcc_lo, 37, v12
+; GFX1310-NEXT: v_and_b32_e32 v7, 0x1ffff, v3
+; GFX1310-NEXT: v_and_b32_e32 v9, 0xfffff, v3
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_sub_co_ci_u32_e64 v5, null, 0, v13, vcc_lo
+; GFX1310-NEXT: v_bfe_u32 v17, v3, 18, 2
+; GFX1310-NEXT: v_mov_b32_e32 v6, v2
+; GFX1310-NEXT: v_bfe_u32 v11, v9, 18, 1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_cmp_gt_u64_e32 vcc_lo, 63, v[4:5]
+; GFX1310-NEXT: v_or_b32_e32 v9, 0x100000, v9
+; GFX1310-NEXT: v_dual_lshrrev_b32 v15, 17, v3 :: v_dual_cndmask_b32 v5, 0, v5, vcc_lo
+; GFX1310-NEXT: v_cndmask_b32_e32 v4, 63, v4, vcc_lo
+; GFX1310-NEXT: v_cmp_lt_u64_e32 vcc_lo, 1, v[4:5]
+; GFX1310-NEXT: v_cndmask_b32_e32 v8, 1, v4, vcc_lo
+; GFX1310-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_dual_add_nc_u32 v14, -1, v8 :: v_dual_mov_b32 v8, v2
+; GFX1310-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1310-NEXT: v_lshlrev_b64_e64 v[6:7], v14, 1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX1310-NEXT: v_add_co_u32 v11, vcc_lo, v6, -1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_add_co_ci_u32_e64 v16, null, -1, v7, vcc_lo
+; GFX1310-NEXT: v_and_b32_e32 v10, v15, v10
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_and_b32_e32 v2, v2, v11
+; GFX1310-NEXT: v_lshrrev_b64 v[6:7], v4, v[8:9]
+; GFX1310-NEXT: v_and_b32_e32 v3, v9, v16
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_add_co_u32 v10, s0, v17, v10
+; GFX1310-NEXT: v_add_co_ci_u32_e64 v11, null, 0, 0, s0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3]
+; GFX1310-NEXT: v_and_b32_e32 v15, 1, v6
+; GFX1310-NEXT: v_lshrrev_b64 v[2:3], v14, v[8:9]
+; GFX1310-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cmp_lt_i64_e32 vcc_lo, 3, v[10:11]
+; GFX1310-NEXT: v_or_b32_e32 v8, v16, v15
+; GFX1310-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1310-NEXT: v_cndmask_b32_e64 v3, v11, 0, vcc_lo
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_dual_lshrrev_b32 v11, 24, v1 :: v_dual_bitop2_b32 v2, v2, v8 bitop3:0x40
+; GFX1310-NEXT: v_add_co_u32 v8, s0, v12, v9
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v13, s0
+; GFX1310-NEXT: v_cmp_ne_u64_e64 s0, 0, v[4:5]
+; GFX1310-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_add_co_u32 v4, s0, v8, 14
+; GFX1310-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v9, s0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_add_co_u32 v6, s0, v6, v2
+; GFX1310-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, s0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_lshlrev_b64_e32 v[8:9], 2, v[4:5]
+; GFX1310-NEXT: v_and_b32_e32 v9, 0x80, v11
+; GFX1310-NEXT: v_cndmask_b32_e64 v2, v10, 0, vcc_lo
+; GFX1310-NEXT: v_cmp_lt_i64_e64 s0, 3, v[6:7]
+; GFX1310-NEXT: v_cmp_gt_i64_e64 s2, 1, v[4:5]
+; GFX1310-NEXT: v_cmp_lt_i64_e64 s1, 30, v[4:5]
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1310-NEXT: v_cmp_lt_i64_e32 vcc_lo, 3, v[2:3]
+; GFX1310-NEXT: v_or_b32_e32 v3, 0x7c, v9
+; GFX1310-NEXT: v_or_b32_e32 v7, v8, v9
+; GFX1310-NEXT: v_cndmask_b32_e64 v6, v6, 0, s0
+; GFX1310-NEXT: v_cndmask_b32_e64 v8, 0, 4, s0
+; GFX1310-NEXT: v_cmp_eq_u64_e64 s0, 30, v[4:5]
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_or_b32_e32 v7, v7, v2
+; GFX1310-NEXT: v_or3_b32 v6, v9, v8, v6
+; GFX1310-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX1310-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: s_or_b32 vcc_lo, s1, s0
+; GFX1310-NEXT: v_cndmask_b32_e64 v2, v7, v6, s2
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX1310-NEXT: v_cmp_eq_f64_e32 vcc_lo, 0, v[0:1]
+; GFX1310-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
+; GFX1310-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x204
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX1310-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0x7e, v2, vcc_lo
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call i8 @llvm.convert.to.arbitrary.fp.i8.f64(double %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
+ ret i8 %r
+}
+
+; bf16 source has no HW conversion, so it uses the generic expansion.
+define i8 @to_fp8_bf16(bfloat %x) {
+; GFX950-LABEL: to_fp8_bf16:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v5, v1
+; GFX950-NEXT: v_frexp_mant_f32_e32 v2, v1
+; GFX950-NEXT: v_xor_b32_e32 v6, -1, v5
+; GFX950-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0
+; GFX950-NEXT: s_movk_i32 s0, 0x80
+; GFX950-NEXT: v_mov_b32_e32 v3, 0x7f
+; GFX950-NEXT: v_min_u16_e32 v6, 15, v6
+; GFX950-NEXT: v_bitop3_b16 v4, v2, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v9, v6, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, v6, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v4, v9, v4
+; GFX950-NEXT: v_lshlrev_b16_e64 v9, v9, 1
+; GFX950-NEXT: v_and_b32_e32 v10, 0x7f, v2
+; GFX950-NEXT: v_add_u16_e32 v9, -1, v9
+; GFX950-NEXT: v_bitop3_b16 v9, v10, v9, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
+; GFX950-NEXT: v_and_b32_sdwa v0, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v4, v9, v8 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX950-NEXT: v_add_u16_e32 v4, v7, v4
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, 4, v10
+; GFX950-NEXT: v_and_b32_e32 v8, 1, v7
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v0, v4, v6 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, 3, v2
+; GFX950-NEXT: v_and_b32_e32 v2, 7, v2
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v2
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v6, v2, v8 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v2, v7, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v5, v6
+; GFX950-NEXT: v_add_u16_e32 v5, 6, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v6, 3, v5
+; GFX950-NEXT: v_bitop3_b16 v2, v0, v2, v6 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v5
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_fp8_bf16:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX1200-NEXT: v_lshrrev_b16 v0.l, 8, v0.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_frexp_mant_f32_e32 v2, v5
+; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v6, v5
+; GFX1200-NEXT: v_and_b16 v0.l, 0x80, v0.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_bfe_u32 v3, v2, 16, 1
+; GFX1200-NEXT: v_xor_b16 v1.l, v6.l, -1
+; GFX1200-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; GFX1200-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
+; GFX1200-NEXT: v_min_u16 v1.l, v1.l, 15
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_cndmask_b32_e32 v7, v3, v4, vcc_lo
+; GFX1200-NEXT: v_sub_nc_u16 v1.h, v1.l, 1 clamp
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_lshrrev_b32_e32 v3, 16, v7
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, v1.h, 1
+; GFX1200-NEXT: v_lshrrev_b32_e32 v7, 19, v7
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_and_b16 v2.h, 0x7f, v3.l
+; GFX1200-NEXT: v_and_b16 v3.l, v3.l, 7
+; GFX1200-NEXT: v_add_nc_u16 v2.l, v2.l, -1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v3.h, 0x80, v2.h
+; GFX1200-NEXT: v_lshrrev_b16 v2.h, 4, v2.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_and_b16 v2.l, v3.h, v2.l
+; GFX1200-NEXT: v_and_b16 v3.l, v2.h, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, v1.l, v3.h
+; GFX1200-NEXT: v_lshrrev_b16 v1.h, v1.h, v3.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v2.l, v4.l, v3.l
+; GFX1200-NEXT: v_and_b16 v3.l, v4.h, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v1.l
+; GFX1200-NEXT: v_and_b16 v2.l, v7.l, v2.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_mov_b16_e32 v4.l, v8.l
+; GFX1200-NEXT: v_add_nc_u16 v2.l, v2.h, v2.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_or_b16 v3.l, v4.l, v3.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_and_b16 v1.l, v1.h, v3.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, 0, s0
+; GFX1200-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.l, 0, v1.l, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_add_nc_u16 v0.h, v4.h, v1.l
+; GFX1200-NEXT: v_add_nc_u16 v1.l, v6.l, v3.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v0.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_add_nc_u16 v1.l, v1.l, 6
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, 8, vcc_lo
+; GFX1200-NEXT: v_lshlrev_b16 v2.h, 3, v1.l
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, 0, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v1.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v1.h, v0.l, v1.h
+; GFX1200-NEXT: v_or_b16 v2.h, v0.l, v2.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_or_b16 v0.h, v1.h, v0.h
+; GFX1200-NEXT: v_or_b16 v1.l, v2.h, v2.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v1.l, v0.h, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v5, v5
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.l, v0.h, v0.l, s0
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, vcc_lo
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: to_fp8_bf16:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, 0x80
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v0.l, 8, v0.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
+; GFX1250-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, v6
+; GFX1250-TRUE16-NEXT: v_and_b16 v0.l, 0x80, v0.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_xor_b16 v1.l, v7.l, -1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_min_u16 v1.l, v1.l, 15
+; GFX1250-TRUE16-NEXT: v_and_b16 v2.h, 0x7f, v2.l
+; GFX1250-TRUE16-NEXT: v_and_b16 v3.l, v2.l, 7
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_sub_nc_u16 v1.h, v1.l, 1 clamp
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v4.h, 4, v2.h
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
+; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v3.h, v1.h, 1
+; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v3.l, v3.h, -1
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.h, v2.l, v4.l, 0x7f bitop3:0xec
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v2.l, 3, v2.l
+; GFX1250-TRUE16-NEXT: v_and_b16 v4.l, v4.h, 1
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v2.h, v2.h, v3.l, 0x80 bitop3:0xc8
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v3.l, v1.l, v3.h
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v1.h, v1.h, v3.h
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v2.l, v2.l, v5.l, v4.l bitop3:0xe0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2.h
+; GFX1250-TRUE16-NEXT: v_and_b16 v2.h, v3.l, 1
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v2.l, v4.h, v2.l
+; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v1.l
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
+; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v1.h, v4.l, v2.h bitop3:0xe0
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, 0, s0
+; GFX1250-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, 0, v1.l, vcc_lo
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v0.h, v7.l, v4.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.l, v3.l, v1.l
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v0.h, v0.h, 6
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v1.l
+; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v2.l, 3, v0.h
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, 0, vcc_lo
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v2.h, 0, 8, vcc_lo
+; GFX1250-TRUE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v0.h
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.h, v0.l, v1.h, v2.l bitop3:0xfe
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v0.l, v1.l, v2.h bitop3:0xfe
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v1.l, vcc_lo
+; GFX1250-TRUE16-NEXT: v_cmp_o_f32_e32 vcc_lo, v6, v6
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.h, v0.l, s0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, vcc_lo
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_fp8_bf16:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v0, 8, v0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v0, 0x80, v0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_xor_b32_e32 v3, -1, v2
+; GFX1250-FAKE16-NEXT: v_frexp_mant_f32_e32 v4, v1
+; GFX1250-FAKE16-NEXT: v_min_u16 v3, v3, 15
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0
+; GFX1250-FAKE16-NEXT: s_movk_i32 s0, 0x80
+; GFX1250-FAKE16-NEXT: v_sub_nc_u16 v5, v3, 1 clamp
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v6, 0x7f, v4
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v9, v4, s0, 0x7f bitop3:0xec
+; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e64 s0, 0, v3
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v8, 7, v4
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v7, v5, 1
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v10, 4, v6
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v4, 3, v4
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v12, v3, v9
+; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v7, v7, -1
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX1250-FAKE16-NEXT: v_lshrrev_b16 v5, v5, v9
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v6, v6, v7, 0x80 bitop3:0xc8
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v7, 1, v12
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v4, v4, v8, v11 bitop3:0xe0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v4, v10, v4
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v5, v5, v6, v7 bitop3:0xe0
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, v5, s0
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v3, v12, v3
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v2, v2, v5
+; GFX1250-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_add_nc_u16 v2, v2, 6
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc_lo
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 3, v2
+; GFX1250-FAKE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v2
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v3, v0, v3, v5 bitop3:0xfe
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v4, v0, v4, v6 bitop3:0xfe
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX1250-FAKE16-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7f, v0, vcc_lo
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_bf16:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX1310-NEXT: v_lshrrev_b16 v0, 8, v0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
+; GFX1310-NEXT: v_and_b32_e32 v0, 0x80, v0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_xor_b32_e32 v3, -1, v2
+; GFX1310-NEXT: v_frexp_mant_f32_e32 v4, v1
+; GFX1310-NEXT: v_min_u16 v3, v3, 15
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0
+; GFX1310-NEXT: s_movk_i32 s0, 0x80
+; GFX1310-NEXT: v_sub_nc_u16 v5, v3, 1 clamp
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1310-NEXT: v_and_b32_e32 v6, 0x7f, v4
+; GFX1310-NEXT: v_bitop3_b16 v9, v4, s0, 0x7f bitop3:0xec
+; GFX1310-NEXT: v_cmp_ne_u16_e64 s0, 0, v3
+; GFX1310-NEXT: v_and_b32_e32 v8, 7, v4
+; GFX1310-NEXT: v_lshlrev_b16 v7, v5, 1
+; GFX1310-NEXT: v_lshrrev_b16 v10, 4, v6
+; GFX1310-NEXT: v_lshrrev_b16 v4, 3, v4
+; GFX1310-NEXT: v_lshrrev_b16 v12, v3, v9
+; GFX1310-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8
+; GFX1310-NEXT: v_add_nc_u16 v7, v7, -1
+; GFX1310-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX1310-NEXT: v_lshrrev_b16 v5, v5, v9
+; GFX1310-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_bitop3_b16 v6, v6, v7, 0x80 bitop3:0xc8
+; GFX1310-NEXT: v_and_b32_e32 v7, 1, v12
+; GFX1310-NEXT: v_bitop3_b16 v4, v4, v8, v11 bitop3:0xe0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6
+; GFX1310-NEXT: v_add_nc_u16 v4, v10, v4
+; GFX1310-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4
+; GFX1310-NEXT: v_bitop3_b16 v5, v5, v6, v7 bitop3:0xe0
+; GFX1310-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cndmask_b32_e64 v3, 0, v5, s0
+; GFX1310-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX1310-NEXT: v_add_nc_u16 v3, v12, v3
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_add_nc_u16 v2, v2, v5
+; GFX1310-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_add_nc_u16 v2, v2, 6
+; GFX1310-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
+; GFX1310-NEXT: v_cndmask_b32_e64 v5, 0, 8, vcc_lo
+; GFX1310-NEXT: v_lshlrev_b16 v6, 3, v2
+; GFX1310-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v2
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_bitop3_b16 v3, v0, v3, v5 bitop3:0xfe
+; GFX1310-NEXT: v_bitop3_b16 v4, v0, v4, v6 bitop3:0xfe
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc_lo
+; GFX1310-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1
+; GFX1310-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX1310-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1310-NEXT: v_cndmask_b32_e32 v0, 0x7f, v0, vcc_lo
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call i8 @llvm.convert.to.arbitrary.fp.i8.bf16(bfloat %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
+ ret i8 %r
+}
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
new file mode 100644
index 0000000000000..3aec6c15ee0c8
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
@@ -0,0 +1,3763 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=amdgpu9.50-amd-amdhsa | FileCheck -check-prefix=GFX950 %s
+; RUN: llc < %s -mtriple=amdgpu12.00-amd-amdhsa | FileCheck -check-prefix=GFX1200 %s
+; RUN: llc < %s -mtriple=amdgpu12.50-amd-amdhsa -mattr=+real-true16 | FileCheck -check-prefix=GFX1250-TRUE16 %s
+; RUN: llc < %s -mtriple=amdgpu12.50-amd-amdhsa -mattr=-real-true16 | FileCheck -check-prefix=GFX1250-FAKE16 %s
+; RUN: llc < %s -mtriple=amdgpu13.10-amd-amdhsa | FileCheck -check-prefix=GFX1310 %s
+
+; Element counts the vector legalizer neither splits nor widens evenly, so the
+; conversion is unrolled. An f32 source selects a packed HW instruction per lane
+; pair on every OCP subtarget. An f16 source needs the f16 -> fp8 conversions and
+; falls back to the software expansion without them.
+
+define <5 x i8> @to_fp8_v5f32(<5 x float> %x) {
+; GFX950-LABEL: to_fp8_v5f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v1, v1, v1
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v2, v2, v2
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v3, v3, v3
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v4, v4, v4
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_fp8_v5f32:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v0
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v1.l, v1, v1
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v2.l, v2, v2
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v3.l, v3, v3
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v4.l, v4, v4
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: to_fp8_v5f32:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v1.l, v1, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v2.l, v2, v2
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v3.l, v3, v3
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v4.l, v4, v4
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_fp8_v5f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v1, v1, v1
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v2, v2, v2
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v3, v3, v3
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v4, v4, v4
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_v5f32:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v1, v1, v1
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v2, v2, v2
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v3, v3, v3
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v4, v4, v4
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <5 x i8> @llvm.convert.to.arbitrary.fp.v5i8.v5f32(<5 x float> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
+ ret <5 x i8> %r
+}
+
+define <6 x i8> @to_fp8_v6f32(<6 x float> %x) {
+; GFX950-LABEL: to_fp8_v6f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v1, v1, v1
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v2, v2, v2
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v3, v3, v3
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v4, v4, v4
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v5, v5, v5
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_fp8_v6f32:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v0
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v1.l, v1, v1
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v2.l, v2, v2
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v3.l, v3, v3
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v4.l, v4, v4
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v5.l, v5, v5
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: to_fp8_v6f32:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v1.l, v1, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v2.l, v2, v2
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v3.l, v3, v3
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v4.l, v4, v4
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v5.l, v5, v5
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_fp8_v6f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v1, v1, v1
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v2, v2, v2
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v3, v3, v3
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v4, v4, v4
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v5, v5, v5
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_v6f32:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v1, v1, v1
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v2, v2, v2
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v3, v3, v3
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v4, v4, v4
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v5, v5, v5
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <6 x i8> @llvm.convert.to.arbitrary.fp.v6i8.v6f32(<6 x float> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
+ ret <6 x i8> %r
+}
+
+define <7 x i8> @to_fp8_v7f32(<7 x float> %x) {
+; GFX950-LABEL: to_fp8_v7f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v1, v1, v1
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v2, v2, v2
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v3, v3, v3
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v4, v4, v4
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v5, v5, v5
+; GFX950-NEXT: v_cvt_pk_fp8_f32 v6, v6, v6
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_fp8_v7f32:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v0
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v1.l, v1, v1
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v2.l, v2, v2
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v3.l, v3, v3
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v4.l, v4, v4
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v5.l, v5, v5
+; GFX1200-NEXT: v_cvt_pk_fp8_f32 v6.l, v6, v6
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: to_fp8_v7f32:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, v0, v0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v1.l, v1, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v2.l, v2, v2
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v3.l, v3, v3
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v4.l, v4, v4
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v5.l, v5, v5
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v6.l, v6, v6
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_fp8_v7f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v1, v1, v1
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v2, v2, v2
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v3, v3, v3
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v4, v4, v4
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v5, v5, v5
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f32 v6, v6, v6
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_v7f32:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v0, v0, v0
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v1, v1, v1
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v2, v2, v2
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v3, v3, v3
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v4, v4, v4
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v5, v5, v5
+; GFX1310-NEXT: v_cvt_pk_fp8_f32 v6, v6, v6
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <7 x i8> @llvm.convert.to.arbitrary.fp.v7i8.v7f32(<7 x float> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
+ ret <7 x i8> %r
+}
+
+define <5 x i8> @to_bf8_v5f32(<5 x float> %x) {
+; GFX950-LABEL: to_bf8_v5f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cvt_pk_bf8_f32 v0, v0, v0
+; GFX950-NEXT: v_cvt_pk_bf8_f32 v1, v1, v1
+; GFX950-NEXT: v_cvt_pk_bf8_f32 v2, v2, v2
+; GFX950-NEXT: v_cvt_pk_bf8_f32 v3, v3, v3
+; GFX950-NEXT: v_cvt_pk_bf8_f32 v4, v4, v4
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_bf8_v5f32:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v0
+; GFX1200-NEXT: v_cvt_pk_bf8_f32 v1.l, v1, v1
+; GFX1200-NEXT: v_cvt_pk_bf8_f32 v2.l, v2, v2
+; GFX1200-NEXT: v_cvt_pk_bf8_f32 v3.l, v3, v3
+; GFX1200-NEXT: v_cvt_pk_bf8_f32 v4.l, v4, v4
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: to_bf8_v5f32:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v0.l, v0, v0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v1.l, v1, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v2.l, v2, v2
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v3.l, v3, v3
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v4.l, v4, v4
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_bf8_v5f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v0, v0, v0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v1, v1, v1
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v2, v2, v2
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v3, v3, v3
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f32 v4, v4, v4
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_bf8_v5f32:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_bf8_f32 v0, v0, v0
+; GFX1310-NEXT: v_cvt_pk_bf8_f32 v1, v1, v1
+; GFX1310-NEXT: v_cvt_pk_bf8_f32 v2, v2, v2
+; GFX1310-NEXT: v_cvt_pk_bf8_f32 v3, v3, v3
+; GFX1310-NEXT: v_cvt_pk_bf8_f32 v4, v4, v4
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <5 x i8> @llvm.convert.to.arbitrary.fp.v5i8.v5f32(<5 x float> %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
+ ret <5 x i8> %r
+}
+
+define <5 x i8> @to_fp8_v5f16(<5 x half> %x) {
+; GFX950-LABEL: to_fp8_v5f16:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v6, v2
+; GFX950-NEXT: v_sub_u16_e32 v7, 2, v6
+; GFX950-NEXT: v_frexp_mant_f16_e32 v4, v2
+; GFX950-NEXT: s_movk_i32 s0, 0x400
+; GFX950-NEXT: v_mov_b32_e32 v3, 0x3ff
+; GFX950-NEXT: v_min_u16_e32 v7, 15, v7
+; GFX950-NEXT: v_bitop3_b16 v5, v4, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v10, v7, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, v7, v5
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, v10, v5
+; GFX950-NEXT: v_lshlrev_b16_e64 v10, v10, 1
+; GFX950-NEXT: v_and_b32_e32 v11, 0x3ff, v4
+; GFX950-NEXT: v_add_u16_e32 v10, -1, v10
+; GFX950-NEXT: v_bitop3_b16 v10, v11, v10, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_and_b32_e32 v9, 1, v8
+; GFX950-NEXT: s_movk_i32 s1, 0x80
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v5, v10, v9 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 7, v11
+; GFX950-NEXT: v_and_b32_e32 v10, 1, v9
+; GFX950-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v8, v5
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
+; GFX950-NEXT: v_and_b32_sdwa v8, v2, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_movk_i32 s2, 0xff
+; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v8, v5, v7 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, 6, v4
+; GFX950-NEXT: v_and_b32_e32 v4, 63, v4
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
+; GFX950-NEXT: s_mov_b32 s3, 0x7f7f0000
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v7, v4, v10 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v4, v9, v4
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v6, v6, v7
+; GFX950-NEXT: v_add_u16_e32 v6, 6, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v7, 3, v6
+; GFX950-NEXT: v_bitop3_b16 v4, v8, v4, v7 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v6
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v6, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v7, v6, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
+; GFX950-NEXT: v_and_b32_e32 v13, 0x3ff, v6
+; GFX950-NEXT: v_mov_b32_e32 v5, 0x7f
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_sub_u16_e32 v9, 2, v8
+; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
+; GFX950-NEXT: v_sub_u16_e64 v12, v9, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, v9, v7
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, v12, v7
+; GFX950-NEXT: v_lshlrev_b16_e64 v12, v12, 1
+; GFX950-NEXT: v_add_u16_e32 v12, -1, v12
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v2, v2
+; GFX950-NEXT: v_bitop3_b16 v12, v13, v12, s0 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v7, v12, v11 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v13
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
+; GFX950-NEXT: v_add_u16_e32 v7, v10, v7
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v7
+; GFX950-NEXT: v_lshrrev_b32_e32 v10, 31, v2
+; GFX950-NEXT: v_lshlrev_b16_e32 v10, 7, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v10, v7, v9 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v6
+; GFX950-NEXT: v_and_b32_e32 v6, 63, v6
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v9, v6, v12 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v6, v11, v6
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v8, v8, v9
+; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v9, 3, v8
+; GFX950-NEXT: v_bitop3_b16 v6, v10, v6, v9 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: v_mov_b32_e32 v8, 0
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v9, v1
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v2, v8 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v2, v2 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: v_sub_u16_e32 v10, 2, v9
+; GFX950-NEXT: v_min_u16_e32 v10, 15, v10
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v2, 8, v2
+; GFX950-NEXT: v_bitop3_b16 v4, v4, v2, s2 bitop3:0xec
+; GFX950-NEXT: v_frexp_mant_f16_e32 v2, v1
+; GFX950-NEXT: v_bitop3_b16 v6, v2, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v13, v10, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, v10, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, v13, v6
+; GFX950-NEXT: v_lshlrev_b16_e64 v13, v13, 1
+; GFX950-NEXT: v_and_b32_e32 v14, 0x3ff, v2
+; GFX950-NEXT: v_add_u16_e32 v13, -1, v13
+; GFX950-NEXT: v_bitop3_b16 v13, v14, v13, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_or_b32_sdwa v7, v4, s3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v6, v13, v12 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, 7, v14
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX950-NEXT: v_add_u16_e32 v6, v11, v6
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
+; GFX950-NEXT: v_and_b32_sdwa v11, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v11, v6, v10 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, 6, v2
+; GFX950-NEXT: v_and_b32_e32 v2, 63, v2
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v2
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v10, v2, v13 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v2, v12, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v9, v9, v10
+; GFX950-NEXT: v_add_u16_e32 v9, 6, v9
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v10, 3, v9
+; GFX950-NEXT: v_bitop3_b16 v2, v11, v2, v10 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v9
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v9, v6, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v11, vcc
+; GFX950-NEXT: v_sub_u16_e32 v11, 2, v10
+; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
+; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, v14, v9
+; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
+; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v6
+; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v1, v1
+; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s0 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v9, v9, v14, v13 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v15
+; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
+; GFX950-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
+; GFX950-NEXT: v_add_u16_e32 v9, v12, v9
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v9
+; GFX950-NEXT: v_lshrrev_b32_e32 v12, 31, v1
+; GFX950-NEXT: v_lshlrev_b16_e32 v12, 7, v12
+; GFX950-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v9, v12, v9, v11 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 6, v6
+; GFX950-NEXT: v_and_b32_e32 v6, 63, v6
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v11, v6, v14 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v6, v13, v6
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v10, v10, v11
+; GFX950-NEXT: v_add_u16_e32 v10, 6, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 3, v10
+; GFX950-NEXT: v_bitop3_b16 v6, v12, v6, v11 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v10, v0
+; GFX950-NEXT: v_sub_u16_e32 v11, 2, v10
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v1, v8 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
+; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v12, vcc
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v1, 8, v1
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v1, s2 bitop3:0xec
+; GFX950-NEXT: v_frexp_mant_f16_e32 v1, v0
+; GFX950-NEXT: v_bitop3_b16 v9, v1, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, v14, v9
+; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
+; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v1
+; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v9, v9, v14, v13 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v15
+; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
+; GFX950-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
+; GFX950-NEXT: v_add_u16_e32 v9, v12, v9
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v9
+; GFX950-NEXT: v_and_b32_sdwa v12, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_lshrrev_b64 v[6:7], 24, v[6:7]
+; GFX950-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v9, v12, v9, v11 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 6, v1
+; GFX950-NEXT: v_and_b32_e32 v1, 63, v1
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v11, v1, v14 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v1, v13, v1
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v10, v10, v11
+; GFX950-NEXT: v_add_u16_e32 v10, 6, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 3, v10
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v1, v12, v1, v11 bitop3:0xfe
+; GFX950-NEXT: v_sub_u16_e32 v11, 2, v10
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
+; GFX950-NEXT: v_bitop3_b16 v3, v9, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v12, vcc
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v14, v3
+; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
+; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v9
+; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
+; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s0 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v3, v14, v13 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v15
+; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
+; GFX950-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX950-NEXT: v_add_u16_e32 v3, v12, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
+; GFX950-NEXT: v_lshrrev_b32_e32 v12, 31, v0
+; GFX950-NEXT: v_lshlrev_b16_e32 v12, 7, v12
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v12, v3, v11 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 6, v9
+; GFX950-NEXT: v_and_b32_e32 v9, 63, v9
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v9, v11, v9, v14 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v9, v13, v9
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v9
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v10, v10, v11
+; GFX950-NEXT: v_add_u16_e32 v10, 6, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 3, v10
+; GFX950-NEXT: v_bitop3_b16 v9, v12, v9, v11 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v8 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v12, vcc
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v3, 8, v0
+; GFX950-NEXT: v_bitop3_b16 v0, v1, v3, s2 bitop3:0xec
+; GFX950-NEXT: v_lshl_or_b32 v1, v2, 16, v3
+; GFX950-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX950-NEXT: v_mov_b32_e32 v3, v6
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_fp8_v5f16:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v2.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v3.h, v2.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, 8, v2.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v4.h, v1.l
+; GFX1200-NEXT: v_sub_nc_u16 v5.l, 2, v3.l
+; GFX1200-NEXT: v_and_b16 v5.h, 0x3ff, v3.h
+; GFX1200-NEXT: v_and_b16 v6.l, v3.h, 63
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v14.l
+; GFX1200-NEXT: v_lshrrev_b16 v3.h, 6, v3.h
+; GFX1200-NEXT: v_min_u16 v5.l, v5.l, 15
+; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v5.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v5.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6.l
+; GFX1200-NEXT: v_sub_nc_u16 v9.h, 2, v7.l
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, v5.l, 1 clamp
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v14.l
+; GFX1200-NEXT: v_and_b16 v10.h, v5.h, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_min_u16 v9.h, v9.h, 15
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, v8.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v11.h, v5.l, v8.l
+; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v6.h
+; GFX1200-NEXT: v_or_b16 v10.h, v11.l, v10.h
+; GFX1200-NEXT: v_sub_nc_u16 v11.l, v9.h, 1 clamp
+; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
+; GFX1200-NEXT: v_and_b16 v10.l, v6.h, 63
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
+; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v10.h
+; GFX1200-NEXT: v_lshlrev_b16 v10.h, v11.l, 1
+; GFX1200-NEXT: v_and_b16 v9.l, v8.l, v9.l
+; GFX1200-NEXT: v_or_b16 v5.l, 0x400, v6.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v5.h, v3.h
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v10.h, -1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
+; GFX1200-NEXT: v_and_b16 v9.l, v11.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, v8.h, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
+; GFX1200-NEXT: v_and_b16 v5.h, v5.l, v5.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v10.l
+; GFX1200-NEXT: v_and_b16 v10.l, v6.l, 1
+; GFX1200-NEXT: v_and_b16 v4.l, 0x80, v4.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v5.h
+; GFX1200-NEXT: v_or_b16 v8.h, v12.l, v9.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v3.h
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v9.h, v5.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, s1
+; GFX1200-NEXT: v_and_b16 v8.l, v8.l, v8.h
+; GFX1200-NEXT: v_or_b16 v8.h, v13.l, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, v11.l, v5.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, 2, v4.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, v8.l, vcc_lo
+; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v12.l
+; GFX1200-NEXT: v_and_b16 v8.l, v9.l, 1
+; GFX1200-NEXT: v_mov_b16_e32 v12.l, v15.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v11.h, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, 6
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s0
+; GFX1200-NEXT: v_or_b16 v8.l, v12.l, v8.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v3.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.l
+; GFX1200-NEXT: v_and_b16 v5.l, v5.l, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, 8, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v6.l
+; GFX1200-NEXT: v_or_b16 v8.l, v4.l, v8.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v5.l, 0, v5.l, s1
+; GFX1200-NEXT: v_or_b16 v6.h, v4.l, v6.h
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v2.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1200-NEXT: v_or_b16 v3.l, v8.l, v3.h
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v9.l, v5.l
+; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v5.h
+; GFX1200-NEXT: v_min_u16 v5.h, v7.h, 15
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v1.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v2
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v3.h, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v7.l, v8.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, v5.h, 1 clamp
+; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v6.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, 7, v9.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, 8, s0
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v3.h, 6
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.l, 1
+; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v7.h
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v4.l, s1
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, s0
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v3.h
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_or_b16 v2.h, v8.h, v2.h
+; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v2.l
+; GFX1200-NEXT: v_or_b16 v9.l, v8.h, v9.l
+; GFX1200-NEXT: v_and_b16 v4.l, v9.h, v8.l
+; GFX1200-NEXT: v_or_b16 v2.l, v2.h, v5.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, v5.h, v9.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v1
+; GFX1200-NEXT: v_or_b16 v2.h, v9.l, v6.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0x7f, v3.l, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.l, v12.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.h
+; GFX1200-NEXT: v_and_b16 v3.h, v5.l, 1
+; GFX1200-NEXT: v_and_b16 v3.l, 0xff, v3.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_mov_b16_e32 v4.l, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.h, v2.l, s0
+; GFX1200-NEXT: v_and_b16 v2.h, v6.h, 63
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
+; GFX1200-NEXT: v_or_b16 v3.h, v4.l, v3.h
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, v7.l, v9.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v2.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 7, v7.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v8.h, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v14.l, v14.l
+; GFX1200-NEXT: v_and_b16 v2.h, v4.l, v3.h
+; GFX1200-NEXT: v_sub_nc_u16 v3.h, 2, v6.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
+; GFX1200-NEXT: v_and_b16 v4.l, v7.l, 1
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v12.l
+; GFX1200-NEXT: v_min_u16 v3.h, v3.h, 15
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v2.h, s0
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, 0x7f, v2.l, vcc_lo
+; GFX1200-NEXT: v_and_b16 v9.l, v5.h, 63
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, v3.h, 1 clamp
+; GFX1200-NEXT: v_or_b16 v4.l, v8.l, v4.l
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v5.l, v2.h
+; GFX1200-NEXT: v_and_b16 v5.l, 0x3ff, v5.h
+; GFX1200-NEXT: v_lshrrev_b16 v8.h, 8, v1.l
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.h, 1
+; GFX1200-NEXT: v_and_b16 v4.l, v6.h, v4.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.h
+; GFX1200-NEXT: v_or_b16 v6.h, 0x400, v5.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 7, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v7.l, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s0
+; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, s0
+; GFX1200-NEXT: v_lshrrev_b16 v9.h, v3.h, v6.h
+; GFX1200-NEXT: v_and_b16 v8.l, v6.h, v8.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.l
+; GFX1200-NEXT: v_and_b16 v8.h, 0x80, v8.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v7.h, v6.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 6, v5.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1200-NEXT: v_and_b16 v10.h, v5.l, 1
+; GFX1200-NEXT: v_or_b16 v7.l, v8.h, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, vcc_lo
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
+; GFX1200-NEXT: v_and_b16 v9.l, v9.h, 1
+; GFX1200-NEXT: v_or_b16 v2.h, v7.l, v2.h
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, v8.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v0.l
+; GFX1200-NEXT: v_or_b16 v8.l, v10.l, v9.l
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v13.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, 6
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v2.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.l
+; GFX1200-NEXT: v_or_b16 v7.h, v11.l, v10.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v11, 16, v0
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, v6.h, s0
+; GFX1200-NEXT: v_and_b16 v3.h, v5.h, v7.h
+; GFX1200-NEXT: v_lshlrev_b16 v5.h, 3, v4.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v4.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.h, v0.l
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v9.h, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v5.l, v3.h
+; GFX1200-NEXT: v_or_b16 v5.l, v8.h, v5.h
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v7.l
+; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v4.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v6.h
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.h
+; GFX1200-NEXT: v_or_b16 v4.l, v5.l, v4.l
+; GFX1200-NEXT: v_min_u16 v5.l, v5.h, 15
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v6.h, v6.h, 0, s1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v4.l, v2.h, s0
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, v5.l, 1 clamp
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v1.l
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v1
+; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v7.h
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, 8, s1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v8.h, s0
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v8.l
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v5.h, 1
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, 7, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, v5.h, v9.h
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v1.l, v1.l
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_or_b16 v1.h, v9.l, v1.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0x7f, v2.h, s0
+; GFX1200-NEXT: v_lshlrev_b16 v10.l, 3, v6.l
+; GFX1200-NEXT: v_and_b16 v4.l, v9.h, v8.l
+; GFX1200-NEXT: v_or_b16 v1.h, v1.h, v6.h
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, v5.l, v9.h
+; GFX1200-NEXT: v_and_b16 v2.h, 0xff, v2.h
+; GFX1200-NEXT: v_or_b16 v6.h, v9.l, v10.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.l
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v11.l
+; GFX1200-NEXT: v_and_b16 v4.l, v8.l, 1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v3.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v6.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.h, v11.l
+; GFX1200-NEXT: v_mov_b16_e32 v6.l, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_or_b16 v3.h, v6.l, v4.l
+; GFX1200-NEXT: v_sub_nc_u16 v4.l, 2, v6.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.h, v9.l, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.l, v11.l
+; GFX1200-NEXT: v_and_b16 v3.h, v5.h, v3.h
+; GFX1200-NEXT: v_min_u16 v1.h, v4.l, 15
+; GFX1200-NEXT: v_and_b16 v4.l, v4.h, 63
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v7.h
+; GFX1200-NEXT: v_and_b16 v9.l, v5.l, 63
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, 6, v4.h
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, v1.h, 1 clamp
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v4.l
+; GFX1200-NEXT: v_and_b16 v4.l, 0x3ff, v5.l
+; GFX1200-NEXT: v_and_b16 v8.h, v6.l, 1
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v5.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, v5.h, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.l
+; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v4.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, 7, v4.l
+; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
+; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v8.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s1
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v1.h, v9.h
+; GFX1200-NEXT: v_and_b16 v9.l, v4.l, 1
+; GFX1200-NEXT: v_and_b16 v7.h, v9.h, v7.h
+; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v8.h
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v13.l
+; GFX1200-NEXT: v_and_b16 v8.h, v10.h, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0, v3.h, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v7.h
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v6.l, v4.h
+; GFX1200-NEXT: v_or_b16 v7.h, v10.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, v5.h, v9.h
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v8.l, v3.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s1
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
+; GFX1200-NEXT: v_and_b16 v5.l, v5.l, v7.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v1.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v3.h
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v13.l
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v12.l, v12.l
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, v5.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s3
+; GFX1200-NEXT: v_or_b16 v6.l, v9.l, v8.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 7, v4.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7f, v1.l, s1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_and_b16 v5.l, v5.h, v6.l
+; GFX1200-NEXT: v_mov_b16_e32 v6.l, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s4
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s4
+; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, v5.l, s2
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v0.l
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v7.l, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, 8, s3
+; GFX1200-NEXT: v_add_nc_u16 v1.h, v10.h, v1.h
+; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, v8.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, 6
+; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v1.h
+; GFX1200-NEXT: v_or_b16 v0.h, v5.l, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.h, 6
+; GFX1200-NEXT: v_lshlrev_b16 v6.h, 3, v5.h
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 7, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, s2
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s2
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, 3, v6.l
+; GFX1200-NEXT: v_or_b16 v6.h, v5.l, v6.h
+; GFX1200-NEXT: v_or_b16 v0.h, v0.h, v3.h
+; GFX1200-NEXT: v_or_b16 v7.l, v7.h, v7.l
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v5.h
+; GFX1200-NEXT: v_or_b16 v8.l, v7.h, v8.l
+; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v4.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s2, 1, v6.l
+; GFX1200-NEXT: v_or_b16 v1.h, v7.l, v1.h
+; GFX1200-NEXT: v_or_b16 v2.h, v2.h, v1.l
+; GFX1200-NEXT: v_or_b16 v4.l, v8.l, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v3.h, v0.h, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v4.l, v1.h, s2
+; GFX1200-NEXT: v_or_b16 v4.l, v3.l, v2.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
+; GFX1200-NEXT: v_mov_b16_e32 v3.l, v2.h
+; GFX1200-NEXT: v_cndmask_b16 v0.l, v1.h, v7.h, s0
+; GFX1200-NEXT: v_cvt_u32_u16_e32 v1, v4.l
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v11.l, v11.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7f, v0.h, vcc_lo
+; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX1200-NEXT: v_or_b32_e32 v6, 0x7f7f0000, v1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, s0
+; GFX1200-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_lshrrev_b64 v[5:6], 24, v[5:6]
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v2.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX1200-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1200-NEXT: v_mov_b16_e32 v3.l, v5.l
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: to_fp8_v5f16:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v3.h, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v5.h, s0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v5.l, v2
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v3.l, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.h
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_dual_lshlrev_b32 v4, 16, v1 :: v_dual_lshrrev_b32 v1, 8, v3
+; GFX1250-TRUE16-NEXT: v_lshrrev_b64 v[6:7], 24, v[4:5]
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.l, v6.l
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_fp8_v5f16:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v4, v2
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v0, v0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v3, s0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v2, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v4
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_lshl_or_b32 v7, v3, 16, v1
+; GFX1250-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v5
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_dual_lshlrev_b32 v6, 16, v2 :: v_dual_lshrrev_b32 v1, 8, v1
+; GFX1250-FAKE16-NEXT: v_lshrrev_b64 v[6:7], 24, v[6:7]
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_v5f16:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v5, v2
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v0, v0
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v4, s0
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v2, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_and_b32_e32 v1, 0xffff, v5
+; GFX1310-NEXT: v_and_b32_e32 v6, 0xffff, v0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_lshl_or_b32 v4, v4, 16, v1
+; GFX1310-NEXT: v_lshl_or_b32 v1, v2, 16, v6
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_dual_lshlrev_b32 v3, 16, v2 :: v_dual_lshrrev_b32 v1, 8, v1
+; GFX1310-NEXT: v_lshrrev_b64 v[3:4], 24, v[3:4]
+; GFX1310-NEXT: v_mov_b32_e32 v4, v5
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <5 x i8> @llvm.convert.to.arbitrary.fp.v5i8.v5f16(<5 x half> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
+ ret <5 x i8> %r
+}
+
+define <6 x i8> @to_fp8_v6f16(<6 x half> %x) {
+; GFX950-LABEL: to_fp8_v6f16:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v6, v2
+; GFX950-NEXT: v_sub_u16_e32 v7, 2, v6
+; GFX950-NEXT: v_frexp_mant_f16_e32 v4, v2
+; GFX950-NEXT: s_movk_i32 s0, 0x400
+; GFX950-NEXT: v_mov_b32_e32 v3, 0x3ff
+; GFX950-NEXT: v_min_u16_e32 v7, 15, v7
+; GFX950-NEXT: v_bitop3_b16 v5, v4, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v10, v7, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, v7, v5
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, v10, v5
+; GFX950-NEXT: v_lshlrev_b16_e64 v10, v10, 1
+; GFX950-NEXT: v_and_b32_e32 v11, 0x3ff, v4
+; GFX950-NEXT: v_add_u16_e32 v10, -1, v10
+; GFX950-NEXT: v_bitop3_b16 v10, v11, v10, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_and_b32_e32 v9, 1, v8
+; GFX950-NEXT: s_movk_i32 s1, 0x80
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v5, v10, v9 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 7, v11
+; GFX950-NEXT: v_and_b32_e32 v10, 1, v9
+; GFX950-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v8, v5
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
+; GFX950-NEXT: v_and_b32_sdwa v8, v2, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_movk_i32 s2, 0xff
+; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v8, v5, v7 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, 6, v4
+; GFX950-NEXT: v_and_b32_e32 v4, 63, v4
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
+; GFX950-NEXT: s_mov_b32 s3, 0x7f7f0000
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v7, v4, v10 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v4, v9, v4
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v6, v6, v7
+; GFX950-NEXT: v_add_u16_e32 v6, 6, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v7, 3, v6
+; GFX950-NEXT: v_bitop3_b16 v4, v8, v4, v7 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v6
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v6, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v7, v6, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
+; GFX950-NEXT: v_and_b32_e32 v13, 0x3ff, v6
+; GFX950-NEXT: v_mov_b32_e32 v5, 0x7f
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_sub_u16_e32 v9, 2, v8
+; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
+; GFX950-NEXT: v_sub_u16_e64 v12, v9, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, v9, v7
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, v12, v7
+; GFX950-NEXT: v_lshlrev_b16_e64 v12, v12, 1
+; GFX950-NEXT: v_add_u16_e32 v12, -1, v12
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v2, v2
+; GFX950-NEXT: v_bitop3_b16 v12, v13, v12, s0 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v7, v12, v11 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v13
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
+; GFX950-NEXT: v_add_u16_e32 v7, v10, v7
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v7
+; GFX950-NEXT: v_lshrrev_b32_e32 v10, 31, v2
+; GFX950-NEXT: v_lshlrev_b16_e32 v10, 7, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v10, v7, v9 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v6
+; GFX950-NEXT: v_and_b32_e32 v6, 63, v6
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v9, v6, v12 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v6, v11, v6
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v8, v8, v9
+; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v9, 3, v8
+; GFX950-NEXT: v_bitop3_b16 v6, v10, v6, v9 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: v_mov_b32_e32 v8, 0
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v9, v1
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v2, v8 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v2, v2 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: v_sub_u16_e32 v10, 2, v9
+; GFX950-NEXT: v_min_u16_e32 v10, 15, v10
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v2, 8, v2
+; GFX950-NEXT: v_bitop3_b16 v4, v4, v2, s2 bitop3:0xec
+; GFX950-NEXT: v_frexp_mant_f16_e32 v2, v1
+; GFX950-NEXT: v_bitop3_b16 v6, v2, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v13, v10, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, v10, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, v13, v6
+; GFX950-NEXT: v_lshlrev_b16_e64 v13, v13, 1
+; GFX950-NEXT: v_and_b32_e32 v14, 0x3ff, v2
+; GFX950-NEXT: v_add_u16_e32 v13, -1, v13
+; GFX950-NEXT: v_bitop3_b16 v13, v14, v13, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_or_b32_sdwa v7, v4, s3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v6, v13, v12 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, 7, v14
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX950-NEXT: v_add_u16_e32 v6, v11, v6
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
+; GFX950-NEXT: v_and_b32_sdwa v11, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v11, v6, v10 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, 6, v2
+; GFX950-NEXT: v_and_b32_e32 v2, 63, v2
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v2
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v10, v2, v13 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v2, v12, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v9, v9, v10
+; GFX950-NEXT: v_add_u16_e32 v9, 6, v9
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v10, 3, v9
+; GFX950-NEXT: v_bitop3_b16 v2, v11, v2, v10 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v9
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v9, v6, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v11, vcc
+; GFX950-NEXT: v_sub_u16_e32 v11, 2, v10
+; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
+; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, v14, v9
+; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
+; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v6
+; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v1, v1
+; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s0 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v9, v9, v14, v13 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v15
+; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
+; GFX950-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
+; GFX950-NEXT: v_add_u16_e32 v9, v12, v9
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v9
+; GFX950-NEXT: v_lshrrev_b32_e32 v12, 31, v1
+; GFX950-NEXT: v_lshlrev_b16_e32 v12, 7, v12
+; GFX950-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v9, v12, v9, v11 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 6, v6
+; GFX950-NEXT: v_and_b32_e32 v6, 63, v6
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v11, v6, v14 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v6, v13, v6
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v10, v10, v11
+; GFX950-NEXT: v_add_u16_e32 v10, 6, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 3, v10
+; GFX950-NEXT: v_bitop3_b16 v6, v12, v6, v11 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v10, v0
+; GFX950-NEXT: v_sub_u16_e32 v11, 2, v10
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v1, v8 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
+; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v12, vcc
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v1, 8, v1
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v1, s2 bitop3:0xec
+; GFX950-NEXT: v_frexp_mant_f16_e32 v1, v0
+; GFX950-NEXT: v_bitop3_b16 v9, v1, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, v14, v9
+; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
+; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v1
+; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v9, v9, v14, v13 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v15
+; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
+; GFX950-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
+; GFX950-NEXT: v_add_u16_e32 v9, v12, v9
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v9
+; GFX950-NEXT: v_and_b32_sdwa v12, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v9, v12, v9, v11 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 6, v1
+; GFX950-NEXT: v_and_b32_e32 v1, 63, v1
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v11, v1, v14 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v1, v13, v1
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v10, v10, v11
+; GFX950-NEXT: v_add_u16_e32 v10, 6, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 3, v10
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v1, v12, v1, v11 bitop3:0xfe
+; GFX950-NEXT: v_sub_u16_e32 v11, 2, v10
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
+; GFX950-NEXT: v_bitop3_b16 v3, v9, s0, v3 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v12, vcc
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v14, v3
+; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
+; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v9
+; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
+; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s0 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v3, v14, v13 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v15
+; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
+; GFX950-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX950-NEXT: v_add_u16_e32 v3, v12, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
+; GFX950-NEXT: v_lshrrev_b32_e32 v12, 31, v0
+; GFX950-NEXT: v_lshlrev_b16_e32 v12, 7, v12
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v12, v3, v11 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 6, v9
+; GFX950-NEXT: v_and_b32_e32 v9, 63, v9
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v9, v11, v9, v14 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v9, v13, v9
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v9
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v10, v10, v11
+; GFX950-NEXT: v_add_u16_e32 v10, 6, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 3, v10
+; GFX950-NEXT: v_bitop3_b16 v9, v12, v9, v11 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v8 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v12, vcc
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v3, 8, v0
+; GFX950-NEXT: v_bitop3_b16 v0, v1, v3, s2 bitop3:0xec
+; GFX950-NEXT: v_lshrrev_b32_e32 v5, 8, v7
+; GFX950-NEXT: v_lshl_or_b32 v1, v2, 16, v3
+; GFX950-NEXT: v_lshrrev_b64 v[6:7], 24, v[6:7]
+; GFX950-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX950-NEXT: v_mov_b32_e32 v3, v6
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_fp8_v6f16:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v2.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v3.h, v2.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, 8, v2.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v4.h, v1.l
+; GFX1200-NEXT: v_sub_nc_u16 v5.l, 2, v3.l
+; GFX1200-NEXT: v_and_b16 v5.h, 0x3ff, v3.h
+; GFX1200-NEXT: v_and_b16 v6.l, v3.h, 63
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v14.l
+; GFX1200-NEXT: v_lshrrev_b16 v3.h, 6, v3.h
+; GFX1200-NEXT: v_min_u16 v5.l, v5.l, 15
+; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v5.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v5.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6.l
+; GFX1200-NEXT: v_sub_nc_u16 v9.h, 2, v7.l
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, v5.l, 1 clamp
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v14.l
+; GFX1200-NEXT: v_and_b16 v10.h, v5.h, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_min_u16 v9.h, v9.h, 15
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, v8.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v11.h, v5.l, v8.l
+; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v6.h
+; GFX1200-NEXT: v_or_b16 v10.h, v11.l, v10.h
+; GFX1200-NEXT: v_sub_nc_u16 v11.l, v9.h, 1 clamp
+; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
+; GFX1200-NEXT: v_and_b16 v10.l, v6.h, 63
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
+; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v10.h
+; GFX1200-NEXT: v_lshlrev_b16 v10.h, v11.l, 1
+; GFX1200-NEXT: v_and_b16 v9.l, v8.l, v9.l
+; GFX1200-NEXT: v_or_b16 v5.l, 0x400, v6.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v5.h, v3.h
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v10.h, -1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
+; GFX1200-NEXT: v_and_b16 v9.l, v11.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, v8.h, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
+; GFX1200-NEXT: v_and_b16 v5.h, v5.l, v5.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v10.l
+; GFX1200-NEXT: v_and_b16 v10.l, v6.l, 1
+; GFX1200-NEXT: v_and_b16 v4.l, 0x80, v4.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v5.h
+; GFX1200-NEXT: v_or_b16 v8.h, v12.l, v9.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v3.h
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v9.h, v5.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, s1
+; GFX1200-NEXT: v_and_b16 v8.l, v8.l, v8.h
+; GFX1200-NEXT: v_or_b16 v8.h, v13.l, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, v11.l, v5.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, 2, v4.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, v8.l, vcc_lo
+; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v12.l
+; GFX1200-NEXT: v_and_b16 v8.l, v9.l, 1
+; GFX1200-NEXT: v_mov_b16_e32 v12.l, v15.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v11.h, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, 6
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s0
+; GFX1200-NEXT: v_or_b16 v8.l, v12.l, v8.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v3.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.l
+; GFX1200-NEXT: v_and_b16 v5.l, v5.l, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, 8, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v6.l
+; GFX1200-NEXT: v_or_b16 v8.l, v4.l, v8.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v5.l, 0, v5.l, s1
+; GFX1200-NEXT: v_or_b16 v6.h, v4.l, v6.h
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v2.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1200-NEXT: v_or_b16 v3.l, v8.l, v3.h
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v9.l, v5.l
+; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v5.h
+; GFX1200-NEXT: v_min_u16 v5.h, v7.h, 15
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v1.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v2
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v3.h, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v7.l, v8.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, v5.h, 1 clamp
+; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v6.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, 7, v9.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, 8, s0
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v3.h, 6
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.l, 1
+; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v7.h
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v4.l, s1
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, s0
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v3.h
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_or_b16 v2.h, v8.h, v2.h
+; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v2.l
+; GFX1200-NEXT: v_or_b16 v9.l, v8.h, v9.l
+; GFX1200-NEXT: v_and_b16 v4.l, v9.h, v8.l
+; GFX1200-NEXT: v_or_b16 v2.l, v2.h, v5.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, v5.h, v9.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v1
+; GFX1200-NEXT: v_or_b16 v2.h, v9.l, v6.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0x7f, v3.l, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.l, v12.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.h
+; GFX1200-NEXT: v_and_b16 v3.h, v5.l, 1
+; GFX1200-NEXT: v_and_b16 v3.l, 0xff, v3.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_mov_b16_e32 v4.l, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.h, v2.l, s0
+; GFX1200-NEXT: v_and_b16 v2.h, v6.h, 63
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
+; GFX1200-NEXT: v_or_b16 v3.h, v4.l, v3.h
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, v7.l, v9.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v2.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 7, v7.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v8.h, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v14.l, v14.l
+; GFX1200-NEXT: v_and_b16 v2.h, v4.l, v3.h
+; GFX1200-NEXT: v_sub_nc_u16 v3.h, 2, v6.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
+; GFX1200-NEXT: v_and_b16 v4.l, v7.l, 1
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v12.l
+; GFX1200-NEXT: v_min_u16 v3.h, v3.h, 15
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v2.h, s0
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, 0x7f, v2.l, vcc_lo
+; GFX1200-NEXT: v_and_b16 v9.l, v5.h, 63
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, v3.h, 1 clamp
+; GFX1200-NEXT: v_or_b16 v4.l, v8.l, v4.l
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v5.l, v2.h
+; GFX1200-NEXT: v_and_b16 v5.l, 0x3ff, v5.h
+; GFX1200-NEXT: v_lshrrev_b16 v8.h, 8, v1.l
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.h, 1
+; GFX1200-NEXT: v_and_b16 v4.l, v6.h, v4.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.h
+; GFX1200-NEXT: v_or_b16 v6.h, 0x400, v5.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 7, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v7.l, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s0
+; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, s0
+; GFX1200-NEXT: v_lshrrev_b16 v9.h, v3.h, v6.h
+; GFX1200-NEXT: v_and_b16 v8.l, v6.h, v8.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.l
+; GFX1200-NEXT: v_and_b16 v8.h, 0x80, v8.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v7.h, v6.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 6, v5.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1200-NEXT: v_and_b16 v10.h, v5.l, 1
+; GFX1200-NEXT: v_or_b16 v7.l, v8.h, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, vcc_lo
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
+; GFX1200-NEXT: v_and_b16 v9.l, v9.h, 1
+; GFX1200-NEXT: v_or_b16 v2.h, v7.l, v2.h
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, v8.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v0.l
+; GFX1200-NEXT: v_or_b16 v8.l, v10.l, v9.l
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v13.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, 6
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v2.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.l
+; GFX1200-NEXT: v_or_b16 v7.h, v11.l, v10.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v11, 16, v0
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, v6.h, s0
+; GFX1200-NEXT: v_and_b16 v3.h, v5.h, v7.h
+; GFX1200-NEXT: v_lshlrev_b16 v5.h, 3, v4.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v4.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.h, v0.l
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v9.h, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v5.l, v3.h
+; GFX1200-NEXT: v_or_b16 v5.l, v8.h, v5.h
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v7.l
+; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v4.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v6.h
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.h
+; GFX1200-NEXT: v_or_b16 v4.l, v5.l, v4.l
+; GFX1200-NEXT: v_min_u16 v5.l, v5.h, 15
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v6.h, v6.h, 0, s1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v4.l, v2.h, s0
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, v5.l, 1 clamp
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v1.l
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v1
+; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v7.h
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, 8, s1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v8.h, s0
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v8.l
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v5.h, 1
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, 7, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, v5.h, v9.h
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v1.l, v1.l
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_or_b16 v1.h, v9.l, v1.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0x7f, v2.h, s0
+; GFX1200-NEXT: v_lshlrev_b16 v10.l, 3, v6.l
+; GFX1200-NEXT: v_and_b16 v4.l, v9.h, v8.l
+; GFX1200-NEXT: v_or_b16 v1.h, v1.h, v6.h
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, v5.l, v9.h
+; GFX1200-NEXT: v_and_b16 v2.h, 0xff, v2.h
+; GFX1200-NEXT: v_or_b16 v6.h, v9.l, v10.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.l
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v11.l
+; GFX1200-NEXT: v_and_b16 v4.l, v8.l, 1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v3.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v6.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.h, v11.l
+; GFX1200-NEXT: v_mov_b16_e32 v6.l, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_or_b16 v3.h, v6.l, v4.l
+; GFX1200-NEXT: v_sub_nc_u16 v4.l, 2, v6.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.h, v9.l, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.l, v11.l
+; GFX1200-NEXT: v_and_b16 v3.h, v5.h, v3.h
+; GFX1200-NEXT: v_min_u16 v1.h, v4.l, 15
+; GFX1200-NEXT: v_and_b16 v4.l, v4.h, 63
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v7.h
+; GFX1200-NEXT: v_and_b16 v9.l, v5.l, 63
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, 6, v4.h
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, v1.h, 1 clamp
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v4.l
+; GFX1200-NEXT: v_and_b16 v4.l, 0x3ff, v5.l
+; GFX1200-NEXT: v_and_b16 v8.h, v6.l, 1
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v5.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, v5.h, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.l
+; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v4.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, 7, v4.l
+; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
+; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v8.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s1
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v1.h, v9.h
+; GFX1200-NEXT: v_and_b16 v9.l, v4.l, 1
+; GFX1200-NEXT: v_and_b16 v7.h, v9.h, v7.h
+; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v8.h
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v13.l
+; GFX1200-NEXT: v_and_b16 v8.h, v10.h, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0, v3.h, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v7.h
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v6.l, v4.h
+; GFX1200-NEXT: v_or_b16 v7.h, v10.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, v5.h, v9.h
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v8.l, v3.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s1
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
+; GFX1200-NEXT: v_and_b16 v5.l, v5.l, v7.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v1.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v3.h
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v13.l
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v12.l, v12.l
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, v5.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s3
+; GFX1200-NEXT: v_or_b16 v6.l, v9.l, v8.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 7, v4.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7f, v1.l, s1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_and_b16 v5.l, v5.h, v6.l
+; GFX1200-NEXT: v_mov_b16_e32 v6.l, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s4
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s4
+; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, v5.l, s2
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v0.l
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v7.l, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, 8, s3
+; GFX1200-NEXT: v_add_nc_u16 v1.h, v10.h, v1.h
+; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, v8.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, 6
+; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v1.h
+; GFX1200-NEXT: v_or_b16 v0.h, v5.l, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.h, 6
+; GFX1200-NEXT: v_lshlrev_b16 v6.h, 3, v5.h
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 7, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, s2
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s2
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, 3, v6.l
+; GFX1200-NEXT: v_or_b16 v6.h, v5.l, v6.h
+; GFX1200-NEXT: v_or_b16 v0.h, v0.h, v3.h
+; GFX1200-NEXT: v_or_b16 v7.l, v7.h, v7.l
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v5.h
+; GFX1200-NEXT: v_or_b16 v8.l, v7.h, v8.l
+; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v4.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s2, 1, v6.l
+; GFX1200-NEXT: v_or_b16 v1.h, v7.l, v1.h
+; GFX1200-NEXT: v_or_b16 v2.h, v2.h, v1.l
+; GFX1200-NEXT: v_or_b16 v4.l, v8.l, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v3.h, v0.h, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v4.l, v1.h, s2
+; GFX1200-NEXT: v_or_b16 v4.l, v3.l, v2.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
+; GFX1200-NEXT: v_mov_b16_e32 v3.l, v2.h
+; GFX1200-NEXT: v_cndmask_b16 v0.l, v1.h, v7.h, s0
+; GFX1200-NEXT: v_cvt_u32_u16_e32 v1, v4.l
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v11.l, v11.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7f, v0.h, vcc_lo
+; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX1200-NEXT: v_or_b32_e32 v6, 0x7f7f0000, v1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, s0
+; GFX1200-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_lshrrev_b64 v[7:8], 24, v[5:6]
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v5, 8, v6
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v2.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX1200-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1200-NEXT: v_mov_b16_e32 v3.l, v7.l
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: to_fp8_v6f16:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v3.h, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v7.h, s0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v7.l, v2
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v3.l, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.h
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v7
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v7.l
+; GFX1250-TRUE16-NEXT: v_dual_lshlrev_b32 v6, 16, v1 :: v_dual_lshrrev_b32 v1, 8, v3
+; GFX1250-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[6:7]
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.l, v8.l
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_fp8_v6f16:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v0, v0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v4, v2
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v3, s0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v2, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v4
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX1250-FAKE16-NEXT: v_lshl_or_b32 v7, v3, 16, v5
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX1250-FAKE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[6:7]
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_dual_lshrrev_b32 v5, 8, v7 :: v_dual_mov_b32 v3, v8
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_v6f16:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v0, v0
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v6, v2
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v3, s0
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v2, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_and_b32_e32 v1, 0xffff, v0
+; GFX1310-NEXT: v_and_b32_e32 v5, 0xffff, v6
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1310-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX1310-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX1310-NEXT: v_lshl_or_b32 v5, v3, 16, v5
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX1310-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
+; GFX1310-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_lshrrev_b32 v5, 8, v5
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <6 x i8> @llvm.convert.to.arbitrary.fp.v6i8.v6f16(<6 x half> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
+ ret <6 x i8> %r
+}
+
+define <7 x i8> @to_fp8_v7f16(<7 x half> %x) {
+; GFX950-LABEL: to_fp8_v7f16:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v6, v3
+; GFX950-NEXT: v_sub_u16_e32 v8, 2, v6
+; GFX950-NEXT: v_frexp_mant_f16_e32 v4, v3
+; GFX950-NEXT: s_movk_i32 s0, 0x400
+; GFX950-NEXT: v_mov_b32_e32 v7, 0x3ff
+; GFX950-NEXT: v_min_u16_e32 v8, 15, v8
+; GFX950-NEXT: v_bitop3_b16 v5, v4, s0, v7 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v11, v8, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, v8, v5
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, v11, v5
+; GFX950-NEXT: v_lshlrev_b16_e64 v11, v11, 1
+; GFX950-NEXT: v_and_b32_e32 v12, 0x3ff, v4
+; GFX950-NEXT: v_add_u16_e32 v11, -1, v11
+; GFX950-NEXT: v_bitop3_b16 v11, v12, v11, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: v_and_b32_e32 v10, 1, v9
+; GFX950-NEXT: s_movk_i32 s1, 0x80
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v5, v11, v10 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
+; GFX950-NEXT: v_lshrrev_b16_e32 v10, 7, v12
+; GFX950-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX950-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v9, v5
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
+; GFX950-NEXT: v_and_b32_sdwa v9, v3, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_movk_i32 s2, 0xff
+; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v9, v5, v8 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, 6, v4
+; GFX950-NEXT: v_and_b32_e32 v4, 63, v4
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v8, v4, v11 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v4, v10, v4
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
+; GFX950-NEXT: v_mov_b32_e32 v10, 0x7f
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v6, v6, v8
+; GFX950-NEXT: v_add_u16_e32 v6, 6, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v8, 3, v6
+; GFX950-NEXT: v_bitop3_b16 v4, v9, v4, v8 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v6
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v6, v5, s0, v7 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
+; GFX950-NEXT: v_sub_u16_e32 v9, 2, v8
+; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
+; GFX950-NEXT: v_sub_u16_e64 v13, v9, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, v9, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, v13, v6
+; GFX950-NEXT: v_lshlrev_b16_e64 v13, v13, 1
+; GFX950-NEXT: v_and_b32_e32 v14, 0x3ff, v5
+; GFX950-NEXT: v_add_u16_e32 v13, -1, v13
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v3, v3
+; GFX950-NEXT: v_bitop3_b16 v13, v14, v13, s0 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v11
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v6, v13, v12 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX950-NEXT: v_add_u16_e32 v6, v11, v6
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v6
+; GFX950-NEXT: v_lshrrev_b32_e32 v11, 31, v3
+; GFX950-NEXT: v_lshlrev_b16_e32 v12, 7, v11
+; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v12, v6, v9 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v5
+; GFX950-NEXT: v_and_b32_e32 v5, 63, v5
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v14
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v5
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v11
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v9, v5, v13 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v5, v11, v5
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
+; GFX950-NEXT: v_mov_b32_e32 v11, 0
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v8, v8, v9
+; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v9, 3, v8
+; GFX950-NEXT: v_bitop3_b16 v5, v12, v5, v9 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v3, v11 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v3, v3 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v10, v5, vcc
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v5, v2
+; GFX950-NEXT: v_lshlrev_b16_e32 v3, 8, v3
+; GFX950-NEXT: v_sub_u16_e32 v8, 2, v5
+; GFX950-NEXT: v_bitop3_b16 v6, v4, v3, s2 bitop3:0xec
+; GFX950-NEXT: v_frexp_mant_f16_e32 v3, v2
+; GFX950-NEXT: v_min_u16_e32 v8, 15, v8
+; GFX950-NEXT: v_bitop3_b16 v4, v3, s0, v7 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v13, v8, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, v8, v4
+; GFX950-NEXT: v_lshrrev_b16_e32 v4, v13, v4
+; GFX950-NEXT: v_lshlrev_b16_e64 v13, v13, 1
+; GFX950-NEXT: v_and_b32_e32 v14, 0x3ff, v3
+; GFX950-NEXT: v_add_u16_e32 v13, -1, v13
+; GFX950-NEXT: v_bitop3_b16 v13, v14, v13, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: v_and_b32_e32 v12, 1, v9
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v4, v13, v12 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, 7, v14
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX950-NEXT: v_add_u16_e32 v4, v9, v4
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
+; GFX950-NEXT: v_and_b32_sdwa v9, v2, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v9, v4, v8 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, 6, v3
+; GFX950-NEXT: v_and_b32_e32 v3, 63, v3
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v8, v3, v13 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v3, v12, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v5, v8
+; GFX950-NEXT: v_add_u16_e32 v5, 6, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v8, 3, v5
+; GFX950-NEXT: v_bitop3_b16 v3, v9, v3, v8 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v5
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v5, v4, s0, v7 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc
+; GFX950-NEXT: v_sub_u16_e32 v9, 2, v8
+; GFX950-NEXT: v_min_u16_e32 v9, 15, v9
+; GFX950-NEXT: v_sub_u16_e64 v14, v9, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, v9, v5
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, v14, v5
+; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
+; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v4
+; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v2, v2
+; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s0 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v5, v14, v13 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v15
+; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
+; GFX950-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v12, v5
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
+; GFX950-NEXT: v_lshrrev_b32_e32 v12, 31, v2
+; GFX950-NEXT: v_lshlrev_b16_e32 v12, 7, v12
+; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v12, v5, v9 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 6, v4
+; GFX950-NEXT: v_and_b32_e32 v4, 63, v4
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v9, v4, v14 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v4, v13, v4
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v4
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v8, v8, v9
+; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v9, 3, v8
+; GFX950-NEXT: v_bitop3_b16 v4, v12, v4, v9 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v2, v11 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v5, v1
+; GFX950-NEXT: v_sub_u16_e32 v8, 2, v5
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v2, v2 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: v_min_u16_e32 v8, 15, v8
+; GFX950-NEXT: v_sub_u16_e64 v14, v8, 1 clamp
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v10, v4, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v2, 8, v2
+; GFX950-NEXT: v_bitop3_b16 v4, v3, v2, s2 bitop3:0xec
+; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; GFX950-NEXT: v_or_b32_sdwa v9, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX950-NEXT: v_frexp_mant_f16_e32 v2, v1
+; GFX950-NEXT: v_bitop3_b16 v3, v2, s0, v7 bitop3:0xec
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, v8, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v14, v3
+; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
+; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v2
+; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v3, v14, v13 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v8
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v15
+; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
+; GFX950-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX950-NEXT: v_add_u16_e32 v3, v12, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
+; GFX950-NEXT: v_and_b32_sdwa v12, v1, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v12, v3, v8 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, 6, v2
+; GFX950-NEXT: v_and_b32_e32 v2, 63, v2
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v2
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v8, v2, v14 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v2, v13, v2
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v2
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v5, v8
+; GFX950-NEXT: v_add_u16_e32 v5, 6, v5
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v8, 3, v5
+; GFX950-NEXT: v_bitop3_b16 v2, v12, v2, v8 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v5
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v5, v3, s0, v7 bitop3:0xec
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc
+; GFX950-NEXT: v_sub_u16_e32 v12, 2, v8
+; GFX950-NEXT: v_min_u16_e32 v12, 15, v12
+; GFX950-NEXT: v_sub_u16_e64 v15, v12, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, v12, v5
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, v15, v5
+; GFX950-NEXT: v_lshlrev_b16_e64 v15, v15, 1
+; GFX950-NEXT: v_and_b32_e32 v16, 0x3ff, v3
+; GFX950-NEXT: v_add_u16_e32 v15, -1, v15
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v1, v1
+; GFX950-NEXT: v_bitop3_b16 v15, v16, v15, s0 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v15
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v5, v15, v14 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: v_lshrrev_b16_e32 v14, 7, v16
+; GFX950-NEXT: v_and_b32_e32 v15, 1, v14
+; GFX950-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v13, v5
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v5
+; GFX950-NEXT: v_lshrrev_b32_e32 v13, 31, v1
+; GFX950-NEXT: v_lshlrev_b16_e32 v13, 7, v13
+; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v13, v5, v12 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, 6, v3
+; GFX950-NEXT: v_and_b32_e32 v3, 63, v3
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v12, v3, v15 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v3, v14, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v8, v8, v12
+; GFX950-NEXT: v_add_u16_e32 v8, 6, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v12, 3, v8
+; GFX950-NEXT: v_bitop3_b16 v3, v13, v3, v12 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v8
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v12, v0
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v1, v11 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: v_lshrrev_b32_e32 v5, 8, v9
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: v_sub_u16_e32 v13, 2, v12
+; GFX950-NEXT: v_min_u16_e32 v13, 15, v13
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v1, 8, v1
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v1, s2 bitop3:0xec
+; GFX950-NEXT: v_frexp_mant_f16_e32 v1, v0
+; GFX950-NEXT: v_bitop3_b16 v3, v1, s0, v7 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v16, v13, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v14, v13, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v16, v3
+; GFX950-NEXT: v_lshlrev_b16_e64 v16, v16, 1
+; GFX950-NEXT: v_and_b32_e32 v17, 0x3ff, v1
+; GFX950-NEXT: v_add_u16_e32 v16, -1, v16
+; GFX950-NEXT: v_bitop3_b16 v16, v17, v16, s0 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v16
+; GFX950-NEXT: v_and_b32_e32 v15, 1, v14
+; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX950-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v3, v16, v15 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: v_lshrrev_b16_e32 v15, 7, v17
+; GFX950-NEXT: v_and_b32_e32 v16, 1, v15
+; GFX950-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX950-NEXT: v_add_u16_e32 v3, v14, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
+; GFX950-NEXT: v_and_b32_sdwa v14, v0, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_lshrrev_b64 v[8:9], 24, v[8:9]
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v14, v3, v13 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, 6, v1
+; GFX950-NEXT: v_and_b32_e32 v1, 63, v1
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v13, v1, v16 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v1, v15, v1
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v12, v12, v13
+; GFX950-NEXT: v_add_u16_e32 v12, 6, v12
+; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v13, 3, v12
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v12
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v12, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v1, v14, v1, v13 bitop3:0xfe
+; GFX950-NEXT: v_sub_u16_e32 v13, 2, v12
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_min_u16_e32 v13, 15, v13
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
+; GFX950-NEXT: v_bitop3_b16 v7, v3, s0, v7 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v16, v13, 1 clamp
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v14, vcc
+; GFX950-NEXT: v_lshrrev_b16_e32 v14, v13, v7
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, v16, v7
+; GFX950-NEXT: v_lshlrev_b16_e64 v16, v16, 1
+; GFX950-NEXT: v_and_b32_e32 v17, 0x3ff, v3
+; GFX950-NEXT: v_add_u16_e32 v16, -1, v16
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
+; GFX950-NEXT: v_bitop3_b16 v16, v17, v16, s0 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v15, 1, v14
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v16
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v7, v16, v15 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: v_lshrrev_b16_e32 v15, 7, v17
+; GFX950-NEXT: v_and_b32_e32 v16, 1, v15
+; GFX950-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
+; GFX950-NEXT: v_add_u16_e32 v7, v14, v7
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v7
+; GFX950-NEXT: v_lshrrev_b32_e32 v14, 31, v0
+; GFX950-NEXT: v_lshlrev_b16_e32 v14, 7, v14
+; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 8, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v14, v7, v13 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, 6, v3
+; GFX950-NEXT: v_and_b32_e32 v3, 63, v3
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v13, v3, v16 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_e32 v3, v15, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 7, v3
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v12, v12, v13
+; GFX950-NEXT: v_add_u16_e32 v12, 6, v12
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v13, 3, v12
+; GFX950-NEXT: v_bitop3_b16 v3, v14, v3, v13 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v12
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v11 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v14, vcc
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v10, v3, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v3, 8, v0
+; GFX950-NEXT: v_bitop3_b16 v0, v1, v3, s2 bitop3:0xec
+; GFX950-NEXT: v_lshl_or_b32 v1, v2, 16, v3
+; GFX950-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX950-NEXT: v_mov_b32_e32 v3, v8
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_fp8_v7f16:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v4.l, v3.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.h, v3.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v13, 16, v3
+; GFX1200-NEXT: v_lshrrev_b32_e32 v14, 31, v3
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v3.l
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v4.l
+; GFX1200-NEXT: v_and_b16 v6.l, v4.h, 63
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.h, v13.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v7.l, v13.l
+; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
+; GFX1200-NEXT: v_min_u16 v3.h, v5.h, 15
+; GFX1200-NEXT: v_and_b16 v5.h, 0x3ff, v4.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v6.l
+; GFX1200-NEXT: v_sub_nc_u16 v9.l, 2, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, 6, v4.h
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, v3.h, 1 clamp
+; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v5.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v5.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
+; GFX1200-NEXT: v_min_u16 v9.l, v9.l, 15
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, v6.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v3.h, v8.l
+; GFX1200-NEXT: v_and_b16 v10.l, v5.h, 1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v3.h
+; GFX1200-NEXT: v_sub_nc_u16 v3.h, v9.l, 1 clamp
+; GFX1200-NEXT: v_add_nc_u16 v8.h, v8.h, -1
+; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v7.l
+; GFX1200-NEXT: v_or_b16 v10.l, v11.l, v10.l
+; GFX1200-NEXT: v_and_b16 v9.h, v7.l, 63
+; GFX1200-NEXT: v_lshlrev_b16 v11.l, v3.h, 1
+; GFX1200-NEXT: v_and_b16 v8.h, v8.l, v8.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 6, v7.l
+; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v10.l
+; GFX1200-NEXT: v_and_b16 v10.l, v10.h, 1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s3, 0, v9.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v8.h
+; GFX1200-NEXT: v_or_b16 v8.h, 0x400, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v5.h, v4.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v6.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.h, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s2
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v11.l, -1
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v4.h
+; GFX1200-NEXT: v_lshrrev_b16 v3.h, v3.h, v8.h
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v3.l
+; GFX1200-NEXT: v_or_b16 v8.l, v12.l, v10.l
+; GFX1200-NEXT: v_and_b16 v6.h, v8.h, v6.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s2
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s3
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s3, 0, v9.l
+; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, v9.l, v8.h
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v3.l, v3.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v2.l
+; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v6.l, s1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, v10.l
+; GFX1200-NEXT: v_and_b16 v6.h, v5.h, 1
+; GFX1200-NEXT: v_and_b16 v9.l, v8.l, 1
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v10.h, v6.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, 6
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s2
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v6.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v9.h, 0, 8, s1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v9.l
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v4.l
+; GFX1200-NEXT: v_or_b16 v6.h, v11.l, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s1
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s1, 1, v4.l
+; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v8.h
+; GFX1200-NEXT: v_or_b16 v8.h, v5.l, v9.l
+; GFX1200-NEXT: v_or_b16 v9.l, v5.l, v9.h
+; GFX1200-NEXT: v_and_b16 v6.h, v7.l, v6.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0, v3.h, s3
+; GFX1200-NEXT: v_or_b16 v4.l, v8.h, v4.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v4.h, v9.l, v6.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.l, 2, v3.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v8.l, v3.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v2.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, v4.h, s1
+; GFX1200-NEXT: v_min_u16 v4.h, v6.l, 15
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v5.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v3.h
+; GFX1200-NEXT: v_and_b16 v9.h, v6.h, 63
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, v5.l, vcc_lo
+; GFX1200-NEXT: v_sub_nc_u16 v6.l, v4.h, 1 clamp
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s1
+; GFX1200-NEXT: v_lshlrev_b16 v5.l, 7, v14.l
+; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s2
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, v6.l, 1
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, s2
+; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, s1
+; GFX1200-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.h, v7.l
+; GFX1200-NEXT: v_or_b16 v7.h, v5.l, v8.l
+; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v8.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v4.l, 0x7f, v4.l, s0
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, 6
+; GFX1200-NEXT: v_or_b16 v3.h, v7.h, v3.h
+; GFX1200-NEXT: v_and_b16 v7.h, v8.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v10.l, v4.h, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.l, v8.l
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v7.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v8.h
+; GFX1200-NEXT: v_and_b16 v4.l, 0xff, v4.l
+; GFX1200-NEXT: v_or_b16 v8.h, v5.l, v9.l
+; GFX1200-NEXT: v_and_b16 v9.l, v10.l, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9.h
+; GFX1200-NEXT: v_and_b16 v9.h, v7.h, 1
+; GFX1200-NEXT: v_or_b16 v5.h, v8.h, v5.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v7.l
+; GFX1200-NEXT: v_or_b16 v7.l, v11.l, v9.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v9.l, v14.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v8.h, v12.l, v9.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v5.h, v3.h, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v13.l
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v9.l
+; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v7.l
+; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
+; GFX1200-NEXT: v_lshrrev_b16 v9.h, 8, v2.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v5.l, vcc_lo
+; GFX1200-NEXT: v_min_u16 v4.h, v5.h, 15
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, v6.l, s0
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v7.h, v6.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v14.l
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v13.l, v13.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, v4.h, 1 clamp
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v10.l, v5.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v5.l
+; GFX1200-NEXT: v_and_b16 v7.l, 0x3ff, v6.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7f, v3.h, vcc_lo
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, v6.h, 1
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
+; GFX1200-NEXT: v_or_b16 v8.h, 0x400, v7.l
+; GFX1200-NEXT: v_and_b16 v10.l, v6.l, 63
+; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, vcc_lo
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v4.h, v8.h
+; GFX1200-NEXT: v_and_b16 v7.h, v8.h, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 7, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, 6
+; GFX1200-NEXT: v_and_b16 v9.h, 0x80, v9.h
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 3, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v8.h
+; GFX1200-NEXT: v_or_b16 v8.l, v9.h, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v10.l
+; GFX1200-NEXT: v_and_b16 v10.l, v10.h, 1
+; GFX1200-NEXT: v_and_b16 v11.h, v7.l, 1
+; GFX1200-NEXT: v_or_b16 v7.h, v9.h, v7.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_or_b16 v10.l, v11.l, v10.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.h
+; GFX1200-NEXT: v_or_b16 v5.l, v7.h, v5.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.h, v1.l
+; GFX1200-NEXT: v_or_b16 v11.l, v12.l, v11.h
+; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v10.l
+; GFX1200-NEXT: v_or_b16 v5.h, v8.l, v5.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v13, 16, v1
+; GFX1200-NEXT: v_sub_nc_u16 v3.l, 2, v7.h
+; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v11.l
+; GFX1200-NEXT: v_lshlrev_b16 v3.h, 8, v3.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, v5.h, s0
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v2.l
+; GFX1200-NEXT: v_min_u16 v3.l, v3.l, 15
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.l, v6.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v6.h, vcc_lo
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, v9.h, s0
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, v3.l, 1 clamp
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v10.h, v6.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v1.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 31, v2
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, v6.h, 1
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v5.h
+; GFX1200-NEXT: v_lshlrev_b16 v10.l, 7, v10.l
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v8.l
+; GFX1200-NEXT: v_and_b16 v8.l, 0x3ff, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v8.h, v8.h, -1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, s1
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v9.l, v7.l
+; GFX1200-NEXT: v_or_b16 v9.l, 0x400, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, s1
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, 7, v8.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v2.h, 6
+; GFX1200-NEXT: v_and_b16 v8.h, v9.l, v8.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v7.l, v10.l, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v3.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v9.l
+; GFX1200-NEXT: v_lshlrev_b16 v9.h, 3, v2.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v2.h
+; GFX1200-NEXT: v_and_b16 v2.h, v6.l, 63
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
+; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v9.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v2.l
+; GFX1200-NEXT: v_or_b16 v2.l, v7.l, v5.h
+; GFX1200-NEXT: v_and_b16 v5.h, v10.h, 1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v2.h
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v11.l
+; GFX1200-NEXT: v_or_b16 v4.h, v8.h, v4.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v5.l, 0x7f, v5.l, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s1
+; GFX1200-NEXT: v_or_b16 v5.h, v7.l, v5.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v13.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v3.l
+; GFX1200-NEXT: v_and_b16 v3.l, v8.l, 1
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v4.h, v2.l, s0
+; GFX1200-NEXT: v_and_b16 v2.h, v6.h, v5.h
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v7.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.h, v13.l
+; GFX1200-NEXT: v_or_b16 v3.l, v9.l, v3.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, vcc_lo
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v2.h, s1
+; GFX1200-NEXT: v_min_u16 v5.h, v5.h, 15
+; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v4.h
+; GFX1200-NEXT: v_and_b16 v3.l, v6.l, v3.l
+; GFX1200-NEXT: v_and_b16 v10.l, v4.h, 63
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v10.h, v2.h
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, v5.h, 1 clamp
+; GFX1200-NEXT: v_or_b16 v6.l, 0x400, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v8.l, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v8.h, 7, v8.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.h
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, v6.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v5.h, v6.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v9.h, 8, v1.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s0
+; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
+; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, s0
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_and_b16 v11.h, v8.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, 6, v4.h
+; GFX1200-NEXT: v_and_b16 v9.l, v6.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.h, v6.l
+; GFX1200-NEXT: v_and_b16 v9.h, 0x80, v9.h
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v11.l
+; GFX1200-NEXT: v_or_b16 v8.l, v9.h, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v10.l
+; GFX1200-NEXT: v_and_b16 v10.l, v10.h, 1
+; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, v9.l
+; GFX1200-NEXT: v_or_b16 v2.h, v8.l, v2.h
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, 6
+; GFX1200-NEXT: v_or_b16 v9.l, v11.l, v10.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_mov_b16_e32 v12.l, v15.l
+; GFX1200-NEXT: v_lshlrev_b16 v5.h, 3, v7.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v9.l
+; GFX1200-NEXT: v_or_b16 v6.h, v12.l, v11.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v5.h, v9.h, v5.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v6.l, s0
+; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v6.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.h, v0.l
+; GFX1200-NEXT: v_or_b16 v3.l, v5.h, v3.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v7.h
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v10.h, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v8.h, v4.h
+; GFX1200-NEXT: v_sub_nc_u16 v8.l, 2, v6.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v7.h, v0.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v3.l, v2.h, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v6.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
+; GFX1200-NEXT: v_min_u16 v5.h, v8.l, 15
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v1.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, v5.h, 1 clamp
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v9.h, s0
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v1.l, v1.l
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, v8.h, 1
+; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 31, v1
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, 8, s1
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v14.l, v14.l
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, v8.l
+; GFX1200-NEXT: v_and_b16 v8.l, 0x3ff, v7.h
+; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
+; GFX1200-NEXT: v_lshlrev_b16 v10.l, 7, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0x7f, v2.h, s0
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, 6
+; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, 7, v8.l
+; GFX1200-NEXT: v_or_b16 v1.h, v10.l, v1.h
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v12.l
+; GFX1200-NEXT: v_lshlrev_b16 v11.l, 3, v7.l
+; GFX1200-NEXT: v_and_b16 v3.l, v10.h, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v5.h, v10.h
+; GFX1200-NEXT: v_or_b16 v1.h, v1.h, v6.l
+; GFX1200-NEXT: v_and_b16 v9.h, v8.l, 1
+; GFX1200-NEXT: v_or_b16 v6.l, v10.l, v11.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
+; GFX1200-NEXT: v_and_b16 v2.h, 0xff, v2.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_or_b16 v3.l, v6.l, v4.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v7.l
+; GFX1200-NEXT: v_and_b16 v4.h, v9.l, 1
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v12.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_mov_b16_e32 v6.l, v11.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v3.l, v1.h, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v13.l
+; GFX1200-NEXT: v_or_b16 v3.l, v6.l, v4.h
+; GFX1200-NEXT: v_sub_nc_u16 v4.h, 2, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, v8.h, v10.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.h, v10.l, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v12.l
+; GFX1200-NEXT: v_min_u16 v1.h, v4.h, 15
+; GFX1200-NEXT: v_and_b16 v3.l, v6.l, v3.l
+; GFX1200-NEXT: v_and_b16 v4.h, v7.h, 63
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, 6, v7.h
+; GFX1200-NEXT: v_and_b16 v10.l, v5.h, 63
+; GFX1200-NEXT: v_sub_nc_u16 v6.l, v1.h, 1 clamp
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0, v3.l, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v4.h
+; GFX1200-NEXT: v_and_b16 v4.h, 0x3ff, v5.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 6, v5.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, v6.l, 1
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v9.l, v3.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s2
+; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v4.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v10.l
+; GFX1200-NEXT: v_add_nc_u16 v8.h, v8.h, -1
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, 7, v4.h
+; GFX1200-NEXT: v_or_b16 v9.h, v11.l, v9.h
+; GFX1200-NEXT: v_lshrrev_b16 v11.h, v1.h, v10.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s2
+; GFX1200-NEXT: v_and_b16 v8.h, v10.h, v8.h
+; GFX1200-NEXT: v_and_b16 v10.l, v4.h, 1
+; GFX1200-NEXT: v_and_b16 v7.h, v7.h, v9.h
+; GFX1200-NEXT: v_and_b16 v9.h, v11.h, 1
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v14.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v8.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.l, v10.h
+; GFX1200-NEXT: v_add_nc_u16 v7.h, v8.l, v7.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s3, 0, v1.h
+; GFX1200-NEXT: v_or_b16 v8.h, v11.l, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s2
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 7, v3.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v7.h
+; GFX1200-NEXT: v_cmp_o_f16_e64 s2, v13.l, v13.l
+; GFX1200-NEXT: v_and_b16 v5.h, v5.h, v8.h
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v14.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s4
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v7.h, v7.h, 0, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7f, v1.l, s2
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, v5.h
+; GFX1200-NEXT: v_or_b16 v8.l, v10.l, v9.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s5, 7, v4.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_and_b16 v5.h, v6.l, v8.l
+; GFX1200-NEXT: v_mov_b16_e32 v6.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v0
+; GFX1200-NEXT: v_or_b16 v2.h, v2.h, v1.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s5
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, v5.h, s3
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 8, v0.l
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.h, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, 8, s4
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, v8.l
+; GFX1200-NEXT: v_add_nc_u16 v1.h, v11.h, v1.h
+; GFX1200-NEXT: v_and_b16 v5.h, 0x80, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, 7, v9.l
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s5
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v1.h
+; GFX1200-NEXT: v_or_b16 v0.h, v5.h, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v7.l, 6
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, 3, v6.l
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v6.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, s3
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s3
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v6.h
+; GFX1200-NEXT: v_or_b16 v7.l, v5.h, v7.l
+; GFX1200-NEXT: v_or_b16 v0.h, v0.h, v3.l
+; GFX1200-NEXT: v_or_b16 v8.l, v8.h, v8.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s3, 1, v6.h
+; GFX1200-NEXT: v_or_b16 v9.l, v8.h, v9.l
+; GFX1200-NEXT: v_or_b16 v3.l, v7.l, v7.h
+; GFX1200-NEXT: v_and_b16 v1.l, 0xff, v5.l
+; GFX1200-NEXT: v_or_b16 v1.h, v8.l, v1.h
+; GFX1200-NEXT: v_mov_b16_e32 v5.l, v2.h
+; GFX1200-NEXT: v_or_b16 v4.h, v9.l, v4.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v3.l, v0.h, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0.l
+; GFX1200-NEXT: v_or_b16 v6.h, v4.l, v3.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v4.h, v1.h, s3
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v5.h, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
+; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX1200-NEXT: v_cndmask_b16 v0.l, v1.h, v8.h, s0
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0x7f, v2.l, s1
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v12.l, v12.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7f, v0.h, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, s0
+; GFX1200-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_or_b16 v6.l, v1.l, v1.h
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
+; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v2.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX1200-NEXT: v_lshrrev_b32_e32 v5, 8, v6
+; GFX1200-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1200-NEXT: v_mov_b16_e32 v4.l, v6.l
+; GFX1200-NEXT: v_mov_b16_e32 v6.l, v6.h
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: to_fp8_v7f16:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v4.h, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v7.h, v3
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v7.l, v2
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v4.l, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v1.l, v4.h
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.h
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_dual_lshrrev_b32 v5, 8, v7 :: v_dual_lshlrev_b32 v6, 16, v1
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v4
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v7.l
+; GFX1250-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[6:7]
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, v7.h
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.l, v8.l
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_fp8_v7f16:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v4, v2
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v6, v3
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v2, v1
+; GFX1250-FAKE16-NEXT: v_cvt_pk_fp8_f16_e64 v0, v0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v4
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_lshl_or_b32 v9, v6, 16, v1
+; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX1250-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v3
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v9
+; GFX1250-FAKE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[8:9]
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_dual_lshrrev_b32 v1, 8, v1 :: v_dual_mov_b32 v3, v8
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_fp8_v7f16:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v7, v2
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v0, v0
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v6, v3
+; GFX1310-NEXT: v_cvt_pk_fp8_f16_e32 v2, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_and_b32_e32 v1, 0xffff, v7
+; GFX1310-NEXT: v_and_b32_e32 v3, 0xffff, v0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_lshl_or_b32 v4, v6, 16, v1
+; GFX1310-NEXT: v_lshl_or_b32 v1, v2, 16, v3
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_dual_lshlrev_b32 v3, 16, v2 :: v_dual_lshrrev_b32 v5, 8, v4
+; GFX1310-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1310-NEXT: v_lshrrev_b64 v[3:4], 24, v[3:4]
+; GFX1310-NEXT: v_mov_b32_e32 v4, v7
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <7 x i8> @llvm.convert.to.arbitrary.fp.v7i8.v7f16(<7 x half> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
+ ret <7 x i8> %r
+}
+
+define <5 x i8> @to_bf8_v5f16(<5 x half> %x) {
+; GFX950-LABEL: to_bf8_v5f16:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v6, v2
+; GFX950-NEXT: v_sub_u16_e32 v7, -5, v6
+; GFX950-NEXT: v_frexp_mant_f16_e32 v4, v2
+; GFX950-NEXT: s_movk_i32 s2, 0x400
+; GFX950-NEXT: v_mov_b32_e32 v3, 0x3ff
+; GFX950-NEXT: v_min_u16_e32 v7, 15, v7
+; GFX950-NEXT: v_bitop3_b16 v5, v4, s2, v3 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v10, v7, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, v7, v5
+; GFX950-NEXT: v_lshrrev_b16_e32 v5, v10, v5
+; GFX950-NEXT: v_lshlrev_b16_e64 v10, v10, 1
+; GFX950-NEXT: v_and_b32_e32 v11, 0x3ff, v4
+; GFX950-NEXT: v_add_u16_e32 v10, -1, v10
+; GFX950-NEXT: v_bitop3_b16 v10, v11, v10, s2 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v10
+; GFX950-NEXT: v_and_b32_e32 v9, 1, v8
+; GFX950-NEXT: s_movk_i32 s4, 0x7c
+; GFX950-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v5, v10, v9 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v7
+; GFX950-NEXT: v_lshrrev_b16_e32 v9, 7, v4
+; GFX950-NEXT: v_and_b32_e32 v4, 0x7f, v4
+; GFX950-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GFX950-NEXT: v_add_u16_e32 v5, v8, v5
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v5
+; GFX950-NEXT: v_lshrrev_b16_e32 v8, 8, v2
+; GFX950-NEXT: v_and_b32_e32 v10, 0x80, v8
+; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v7, 0, 4, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v10, v5, v7 bitop3:0xfe
+; GFX950-NEXT: v_mov_b32_e32 v5, 1
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
+; GFX950-NEXT: v_and_b32_sdwa v12, v11, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_movk_i32 s3, 0x204
+; GFX950-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v4, v9, v4, v12 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_sdwa v4, v11, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v4
+; GFX950-NEXT: s_movk_i32 s5, 0xff
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v6, v6, v9
+; GFX950-NEXT: v_add_u16_e32 v6, 14, v6
+; GFX950-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v9, 2, v6
+; GFX950-NEXT: v_bitop3_b16 v9, v10, v4, v9 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v6
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 30, v6
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v4
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 30, v6
+; GFX950-NEXT: v_mov_b32_e32 v9, 0x80
+; GFX950-NEXT: v_bitop3_b16 v4, v8, s4, v9 bitop3:0xec
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v7, v4, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
+; GFX950-NEXT: v_mov_b32_e32 v8, 0x7e
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v10, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_cmp_class_f16_e64 vcc, v2, s3
+; GFX950-NEXT: v_sub_u16_e32 v11, -5, v10
+; GFX950-NEXT: v_min_u16_e32 v11, 15, v11
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v6, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v7, v6, s2, v3 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v14, v11, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, v11, v7
+; GFX950-NEXT: v_lshrrev_b16_e32 v7, v14, v7
+; GFX950-NEXT: v_lshlrev_b16_e64 v14, v14, 1
+; GFX950-NEXT: v_and_b32_e32 v15, 0x3ff, v6
+; GFX950-NEXT: v_add_u16_e32 v14, -1, v14
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v2, v2
+; GFX950-NEXT: v_bitop3_b16 v14, v15, v14, s2 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v13, 1, v12
+; GFX950-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v14
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v7, v14, v13 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v11
+; GFX950-NEXT: v_and_b32_sdwa v13, v15, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
+; GFX950-NEXT: v_add_u16_e32 v7, v12, v7
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v7
+; GFX950-NEXT: v_lshrrev_b32_e32 v12, 31, v2
+; GFX950-NEXT: v_lshlrev_b16_e32 v12, 7, v12
+; GFX950-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 4, vcc
+; GFX950-NEXT: v_bitop3_b16 v7, v12, v7, v11 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, 7, v6
+; GFX950-NEXT: v_and_b32_e32 v6, 0x7f, v6
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v11, v6, v13 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_sdwa v6, v15, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v10, v10, v11
+; GFX950-NEXT: v_add_u16_e32 v10, 14, v10
+; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 2, v10
+; GFX950-NEXT: v_bitop3_b16 v11, v12, v6, v11 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v10
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 30, v10
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v6
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 30, v10
+; GFX950-NEXT: v_or_b32_e32 v6, 0x7c, v12
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_mov_b32_e32 v10, 0
+; GFX950-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v2, v10 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v11, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc
+; GFX950-NEXT: v_cmp_class_f16_sdwa s[0:1], v2, s3 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v2, v2 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: v_sub_u16_e32 v12, -5, v11
+; GFX950-NEXT: v_cndmask_b32_e64 v6, v7, v6, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v8, v6, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v2, 8, v2
+; GFX950-NEXT: v_bitop3_b16 v4, v4, v2, s5 bitop3:0xec
+; GFX950-NEXT: v_frexp_mant_f16_e32 v2, v1
+; GFX950-NEXT: v_min_u16_e32 v12, 15, v12
+; GFX950-NEXT: v_bitop3_b16 v6, v2, s2, v3 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v15, v12, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, v12, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v6, v15, v6
+; GFX950-NEXT: v_lshlrev_b16_e64 v15, v15, 1
+; GFX950-NEXT: v_and_b32_e32 v16, 0x3ff, v2
+; GFX950-NEXT: v_add_u16_e32 v15, -1, v15
+; GFX950-NEXT: v_bitop3_b16 v15, v16, v15, s2 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v15
+; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
+; GFX950-NEXT: s_mov_b32 s0, 0x7e7e0000
+; GFX950-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v6, v15, v14 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: v_and_b32_sdwa v15, v16, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_or_b32_sdwa v7, v4, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX950-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX950-NEXT: v_add_u16_e32 v6, v13, v6
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v6
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, 8, v1
+; GFX950-NEXT: v_and_b32_e32 v14, 0x80, v13
+; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 4, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v14, v6, v12 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, 7, v2
+; GFX950-NEXT: v_and_b32_e32 v2, 0x7f, v2
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v2
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v2, v12, v2, v15 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v2
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v11, v11, v12
+; GFX950-NEXT: v_add_u16_e32 v11, 14, v11
+; GFX950-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v12, 2, v11
+; GFX950-NEXT: v_bitop3_b16 v12, v14, v2, v12 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v11
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 30, v11
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v2
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 30, v11
+; GFX950-NEXT: v_bitop3_b16 v2, v13, s4, v9 bitop3:0xec
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v12, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_sub_u16_e32 v13, -5, v12
+; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc
+; GFX950-NEXT: v_cmp_class_f16_e64 vcc, v1, s3
+; GFX950-NEXT: v_min_u16_e32 v13, 15, v13
+; GFX950-NEXT: v_sub_u16_e64 v16, v13, 1 clamp
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v11, v6, s2, v3 bitop3:0xec
+; GFX950-NEXT: v_lshrrev_b16_e32 v14, v13, v11
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, v16, v11
+; GFX950-NEXT: v_lshlrev_b16_e64 v16, v16, 1
+; GFX950-NEXT: v_and_b32_e32 v17, 0x3ff, v6
+; GFX950-NEXT: v_add_u16_e32 v16, -1, v16
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v1, v1
+; GFX950-NEXT: v_bitop3_b16 v16, v17, v16, s2 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v15, 1, v14
+; GFX950-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v16
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v11, v11, v16, v15 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: v_and_b32_sdwa v15, v17, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc
+; GFX950-NEXT: v_add_u16_e32 v11, v14, v11
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v11
+; GFX950-NEXT: v_lshrrev_b32_e32 v14, 31, v1
+; GFX950-NEXT: v_lshlrev_b16_e32 v14, 7, v14
+; GFX950-NEXT: v_cndmask_b32_e64 v11, v11, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 4, vcc
+; GFX950-NEXT: v_bitop3_b16 v11, v14, v11, v13 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v6
+; GFX950-NEXT: v_and_b32_e32 v6, 0x7f, v6
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v6, v13, v6, v15 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_sdwa v6, v17, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v6
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v12, v12, v13
+; GFX950-NEXT: v_add_u16_e32 v12, 14, v12
+; GFX950-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v13, 2, v12
+; GFX950-NEXT: v_bitop3_b16 v13, v14, v6, v13 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v12
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 30, v12
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v6
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 30, v12
+; GFX950-NEXT: v_or_b32_e32 v6, 0x7c, v14
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v11, v11, v6, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v1, v10 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v12, v0
+; GFX950-NEXT: v_sub_u16_e32 v13, -5, v12
+; GFX950-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc
+; GFX950-NEXT: v_cmp_class_f16_sdwa s[0:1], v1, s3 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v1, v1 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: v_min_u16_e32 v13, 15, v13
+; GFX950-NEXT: v_cndmask_b32_e64 v6, v11, v6, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v1, 8, v1
+; GFX950-NEXT: v_bitop3_b16 v2, v2, v1, s5 bitop3:0xec
+; GFX950-NEXT: v_frexp_mant_f16_e32 v1, v0
+; GFX950-NEXT: v_bitop3_b16 v11, v1, s2, v3 bitop3:0xec
+; GFX950-NEXT: v_sub_u16_e64 v16, v13, 1 clamp
+; GFX950-NEXT: v_lshrrev_b16_e32 v14, v13, v11
+; GFX950-NEXT: v_lshrrev_b16_e32 v11, v16, v11
+; GFX950-NEXT: v_lshlrev_b16_e64 v16, v16, 1
+; GFX950-NEXT: v_and_b32_e32 v17, 0x3ff, v1
+; GFX950-NEXT: v_add_u16_e32 v16, -1, v16
+; GFX950-NEXT: v_bitop3_b16 v16, v17, v16, s2 bitop3:0xc8
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v16
+; GFX950-NEXT: v_and_b32_e32 v15, 1, v14
+; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX950-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v11, v11, v16, v15 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v13
+; GFX950-NEXT: v_and_b32_sdwa v16, v17, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_lshrrev_b64 v[6:7], 24, v[6:7]
+; GFX950-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc
+; GFX950-NEXT: v_add_u16_e32 v11, v14, v11
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v11
+; GFX950-NEXT: v_lshrrev_b16_e32 v14, 8, v0
+; GFX950-NEXT: v_and_b32_e32 v15, 0x80, v14
+; GFX950-NEXT: v_cndmask_b32_e64 v11, v11, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 4, vcc
+; GFX950-NEXT: v_bitop3_b16 v11, v15, v11, v13 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, 7, v1
+; GFX950-NEXT: v_and_b32_e32 v1, 0x7f, v1
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v1, v13, v1, v16 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_sdwa v1, v17, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v12, v12, v13
+; GFX950-NEXT: v_add_u16_e32 v12, 14, v12
+; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v13, 2, v12
+; GFX950-NEXT: v_bitop3_b16 v13, v15, v1, v13 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v12
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 30, v12
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v1
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 30, v12
+; GFX950-NEXT: v_bitop3_b16 v1, v14, s4, v9 bitop3:0xec
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v9, v11, v1, vcc
+; GFX950-NEXT: v_cmp_eq_f16_e32 vcc, 0, v0
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v11, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_sub_u16_e32 v12, -5, v11
+; GFX950-NEXT: v_cndmask_b32_e32 v9, v9, v15, vcc
+; GFX950-NEXT: v_cmp_class_f16_e64 vcc, v0, s3
+; GFX950-NEXT: v_min_u16_e32 v12, 15, v12
+; GFX950-NEXT: v_sub_u16_e64 v15, v12, 1 clamp
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX950-NEXT: v_frexp_mant_f16_sdwa v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_bitop3_b16 v3, v9, s2, v3 bitop3:0xec
+; GFX950-NEXT: v_lshrrev_b16_e32 v13, v12, v3
+; GFX950-NEXT: v_lshrrev_b16_e32 v3, v15, v3
+; GFX950-NEXT: v_lshlrev_b16_e64 v15, v15, 1
+; GFX950-NEXT: v_and_b32_e32 v16, 0x3ff, v9
+; GFX950-NEXT: v_add_u16_e32 v15, -1, v15
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
+; GFX950-NEXT: v_bitop3_b16 v15, v16, v15, s2 bitop3:0xc8
+; GFX950-NEXT: v_and_b32_e32 v14, 1, v13
+; GFX950-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v15
+; GFX950-NEXT: v_and_b32_sdwa v5, v16, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v3, v15, v14 bitop3:0xe0
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v12
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX950-NEXT: v_add_u16_e32 v3, v13, v3
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v3
+; GFX950-NEXT: v_lshrrev_b32_e32 v13, 31, v0
+; GFX950-NEXT: v_lshlrev_b16_e32 v13, 7, v13
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
+; GFX950-NEXT: v_cndmask_b32_e64 v12, 0, 4, vcc
+; GFX950-NEXT: v_bitop3_b16 v3, v13, v3, v12 bitop3:0xfe
+; GFX950-NEXT: v_lshrrev_b16_e32 v12, 7, v9
+; GFX950-NEXT: v_and_b32_e32 v9, 0x7f, v9
+; GFX950-NEXT: v_cmp_ne_u16_e32 vcc, 0, v9
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_bitop3_b16 v5, v12, v9, v5 bitop3:0xe0
+; GFX950-NEXT: v_add_u16_sdwa v5, v16, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v5
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-NEXT: v_add_u16_e32 v9, v11, v9
+; GFX950-NEXT: v_add_u16_e32 v9, 14, v9
+; GFX950-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v11, 2, v9
+; GFX950-NEXT: v_bitop3_b16 v11, v13, v5, v11 bitop3:0xfe
+; GFX950-NEXT: v_cmp_gt_i16_e32 vcc, 1, v9
+; GFX950-NEXT: v_cmp_eq_u16_e64 s[0:1], 30, v9
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 3, v5
+; GFX950-NEXT: s_and_b64 s[0:1], s[0:1], vcc
+; GFX950-NEXT: v_cmp_lt_i16_e32 vcc, 30, v9
+; GFX950-NEXT: v_or_b32_e32 v5, 0x7c, v13
+; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX950-NEXT: v_cmp_eq_f16_sdwa vcc, v0, v10 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc
+; GFX950-NEXT: v_cmp_class_f16_sdwa s[0:1], v0, s3 src0_sel:WORD_1 src1_sel:DWORD
+; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
+; GFX950-NEXT: v_cndmask_b32_e32 v0, v8, v3, vcc
+; GFX950-NEXT: v_lshlrev_b16_e32 v3, 8, v0
+; GFX950-NEXT: v_bitop3_b16 v0, v1, v3, s5 bitop3:0xec
+; GFX950-NEXT: v_lshl_or_b32 v1, v2, 16, v3
+; GFX950-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX950-NEXT: v_mov_b32_e32 v3, v6
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1200-LABEL: to_bf8_v5f16:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1200-NEXT: s_wait_expcnt 0x0
+; GFX1200-NEXT: s_wait_samplecnt 0x0
+; GFX1200-NEXT: s_wait_bvhcnt 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v2.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v3.h, v2.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v2
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, 8, v2.l
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2.l
+; GFX1200-NEXT: v_sub_nc_u16 v4.h, -5, v3.l
+; GFX1200-NEXT: v_and_b16 v5.l, 0x3ff, v3.h
+; GFX1200-NEXT: v_and_b16 v5.h, 0x7f, v3.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.h, v12.l
+; GFX1200-NEXT: v_lshrrev_b16 v3.h, 7, v3.h
+; GFX1200-NEXT: v_min_u16 v4.h, v4.h, 15
+; GFX1200-NEXT: v_or_b16 v7.l, 0x400, v5.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v5.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
+; GFX1200-NEXT: v_sub_nc_u16 v9.l, -5, v6.h
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, v4.h, 1 clamp
+; GFX1200-NEXT: v_lshrrev_b16 v10.l, v4.h, v7.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v12.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.h, 1
+; GFX1200-NEXT: v_and_b16 v4.h, v5.l, 1
+; GFX1200-NEXT: v_min_u16 v9.l, v9.l, 15
+; GFX1200-NEXT: v_and_b16 v9.h, 0x7f, v6.l
+; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_or_b16 v4.h, v11.l, v4.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
+; GFX1200-NEXT: v_and_b16 v4.l, 0x80, v4.l
+; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v8.h
+; GFX1200-NEXT: v_and_b16 v8.l, v7.l, v8.l
+; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v4.h
+; GFX1200-NEXT: v_and_b16 v4.h, v10.l, 1
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v7.h, v7.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, v9.l, 1 clamp
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v8.l
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v5.l, v3.h
+; GFX1200-NEXT: v_lshrrev_b16 v8.h, 8, v8.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, v9.l, v10.h
+; GFX1200-NEXT: v_or_b16 v5.h, 0x7c, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 3, v3.h
+; GFX1200-NEXT: v_and_b16 v9.h, v5.l, 1
+; GFX1200-NEXT: v_cmp_class_f16_e64 s6, v2.l, 0x204
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v11.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s2
+; GFX1200-NEXT: v_and_b16 v9.l, v8.h, 1
+; GFX1200-NEXT: v_or_b16 v4.h, v8.l, v4.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, v7.h, v10.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v11.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s2
+; GFX1200-NEXT: v_and_b16 v4.h, v7.l, v4.h
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v8.l, -1
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v13.l
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, 14
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 3, v3.h
+; GFX1200-NEXT: v_cndmask_b16 v4.h, 0, v4.h, s0
+; GFX1200-NEXT: v_and_b16 v7.l, v10.h, v7.l
+; GFX1200-NEXT: v_or_b16 v8.l, v8.l, v9.l
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s3, 30, v3.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s5, 30, v3.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v10.l, v4.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v7.l
+; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v8.l
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, 2, v3.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v13, 16, v1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v4.h
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v8.h, v6.l
+; GFX1200-NEXT: v_or_b16 v8.l, v4.l, v8.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v8.h, 0, 4, s0
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 3, v6.l
+; GFX1200-NEXT: v_or_b16 v3.h, v8.l, v3.h
+; GFX1200-NEXT: v_or_b16 v7.l, v7.l, v9.h
+; GFX1200-NEXT: v_or_b16 v8.h, v4.l, v8.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s4
+; GFX1200-NEXT: v_and_b16 v7.l, v7.h, v7.l
+; GFX1200-NEXT: v_or_b16 v4.h, v8.h, v4.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s4
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0, v7.l, s1
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v4.h, s0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v8.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v2
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v4.h, v1.l
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v5.l, v3.l
+; GFX1200-NEXT: s_and_b32 s0, s3, s2
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v6.h, v7.l
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_or_b32 s0, s5, s0
+; GFX1200-NEXT: v_sub_nc_u16 v5.l, -5, v4.h
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v5.h, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v3.l
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v2.h, 14
+; GFX1200-NEXT: v_min_u16 v5.l, v5.l, 15
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v4.l, vcc_lo
+; GFX1200-NEXT: v_lshlrev_b16 v4.l, 7, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, 4, s0
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v2.l
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 2, v2.h
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v5.h, s6
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s0
+; GFX1200-NEXT: v_or_b16 v5.h, v4.l, v6.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v1.l
+; GFX1200-NEXT: v_or_b16 v2.l, v4.l, v2.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, v5.l, 1 clamp
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7e, v3.h, vcc_lo
+; GFX1200-NEXT: v_or_b16 v3.l, v5.h, v3.l
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v2.h
+; GFX1200-NEXT: v_or_b16 v2.l, v2.l, v6.l
+; GFX1200-NEXT: v_and_b16 v5.h, 0x3ff, v6.h
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, v7.l, 1
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v6.l
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s1, 30, v2.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 30, v2.h
+; GFX1200-NEXT: v_or_b16 v2.h, 0x400, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v7.h, -1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v3.l, vcc_lo
+; GFX1200-NEXT: v_and_b16 v3.l, 0x7f, v6.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 8, v5.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, v5.l, v2.h
+; GFX1200-NEXT: v_and_b16 v6.l, v2.h, v6.l
+; GFX1200-NEXT: s_and_b32 s0, s1, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
+; GFX1200-NEXT: v_or_b16 v3.l, 0x7c, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_or_b32 s0, s2, s0
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 7, v6.h
+; GFX1200-NEXT: v_lshrrev_b16 v2.h, v7.l, v2.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6.l
+; GFX1200-NEXT: v_and_b16 v6.l, v5.h, 1
+; GFX1200-NEXT: v_and_b16 v8.h, v7.h, 1
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v3.l, s0
+; GFX1200-NEXT: v_cmp_class_f16_e64 s0, v12.l, 0x204
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12.l
+; GFX1200-NEXT: v_or_b16 v6.l, v8.l, v6.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 8, v1.l
+; GFX1200-NEXT: v_and_b16 v3.h, 0xff, v3.h
+; GFX1200-NEXT: v_or_b16 v8.l, v9.l, v8.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v4.l, vcc_lo
+; GFX1200-NEXT: v_and_b16 v4.l, v6.h, v6.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.l, v13.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
+; GFX1200-NEXT: v_and_b16 v2.h, v2.h, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v3.l, s0
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v5.h, v4.l
+; GFX1200-NEXT: v_sub_nc_u16 v3.l, -5, v6.l
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v12.l, v12.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v2.h, vcc_lo
+; GFX1200-NEXT: v_and_b16 v7.l, 0x80, v7.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 3, v4.l
+; GFX1200-NEXT: v_min_u16 v3.l, v3.l, 15
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, 0x7e, v2.l, s0
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v7.h, v2.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v0
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v13.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, v3.l, 1 clamp
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v2.h
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, vcc_lo
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, v5.l
+; GFX1200-NEXT: v_and_b16 v5.l, 0x3ff, v5.h
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, v6.h, 1
+; GFX1200-NEXT: v_and_b16 v9.l, 0x7f, v5.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 4, s0
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, 14
+; GFX1200-NEXT: v_or_b16 v8.h, 0x400, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s0
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v5.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
+; GFX1200-NEXT: v_lshlrev_b16 v9.h, 2, v4.h
+; GFX1200-NEXT: v_and_b16 v7.h, v8.h, v7.h
+; GFX1200-NEXT: v_or_b16 v8.l, v7.l, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v5.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
+; GFX1200-NEXT: v_or_b16 v9.h, v7.l, v9.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v7.h
+; GFX1200-NEXT: v_and_b16 v7.h, v5.l, 1
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v3.l, v8.h
+; GFX1200-NEXT: v_or_b16 v2.h, v8.l, v2.h
+; GFX1200-NEXT: v_or_b16 v8.l, v9.h, v4.l
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v4.h
+; GFX1200-NEXT: v_or_b16 v7.h, v10.l, v7.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
+; GFX1200-NEXT: v_and_b16 v10.h, v9.l, 1
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v8.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v8.l, v2.h, vcc_lo
+; GFX1200-NEXT: v_and_b16 v5.h, v5.h, v7.h
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 3, v4.l
+; GFX1200-NEXT: v_or_b16 v9.h, v11.l, v10.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.l
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s1, 30, v4.h
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v5.l, v5.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 30, v4.h
+; GFX1200-NEXT: v_and_b16 v5.l, v6.h, v9.h
+; GFX1200-NEXT: v_or_b16 v4.h, 0x7c, v7.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.h, v0.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 3, v4.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v7.h, v0.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0, v5.l, s0
+; GFX1200-NEXT: s_and_b32 s0, s1, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v1.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s3
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_or_b32 s0, s2, s0
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v9.l, v3.l
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v4.h, s0
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s3
+; GFX1200-NEXT: v_mov_b16_e32 v5.l, v8.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v1
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v3.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v2.h, v7.l, vcc_lo
+; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v7.h
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v6.l, v5.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.l, -5, v5.h
+; GFX1200-NEXT: v_lshlrev_b16 v6.h, 7, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s0
+; GFX1200-NEXT: v_cmp_class_f16_e64 s2, v1.l, 0x204
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v5.l, 14
+; GFX1200-NEXT: v_min_u16 v6.l, v6.l, 15
+; GFX1200-NEXT: v_cndmask_b16 v5.l, 0, 4, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, v4.h, s2
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, 2, v2.h
+; GFX1200-NEXT: v_sub_nc_u16 v8.l, v6.l, 1 clamp
+; GFX1200-NEXT: v_or_b16 v5.l, v6.h, v5.l
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s1, 30, v2.h
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v2.h
+; GFX1200-NEXT: v_or_b16 v7.l, v6.h, v7.l
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, v8.l, 1
+; GFX1200-NEXT: v_or_b16 v3.l, v5.l, v3.l
+; GFX1200-NEXT: s_and_b32 s1, s1, s0
+; GFX1200-NEXT: v_cmp_class_f16_e64 s3, v13.l, 0x204
+; GFX1200-NEXT: v_or_b16 v5.l, v7.l, v4.l
+; GFX1200-NEXT: v_or_b16 v7.l, 0x400, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v2.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v5.l, v3.l, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 30, v2.h
+; GFX1200-NEXT: v_and_b16 v4.l, v7.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v2.h, v6.l, v7.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.l
+; GFX1200-NEXT: v_or_b16 v4.l, 0x7c, v6.h
+; GFX1200-NEXT: v_and_b16 v4.h, v2.h, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_or_b32 s0, vcc_lo, s1
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v1.l
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v3.l, v4.l, s0
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v12.l
+; GFX1200-NEXT: v_mov_b16_e32 v5.l, v9.l
+; GFX1200-NEXT: v_and_b16 v9.l, 0x7f, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v7.h
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v13.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0x7e, v1.h, vcc_lo
+; GFX1200-NEXT: v_or_b16 v4.h, v5.l, v4.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, v8.l, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 8, v8.h
+; GFX1200-NEXT: v_sub_nc_u16 v8.l, -5, v3.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v8.h, v12.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
+; GFX1200-NEXT: v_and_b16 v4.h, v5.l, v4.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v6.l
+; GFX1200-NEXT: v_min_u16 v5.l, v8.l, 15
+; GFX1200-NEXT: v_and_b16 v6.l, v7.l, 1
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v6.h, s1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v4.h, 0, v4.h, s0
+; GFX1200-NEXT: v_sub_nc_u16 v9.l, v5.l, 1 clamp
+; GFX1200-NEXT: v_and_b16 v1.h, 0xff, v1.h
+; GFX1200-NEXT: v_or_b16 v6.l, v8.l, v6.l
+; GFX1200-NEXT: v_and_b16 v8.l, 0x3ff, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v2.h, v4.h
+; GFX1200-NEXT: v_lshlrev_b16 v9.h, v9.l, 1
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s3
+; GFX1200-NEXT: v_and_b16 v4.h, v7.h, v6.l
+; GFX1200-NEXT: v_and_b16 v7.h, 0x7f, v8.h
+; GFX1200-NEXT: v_or_b16 v6.l, 0x400, v8.l
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v9.h, -1
+; GFX1200-NEXT: v_lshrrev_b16 v8.h, 7, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.l, v4.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 8, v8.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v7.h
+; GFX1200-NEXT: v_and_b16 v6.h, v6.l, v6.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, v5.l, v6.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v2.h
+; GFX1200-NEXT: v_and_b16 v8.l, v7.l, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s1
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 3, v4.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v6.h
+; GFX1200-NEXT: v_and_b16 v6.h, v7.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, v9.l, v6.l
+; GFX1200-NEXT: v_or_b16 v8.l, v10.l, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
+; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s2
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s0
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s1
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v5.h, v11.l
+; GFX1200-NEXT: v_and_b16 v5.h, v8.h, v8.l
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v14.l
+; GFX1200-NEXT: v_lshrrev_b16 v8.h, 8, v0.l
+; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 4, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v7.l, v5.h
+; GFX1200-NEXT: v_or_b16 v6.h, v10.l, v6.h
+; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, 14
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 3, v4.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 3, v5.h
+; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v6.h
+; GFX1200-NEXT: v_or_b16 v7.l, v5.l, v8.l
+; GFX1200-NEXT: v_lshlrev_b16 v6.h, 2, v4.l
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s5, 30, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s2
+; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v6.l, s0
+; GFX1200-NEXT: v_or_b16 v2.h, v7.l, v2.h
+; GFX1200-NEXT: v_or_b16 v6.h, v5.l, v6.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s3, 1, v4.l
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v7.h, v6.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v7, 31, v0
+; GFX1200-NEXT: v_or_b16 v6.h, v6.h, v4.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s6, 30, v4.l
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v8.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 3, v6.l
+; GFX1200-NEXT: v_lshlrev_b16 v4.h, 7, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, s2
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v6.h, v2.h, s3
+; GFX1200-NEXT: v_add_nc_u16 v0.h, v3.l, 14
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0, 4, s1
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v6.l, 0, s1
+; GFX1200-NEXT: s_and_b32 s1, s5, s4
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 3, v5.h
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, 2, v0.h
+; GFX1200-NEXT: v_or_b16 v3.l, v4.h, v3.l
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_or_b32 s5, s6, s1
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s1, 1, v0.h
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s3, 30, v0.h
+; GFX1200-NEXT: v_or_b16 v6.l, v4.h, v7.l
+; GFX1200-NEXT: v_or_b16 v3.l, v3.l, v4.l
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v13.l, v13.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 30, v0.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v4.l, v6.l, v5.h
+; GFX1200-NEXT: v_or_b16 v5.h, 0x7c, v5.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7e, v1.l, s0
+; GFX1200-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x204
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v4.l, v3.l, s1
+; GFX1200-NEXT: s_and_b32 s1, s3, s2
+; GFX1200-NEXT: v_or_b16 v3.l, 0x7c, v4.h
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v5.h, s5
+; GFX1200-NEXT: s_or_b32 s2, s4, s1
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v0.l
+; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v3.l, s2
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s2, 0, v12.l
+; GFX1200-NEXT: v_or_b16 v4.l, v3.h, v2.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v5.l, s1
+; GFX1200-NEXT: v_cmp_class_f16_e64 s1, v12.l, 0x204
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v4.h, s2
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v2.h, v5.h, s0
+; GFX1200-NEXT: v_or_b16 v2.h, v1.h, v1.l
+; GFX1200-NEXT: v_cvt_u32_u16_e32 v1, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.l, v0.h, v3.l, s1
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v12.l, v12.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7e, v4.h, vcc_lo
+; GFX1200-NEXT: v_mov_b16_e32 v3.l, v2.h
+; GFX1200-NEXT: v_or_b32_e32 v6, 0x7e7e0000, v1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7e, v0.l, s0
+; GFX1200-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
+; GFX1200-NEXT: v_lshrrev_b64 v[5:6], 24, v[5:6]
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v2.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX1200-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1200-NEXT: v_mov_b16_e32 v3.l, v5.l
+; GFX1200-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: to_bf8_v5f16:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v3.h, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v5.h, s0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v5.l, v2
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v3.l, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.h
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_dual_lshlrev_b32 v4, 16, v1 :: v_dual_lshrrev_b32 v1, 8, v3
+; GFX1250-TRUE16-NEXT: v_lshrrev_b64 v[6:7], 24, v[4:5]
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.l, v6.l
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: to_bf8_v5f16:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f16_e64 v4, v2
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f16_e64 v0, v0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f16_e64 v3, s0
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf8_f16_e64 v2, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v4
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_lshl_or_b32 v7, v3, 16, v1
+; GFX1250-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v5
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_dual_lshlrev_b32 v6, 16, v2 :: v_dual_lshrrev_b32 v1, 8, v1
+; GFX1250-FAKE16-NEXT: v_lshrrev_b64 v[6:7], 24, v[6:7]
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1310-LABEL: to_bf8_v5f16:
+; GFX1310: ; %bb.0:
+; GFX1310-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1310-NEXT: s_wait_expcnt 0x0
+; GFX1310-NEXT: s_wait_samplecnt 0x0
+; GFX1310-NEXT: s_wait_bvhcnt 0x0
+; GFX1310-NEXT: s_wait_kmcnt 0x0
+; GFX1310-NEXT: v_cvt_pk_bf8_f16_e32 v5, v2
+; GFX1310-NEXT: v_cvt_pk_bf8_f16_e32 v0, v0
+; GFX1310-NEXT: v_cvt_pk_bf8_f16_e32 v4, s0
+; GFX1310-NEXT: v_cvt_pk_bf8_f16_e32 v2, v1
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1310-NEXT: v_and_b32_e32 v1, 0xffff, v5
+; GFX1310-NEXT: v_and_b32_e32 v6, 0xffff, v0
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1310-NEXT: v_lshl_or_b32 v4, v4, 16, v1
+; GFX1310-NEXT: v_lshl_or_b32 v1, v2, 16, v6
+; GFX1310-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1310-NEXT: v_dual_lshlrev_b32 v3, 16, v2 :: v_dual_lshrrev_b32 v1, 8, v1
+; GFX1310-NEXT: v_lshrrev_b64 v[3:4], 24, v[3:4]
+; GFX1310-NEXT: v_mov_b32_e32 v4, v5
+; GFX1310-NEXT: s_set_pc_i64 s[30:31]
+ %r = call <5 x i8> @llvm.convert.to.arbitrary.fp.v5i8.v5f16(<5 x half> %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
+ ret <5 x i8> %r
+}
diff --git a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
index 79d8bd57ef560..e12bea905e18a 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
@@ -201,20 +201,28 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
// CHECK-LABEL: // PatFrag predicates.
// CHECK-NEXT: enum {
-// CHECK-NEXT: GICXXPred_I64_Predicate_Float8E4M3FN = GICXXPred_Invalid + 1,
+// CHECK-NEXT: GICXXPred_I64_Predicate_FPNoSaturation = GICXXPred_Invalid + 1,
+// CHECK-NEXT: GICXXPred_I64_Predicate_Float8E4M3FN,
// CHECK-NEXT: GICXXPred_I64_Predicate_Float8E5M2,
+// CHECK-NEXT: GICXXPred_I64_Predicate_NearestTiesToEven,
// CHECK-NEXT: GICXXPred_I64_Predicate_cimm8,
// CHECK-NEXT: GICXXPred_I64_Predicate_simm8,
// CHECK-NEXT: };
// CHECK-NEXT: bool MyTargetInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
// CHECK-NEXT: switch (PredicateID) {
+// CHECK-NEXT: case GICXXPred_I64_Predicate_FPNoSaturation: {
+// CHECK-NEXT: return Imm == 0;
+// CHECK-NEXT: }
// CHECK-NEXT: case GICXXPred_I64_Predicate_Float8E4M3FN: {
// CHECK-NEXT: return Imm == APFloatBase::S_Float8E4M3FN;
// CHECK-NEXT: }
// CHECK-NEXT: case GICXXPred_I64_Predicate_Float8E5M2: {
// CHECK-NEXT: return Imm == APFloatBase::S_Float8E5M2;
// CHECK-NEXT: }
+// CHECK-NEXT: case GICXXPred_I64_Predicate_NearestTiesToEven: {
+// CHECK-NEXT: return Imm == static_cast<int>(RoundingMode::NearestTiesToEven);
+// CHECK-NEXT: }
// CHECK-NEXT: case GICXXPred_I64_Predicate_cimm8: {
// CHECK-NEXT: return isInt<8>(Imm);
// CHECK-NEXT: }
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