[llvm] [CodeGen] Expand unsupported interleave to shuffles (PR #210494)
Kamlesh Kumar via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 10 21:54:58 PDT 2026
https://github.com/kamleshbhalui updated https://github.com/llvm/llvm-project/pull/210494
>From 06b0bbc33cdb0500301c52cb5b4a7e05d6783026 Mon Sep 17 00:00:00 2001
From: Kamlesh Kumar <kamlesh.kumar at arm.com>
Date: Tue, 28 Jul 2026 07:58:49 +0100
Subject: [PATCH] [CodeGen][AArch64] Expand unsupported interleave to shuffles
---
llvm/include/llvm/CodeGen/TargetLowering.h | 8 +
.../SelectionDAG/LegalizeVectorOps.cpp | 90 ++
.../SelectionDAG/SelectionDAGBuilder.cpp | 22 -
llvm/lib/Target/AArch64/AArch64ISelLowering.h | 3 +
llvm/lib/Target/RISCV/RISCVISelLowering.h | 3 +
.../aarch64-interleaved-access-w-undef.ll | 40 +-
.../AArch64/aarch64-interleaved-ld-combine.ll | 71 +-
llvm/test/CodeGen/AArch64/binopshuffles.ll | 73 +-
.../complex-deinterleaving-multiuses.ll | 288 ++-----
.../complex-deinterleaving-reductions.ll | 16 +-
.../AArch64/fixed-deinterleave-intrinsics.ll | 816 +++++-------------
.../AArch64/fixed-length-sve-interleave.ll | 19 +-
.../AArch64/fixed-vector-deinterleave.ll | 63 +-
.../fixed-vector-interleave-odd-factor.ll | 131 +++
.../AArch64/fixed-vector-interleave.ll | 50 +-
.../fixed_masked_deinterleaved_loads.ll | 28 +-
.../fixed_masked_interleaved_stores.ll | 24 +-
.../CodeGen/AArch64/interleaved-accesses.ll | 61 +-
.../AArch64/nontemporal-load-interleaved.ll | 522 ++++-------
.../nontemporal-store-interleaved-optsize.ll | 183 ++--
.../AArch64/nontemporal-store-interleaved.ll | 644 +++++---------
.../AArch64/sve-fixed-length-shuffles.ll | 26 +-
.../AArch64/sve-interleaved-accesses.ll | 93 +-
...-streaming-mode-fixed-length-interleave.ll | 128 +--
...-streaming-mode-fixed-length-ld2-alloca.ll | 8 +-
...sve-streaming-mode-fixed-length-shuffle.ll | 15 +-
llvm/test/CodeGen/AArch64/tbl-loops.ll | 229 ++---
.../AArch64/vector-deinterleave-load.ll | 39 +-
.../AArch64/vector-interleave-store.ll | 29 +-
llvm/test/CodeGen/AArch64/vldn_shuffle.ll | 243 ++----
.../X86/vector-interleave-intrinsics.ll | 576 +++++++++++++
31 files changed, 1921 insertions(+), 2620 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/fixed-vector-interleave-odd-factor.ll
create mode 100644 llvm/test/CodeGen/X86/vector-interleave-intrinsics.ll
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 9a525d69b3ee8..ca9792d6ca2d4 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -3335,6 +3335,14 @@ class LLVM_ABI TargetLoweringBase {
/// Default to be the minimum interleave factor: 2.
virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
+ /// Return true if the target lowers ISD::VECTOR_INTERLEAVE and
+ /// ISD::VECTOR_DEINTERLEAVE of the given Factor and VecTy
+ /// itself.
+ virtual bool isInterleaveIntrinsicSupported(unsigned /*Factor*/,
+ EVT /*VecTy*/) const {
+ return false;
+ }
+
/// Lower an interleaved load to target specific intrinsics. Return
/// true on success.
///
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 7b97c41ac2dbc..0e2baac46fa5c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -95,6 +95,14 @@ class VectorLegalizer {
/// operations to legalize them.
void Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results);
+ /// Expand a VECTOR_INTERLEAVE into shuffles.
+ void ExpandVectorInterleaveToShuffles(SDNode *Node,
+ SmallVectorImpl<SDValue> &Results);
+
+ /// Expand a VECTOR_DEINTERLEAVE into shuffles.
+ void ExpandVectorDeinterleaveToShuffles(SDNode *Node,
+ SmallVectorImpl<SDValue> &Results);
+
/// Implements expansion for FP_TO_UINT; falls back to UnrollVectorOp if
/// FP_TO_SINT isn't legal.
void ExpandFP_TO_UINT(SDNode *Node, SmallVectorImpl<SDValue> &Results);
@@ -491,6 +499,18 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
case ISD::MASKED_SREM:
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
break;
+ case ISD::VECTOR_INTERLEAVE:
+ case ISD::VECTOR_DEINTERLEAVE: {
+ EVT VT = Node->getValueType(0);
+ unsigned Factor = Node->getNumOperands();
+ Action = TLI.getOperationAction(Node->getOpcode(), VT);
+ if (!TLI.isInterleaveIntrinsicSupported(Factor, VT))
+ Action = TargetLowering::Expand;
+ else if (Action == TargetLowering::Custom)
+ // Leave the node untouched for LegalizeDAG.
+ Action = TargetLowering::Legal;
+ break;
+ }
case ISD::SMULFIX:
case ISD::SMULFIXSAT:
case ISD::UMULFIX:
@@ -967,6 +987,70 @@ SDValue VectorLegalizer::ExpandStore(SDNode *N) {
return TF;
}
+void VectorLegalizer::ExpandVectorInterleaveToShuffles(
+ SDNode *Node, SmallVectorImpl<SDValue> &Results) {
+ assert(Node->getOpcode() == ISD::VECTOR_INTERLEAVE && "Unexpected opcode");
+ EVT VT = Node->getValueType(0);
+ if (!VT.isFixedLengthVector())
+ return;
+
+ unsigned Factor = Node->getNumOperands();
+ unsigned NumElts = VT.getVectorNumElements();
+ SDLoc DL(Node);
+
+ // The interleaved value is the concatenation of the results, so build it as
+ // one wide shuffle and split that back up into one vector per factor.
+ EVT WideVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
+ NumElts * Factor);
+ SmallVector<SDValue, 8> InVecs(Node->op_values());
+ SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideVT, InVecs);
+ SDValue Interleaved =
+ DAG.getVectorShuffle(WideVT, DL, Concat, DAG.getUNDEF(WideVT),
+ createInterleaveMask(NumElts, Factor));
+
+ for (unsigned I = 0; I != Factor; ++I)
+ Results.push_back(
+ DAG.getExtractSubvector(DL, VT, Interleaved, I * NumElts));
+}
+
+void VectorLegalizer::ExpandVectorDeinterleaveToShuffles(
+ SDNode *Node, SmallVectorImpl<SDValue> &Results) {
+ assert(Node->getOpcode() == ISD::VECTOR_DEINTERLEAVE && "Unexpected opcode");
+ EVT VT = Node->getValueType(0);
+ if (!VT.isFixedLengthVector())
+ return;
+
+ unsigned Factor = Node->getNumOperands();
+ unsigned NumElts = VT.getVectorNumElements();
+ SDLoc DL(Node);
+
+ // A factor of two is a plain two-input shuffle per result.
+ if (Factor == 2) {
+ for (unsigned I = 0; I != Factor; ++I)
+ Results.push_back(
+ DAG.getVectorShuffle(VT, DL, Node->getOperand(0), Node->getOperand(1),
+ createStrideMask(I, Factor, NumElts)));
+ return;
+ }
+
+ // Higher factors need more than the two inputs a shuffle has, so gather the
+ // operands into one wide vector, permute it and split the result back up.
+ EVT WideVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
+ NumElts * Factor);
+ SmallVector<int, 16> Mask;
+ for (unsigned I = 0; I != Factor; ++I)
+ llvm::append_range(Mask, createStrideMask(I, Factor, NumElts));
+
+ SmallVector<SDValue, 8> InVecs(Node->op_values());
+ SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideVT, InVecs);
+ SDValue Deinterleaved =
+ DAG.getVectorShuffle(WideVT, DL, Concat, DAG.getUNDEF(WideVT), Mask);
+
+ for (unsigned I = 0; I != Factor; ++I)
+ Results.push_back(
+ DAG.getExtractSubvector(DL, VT, Deinterleaved, I * NumElts));
+}
+
void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
switch (Node->getOpcode()) {
case ISD::LOAD: {
@@ -982,6 +1066,12 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
Results.push_back(Node->getOperand(i));
return;
+ case ISD::VECTOR_INTERLEAVE:
+ ExpandVectorInterleaveToShuffles(Node, Results);
+ return;
+ case ISD::VECTOR_DEINTERLEAVE:
+ ExpandVectorDeinterleaveToShuffles(Node, Results);
+ return;
case ISD::SIGN_EXTEND_INREG:
if (SDValue Expanded = ExpandSEXTINREG(Node)) {
Results.push_back(Expanded);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index a2b9a14ed9543..2a3be7f9775d1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -13061,18 +13061,6 @@ void SelectionDAGBuilder::visitVectorDeinterleave(const CallInst &I,
DAG.getVectorIdxConstant(OutNumElts * i, DL));
}
- // Use VECTOR_SHUFFLE for fixed-length vectors with factor of 2 to benefit
- // from existing legalisation and combines.
- if (OutVT.isFixedLengthVector() && Factor == 2) {
- SDValue Even = DAG.getVectorShuffle(OutVT, DL, SubVecs[0], SubVecs[1],
- createStrideMask(0, 2, OutNumElts));
- SDValue Odd = DAG.getVectorShuffle(OutVT, DL, SubVecs[0], SubVecs[1],
- createStrideMask(1, 2, OutNumElts));
- SDValue Res = DAG.getMergeValues({Even, Odd}, getCurSDLoc());
- setValue(&I, Res);
- return;
- }
-
SDValue Res = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL,
DAG.getVTList(ValueVTs), SubVecs);
setValue(&I, Res);
@@ -13092,16 +13080,6 @@ void SelectionDAGBuilder::visitVectorInterleave(const CallInst &I,
"Expected VTs to be the same");
}
- // Use VECTOR_SHUFFLE for fixed-length vectors with factor of 2 to benefit
- // from existing legalisation and combines.
- if (OutVT.isFixedLengthVector() && Factor == 2) {
- unsigned NumElts = InVT.getVectorMinNumElements();
- SDValue V = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, InVecs);
- setValue(&I, DAG.getVectorShuffle(OutVT, DL, V, DAG.getUNDEF(OutVT),
- createInterleaveMask(NumElts, 2)));
- return;
- }
-
SmallVector<EVT, 8> ValueVTs(Factor, InVT);
SDValue Res =
DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, DAG.getVTList(ValueVTs), InVecs);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 66a6261d2a991..5cf25a44d8ac2 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -231,6 +231,9 @@ class AArch64TargetLowering : public TargetLowering {
bool hasPairedLoad(EVT LoadedType, Align &RequiredAlignment) const override;
unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
+ bool isInterleaveIntrinsicSupported(unsigned Factor, EVT VT) const override {
+ return VT.isScalableVector() || Factor == 3 || Factor % 2 == 0;
+ }
bool lowerInterleavedLoad(Instruction *Load, Value *Mask,
ArrayRef<ShuffleVectorInst *> Shuffles,
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 972cc256a3386..c30966eaf1843 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -438,6 +438,9 @@ class RISCVTargetLowering : public TargetLowering {
bool isLegalFirstFaultLoad(EVT DataType, Align Alignment) const;
unsigned getMaxSupportedInterleaveFactor() const override { return 8; }
+ bool isInterleaveIntrinsicSupported(unsigned Factor, EVT VT) const override {
+ return Factor > 2 && Factor <= 8;
+ }
bool fallBackToDAGISel(const Instruction &Inst) const override;
diff --git a/llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll b/llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll
index 6b49ba0a65340..d367f39445799 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll
@@ -157,6 +157,12 @@ define void @f_undef_intrinsic(<8 x i64> %a, ptr %dst) {
;
; CHECK-IADISABLED-LABEL: f_undef_intrinsic:
; CHECK-IADISABLED: // %bb.0: // %BB
+; CHECK-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: zip1 v1.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #32]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #64]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #96]
; CHECK-IADISABLED-NEXT: ret
BB:
%S = call <16 x i64> @llvm.vector.interleave2.v16i64(<8 x i64> poison, <8 x i64> poison)
@@ -179,6 +185,12 @@ define void @f_poison_intrinsic(<8 x i64> %a, ptr %dst) {
;
; CHECK-IADISABLED-LABEL: f_poison_intrinsic:
; CHECK-IADISABLED: // %bb.0: // %BB
+; CHECK-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: zip1 v1.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #32]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #64]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #96]
; CHECK-IADISABLED-NEXT: ret
BB:
%S = call <16 x i64> @llvm.vector.interleave2.v16i64(<8 x i64> poison, <8 x i64> poison)
@@ -202,8 +214,14 @@ define void @f_undef_15_intrinsic(<8 x i64> %a, ptr %dst) {
;
; CHECK-IADISABLED-LABEL: f_undef_15_intrinsic:
; CHECK-IADISABLED: // %bb.0: // %BB
-; CHECK-IADISABLED-NEXT: dup v1.2d, v0.d[1]
-; CHECK-IADISABLED-NEXT: stp q0, q1, [x0]
+; CHECK-IADISABLED-NEXT: zip2 v1.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: zip1 v2.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: zip2 v3.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: stp q2, q1, [x0, #32]
+; CHECK-IADISABLED-NEXT: stp q0, q3, [x0]
+; CHECK-IADISABLED-NEXT: stp q2, q1, [x0, #64]
+; CHECK-IADISABLED-NEXT: stp q2, q1, [x0, #96]
; CHECK-IADISABLED-NEXT: ret
BB:
%a.0 = extractelement <8 x i64> %a, i64 0
@@ -236,17 +254,17 @@ define void @f_undef_1_intrinsic(<8 x i64> %a, ptr %dst) {
;
; CHECK-IADISABLED-LABEL: f_undef_1_intrinsic:
; CHECK-IADISABLED: // %bb.0: // %BB
-; CHECK-IADISABLED-NEXT: dup v4.2d, v3.d[1]
-; CHECK-IADISABLED-NEXT: dup v3.2d, v3.d[0]
-; CHECK-IADISABLED-NEXT: dup v5.2d, v2.d[1]
-; CHECK-IADISABLED-NEXT: dup v2.2d, v2.d[0]
+; CHECK-IADISABLED-NEXT: zip2 v4.2d, v3.2d, v3.2d
+; CHECK-IADISABLED-NEXT: zip1 v3.2d, v3.2d, v3.2d
+; CHECK-IADISABLED-NEXT: zip2 v5.2d, v2.2d, v2.2d
+; CHECK-IADISABLED-NEXT: zip1 v2.2d, v2.2d, v2.2d
+; CHECK-IADISABLED-NEXT: zip2 v6.2d, v1.2d, v1.2d
+; CHECK-IADISABLED-NEXT: zip1 v1.2d, v1.2d, v1.2d
; CHECK-IADISABLED-NEXT: stp q3, q4, [x0, #96]
-; CHECK-IADISABLED-NEXT: dup v4.2d, v1.d[1]
-; CHECK-IADISABLED-NEXT: dup v1.2d, v1.d[0]
-; CHECK-IADISABLED-NEXT: dup v3.2d, v0.d[1]
-; CHECK-IADISABLED-NEXT: dup v0.2d, v0.d[0]
+; CHECK-IADISABLED-NEXT: zip2 v3.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: stp q1, q6, [x0, #32]
; CHECK-IADISABLED-NEXT: stp q2, q5, [x0, #64]
-; CHECK-IADISABLED-NEXT: stp q1, q4, [x0, #32]
; CHECK-IADISABLED-NEXT: stp q0, q3, [x0]
; CHECK-IADISABLED-NEXT: ret
BB:
diff --git a/llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll b/llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll
index f83739ef6f44f..c56b492bb33cd 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll
@@ -896,31 +896,17 @@ define void @aarch64_ilc_idx_ld2_intrinsic(ptr %ptr, i64 %idx) {
; CHECK-NEXT: store <4 x float> [[M4_7]], ptr [[GEP2]], align 16
; CHECK-NEXT: ret void
;
-; AS-IAENABLED-LABEL: aarch64_ilc_idx_ld2_intrinsic:
-; AS-IAENABLED: // %bb.0: // %entry
-; AS-IAENABLED-NEXT: lsl x8, x1, #2
-; AS-IAENABLED-NEXT: and x9, x8, #0xfffffffffffffff0
-; AS-IAENABLED-NEXT: add x8, x8, #16
-; AS-IAENABLED-NEXT: add x10, x0, x9
-; AS-IAENABLED-NEXT: and x8, x8, #0xfffffffffffffff0
-; AS-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x10]
-; AS-IAENABLED-NEXT: str q0, [x0, x9]
-; AS-IAENABLED-NEXT: str q1, [x0, x8]
-; AS-IAENABLED-NEXT: ret
-;
-; AS-IADISABLED-LABEL: aarch64_ilc_idx_ld2_intrinsic:
-; AS-IADISABLED: // %bb.0: // %entry
-; AS-IADISABLED-NEXT: lsl x8, x1, #2
-; AS-IADISABLED-NEXT: and x9, x8, #0xfffffffffffffff0
-; AS-IADISABLED-NEXT: add x8, x8, #16
-; AS-IADISABLED-NEXT: add x9, x0, x9
-; AS-IADISABLED-NEXT: and x8, x8, #0xfffffffffffffff0
-; AS-IADISABLED-NEXT: ldp q1, q0, [x9]
-; AS-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; AS-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; AS-IADISABLED-NEXT: str q2, [x9]
-; AS-IADISABLED-NEXT: str q0, [x0, x8]
-; AS-IADISABLED-NEXT: ret
+; AS-LABEL: aarch64_ilc_idx_ld2_intrinsic:
+; AS: // %bb.0: // %entry
+; AS-NEXT: lsl x8, x1, #2
+; AS-NEXT: and x9, x8, #0xfffffffffffffff0
+; AS-NEXT: add x8, x8, #16
+; AS-NEXT: add x10, x0, x9
+; AS-NEXT: and x8, x8, #0xfffffffffffffff0
+; AS-NEXT: ld2 { v0.4s, v1.4s }, [x10]
+; AS-NEXT: str q0, [x0, x9]
+; AS-NEXT: str q1, [x0, x8]
+; AS-NEXT: ret
entry:
%idx1 = lshr i64 %idx, 2
%a1 = add i64 %idx, 4
@@ -1009,30 +995,17 @@ define void @aarch64_ilc_i32_idx_intrinsic(ptr %ptr, i32 %idx) {
; CHECK-NEXT: store <4 x float> [[M4_7]], ptr [[GEP2]], align 16
; CHECK-NEXT: ret void
;
-; AS-IAENABLED-LABEL: aarch64_ilc_i32_idx_intrinsic:
-; AS-IAENABLED: // %bb.0: // %entry
-; AS-IAENABLED-NEXT: lsr w8, w1, #2
-; AS-IAENABLED-NEXT: ubfiz x8, x8, #4, #32
-; AS-IAENABLED-NEXT: add x9, x0, x8
-; AS-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x9]
-; AS-IAENABLED-NEXT: add w9, w1, #4
-; AS-IAENABLED-NEXT: lsr w9, w9, #2
-; AS-IAENABLED-NEXT: str q0, [x0, x8]
-; AS-IAENABLED-NEXT: str q1, [x0, w9, uxtw #4]
-; AS-IAENABLED-NEXT: ret
-;
-; AS-IADISABLED-LABEL: aarch64_ilc_i32_idx_intrinsic:
-; AS-IADISABLED: // %bb.0: // %entry
-; AS-IADISABLED-NEXT: lsr w8, w1, #2
-; AS-IADISABLED-NEXT: add w9, w1, #4
-; AS-IADISABLED-NEXT: lsr w9, w9, #2
-; AS-IADISABLED-NEXT: add x8, x0, w8, uxtw #4
-; AS-IADISABLED-NEXT: ldp q1, q0, [x8]
-; AS-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; AS-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; AS-IADISABLED-NEXT: str q2, [x8]
-; AS-IADISABLED-NEXT: str q0, [x0, w9, uxtw #4]
-; AS-IADISABLED-NEXT: ret
+; AS-LABEL: aarch64_ilc_i32_idx_intrinsic:
+; AS: // %bb.0: // %entry
+; AS-NEXT: lsr w8, w1, #2
+; AS-NEXT: ubfiz x8, x8, #4, #32
+; AS-NEXT: add x9, x0, x8
+; AS-NEXT: ld2 { v0.4s, v1.4s }, [x9]
+; AS-NEXT: add w9, w1, #4
+; AS-NEXT: lsr w9, w9, #2
+; AS-NEXT: str q0, [x0, x8]
+; AS-NEXT: str q1, [x0, w9, uxtw #4]
+; AS-NEXT: ret
entry:
%idx1 = lshr i32 %idx, 2
%a1 = add i32 %idx, 4
diff --git a/llvm/test/CodeGen/AArch64/binopshuffles.ll b/llvm/test/CodeGen/AArch64/binopshuffles.ll
index 3ee9df3165c98..ab4e106c6362e 100644
--- a/llvm/test/CodeGen/AArch64/binopshuffles.ll
+++ b/llvm/test/CodeGen/AArch64/binopshuffles.ll
@@ -251,25 +251,13 @@ entry:
}
define <4 x float> @twosrc_intrinsic(ptr %pSrc1, ptr %pSrc2) {
-; CHECK-IAENABLED-LABEL: twosrc_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: ld2 { v1.4s, v2.4s }, [x0]
-; CHECK-IAENABLED-NEXT: ld2 { v3.4s, v4.4s }, [x1]
-; CHECK-IAENABLED-NEXT: fmul v0.4s, v3.4s, v1.4s
-; CHECK-IAENABLED-NEXT: fmla v0.4s, v2.4s, v4.4s
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: twosrc_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: ldp q1, q0, [x0]
-; CHECK-IADISABLED-NEXT: ldp q3, q2, [x1]
-; CHECK-IADISABLED-NEXT: uzp1 v4.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp2 v1.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp1 v5.4s, v3.4s, v2.4s
-; CHECK-IADISABLED-NEXT: uzp2 v2.4s, v3.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmul v0.4s, v5.4s, v4.4s
-; CHECK-IADISABLED-NEXT: fmla v0.4s, v1.4s, v2.4s
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: twosrc_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ld2 { v1.4s, v2.4s }, [x0]
+; CHECK-NEXT: ld2 { v3.4s, v4.4s }, [x1]
+; CHECK-NEXT: fmul v0.4s, v3.4s, v1.4s
+; CHECK-NEXT: fmla v0.4s, v2.4s, v4.4s
+; CHECK-NEXT: ret
entry:
%intrinsic.load.0 = load <8 x float>, ptr %pSrc1, align 4
%ldN = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %intrinsic.load.0)
@@ -286,25 +274,13 @@ entry:
}
define <4 x float> @twosrc2_intrinsic(ptr %pSrc1, ptr %pSrc2) {
-; CHECK-IAENABLED-LABEL: twosrc2_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: ld2 { v1.4s, v2.4s }, [x0]
-; CHECK-IAENABLED-NEXT: ld2 { v3.4s, v4.4s }, [x1]
-; CHECK-IAENABLED-NEXT: fmul v0.4s, v3.4s, v1.4s
-; CHECK-IAENABLED-NEXT: fmla v0.4s, v2.4s, v4.4s
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: twosrc2_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: ldp q1, q0, [x0]
-; CHECK-IADISABLED-NEXT: ldp q3, q2, [x1]
-; CHECK-IADISABLED-NEXT: uzp1 v4.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp2 v1.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp1 v5.4s, v3.4s, v2.4s
-; CHECK-IADISABLED-NEXT: uzp2 v2.4s, v3.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmul v0.4s, v5.4s, v4.4s
-; CHECK-IADISABLED-NEXT: fmla v0.4s, v1.4s, v2.4s
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: twosrc2_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ld2 { v1.4s, v2.4s }, [x0]
+; CHECK-NEXT: ld2 { v3.4s, v4.4s }, [x1]
+; CHECK-NEXT: fmul v0.4s, v3.4s, v1.4s
+; CHECK-NEXT: fmla v0.4s, v2.4s, v4.4s
+; CHECK-NEXT: ret
entry:
%intrinsic.load.0 = load <8 x float>, ptr %pSrc1, align 4
%ldN = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %intrinsic.load.0)
@@ -321,21 +297,12 @@ entry:
}
define <4 x float> @vld2_intrinsic(ptr %pSrc) {
-; CHECK-IAENABLED-LABEL: vld2_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: ld2 { v1.4s, v2.4s }, [x0]
-; CHECK-IAENABLED-NEXT: fmul v0.4s, v1.4s, v1.4s
-; CHECK-IAENABLED-NEXT: fmla v0.4s, v2.4s, v2.4s
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: vld2_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: ldp q1, q0, [x0]
-; CHECK-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp2 v1.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fmul v0.4s, v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmla v0.4s, v1.4s, v1.4s
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: vld2_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ld2 { v1.4s, v2.4s }, [x0]
+; CHECK-NEXT: fmul v0.4s, v1.4s, v1.4s
+; CHECK-NEXT: fmla v0.4s, v2.4s, v2.4s
+; CHECK-NEXT: ret
entry:
%intrinsic.load.0 = load <8 x float>, ptr %pSrc, align 4
%ldN = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %intrinsic.load.0)
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
index 434fb08c3d4b6..e82c7c2849cab 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
@@ -524,10 +524,10 @@ define <4 x float> @mul_triangle_external_use_intrinsic(<4 x float> %a, <4 x flo
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov d2, v0.d[1]
; CHECK-NEXT: mov d3, v1.d[1]
-; CHECK-NEXT: zip2 v4.2s, v0.2s, v2.2s
-; CHECK-NEXT: zip1 v5.2s, v1.2s, v3.2s
-; CHECK-NEXT: zip1 v0.2s, v0.2s, v2.2s
-; CHECK-NEXT: zip2 v1.2s, v1.2s, v3.2s
+; CHECK-NEXT: uzp2 v4.2s, v0.2s, v2.2s
+; CHECK-NEXT: uzp1 v5.2s, v1.2s, v3.2s
+; CHECK-NEXT: uzp1 v0.2s, v0.2s, v2.2s
+; CHECK-NEXT: uzp2 v1.2s, v1.2s, v3.2s
; CHECK-NEXT: fmul v2.2s, v4.2s, v5.2s
; CHECK-NEXT: fmul v3.2s, v1.2s, v4.2s
; CHECK-NEXT: fmla v2.2s, v0.2s, v1.2s
@@ -539,9 +539,7 @@ define <4 x float> @mul_triangle_external_use_intrinsic(<4 x float> %a, <4 x flo
; CHECK-NEXT: fneg v3.2s, v3.2s
; CHECK-NEXT: fmla v5.2s, v4.2s, v1.2s
; CHECK-NEXT: fmla v3.2s, v0.2s, v1.2s
-; CHECK-NEXT: mov v3.d[1], v5.d[0]
-; CHECK-NEXT: rev64 v0.4s, v3.4s
-; CHECK-NEXT: uzp1 v0.4s, v3.4s, v0.4s
+; CHECK-NEXT: zip1 v0.4s, v3.4s, v5.4s
; CHECK-NEXT: ret
entry:
%a.deinterleaved = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %a)
@@ -569,64 +567,33 @@ entry:
define <4 x float> @multiple_muls_shuffle_external_intrinsic(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, ptr %p1, ptr %p2) {
-; CHECK-IAENABLED-LABEL: multiple_muls_shuffle_external_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: mov d5, v0.d[1]
-; CHECK-IAENABLED-NEXT: mov d6, v1.d[1]
-; CHECK-IAENABLED-NEXT: mov d4, v2.d[1]
-; CHECK-IAENABLED-NEXT: zip2 v7.2s, v0.2s, v5.2s
-; CHECK-IAENABLED-NEXT: zip2 v16.2s, v1.2s, v6.2s
-; CHECK-IAENABLED-NEXT: zip1 v1.2s, v1.2s, v6.2s
-; CHECK-IAENABLED-NEXT: zip1 v0.2s, v0.2s, v5.2s
-; CHECK-IAENABLED-NEXT: fmul v5.2s, v1.2s, v7.2s
-; CHECK-IAENABLED-NEXT: fmul v6.2s, v16.2s, v7.2s
-; CHECK-IAENABLED-NEXT: zip1 v7.2s, v2.2s, v4.2s
-; CHECK-IAENABLED-NEXT: zip2 v4.2s, v2.2s, v4.2s
-; CHECK-IAENABLED-NEXT: fmla v5.2s, v0.2s, v16.2s
-; CHECK-IAENABLED-NEXT: fneg v6.2s, v6.2s
-; CHECK-IAENABLED-NEXT: fmla v6.2s, v0.2s, v1.2s
-; CHECK-IAENABLED-NEXT: fmul v17.2s, v7.2s, v5.2s
-; CHECK-IAENABLED-NEXT: movi v0.2d, #0000000000000000
-; CHECK-IAENABLED-NEXT: fmul v1.2s, v4.2s, v5.2s
-; CHECK-IAENABLED-NEXT: fmla v17.2s, v6.2s, v4.2s
-; CHECK-IAENABLED-NEXT: fcmla v0.4s, v2.4s, v3.4s, #0
-; CHECK-IAENABLED-NEXT: str d6, [x0]
-; CHECK-IAENABLED-NEXT: fneg v16.2s, v1.2s
-; CHECK-IAENABLED-NEXT: fcmla v0.4s, v2.4s, v3.4s, #90
-; CHECK-IAENABLED-NEXT: fmla v16.2s, v6.2s, v7.2s
-; CHECK-IAENABLED-NEXT: st2 { v16.2s, v17.2s }, [x1]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: multiple_muls_shuffle_external_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: mov d4, v1.d[1]
-; CHECK-IADISABLED-NEXT: mov d5, v0.d[1]
-; CHECK-IADISABLED-NEXT: zip1 v6.2s, v1.2s, v4.2s
-; CHECK-IADISABLED-NEXT: zip2 v7.2s, v0.2s, v5.2s
-; CHECK-IADISABLED-NEXT: zip1 v0.2s, v0.2s, v5.2s
-; CHECK-IADISABLED-NEXT: zip2 v1.2s, v1.2s, v4.2s
-; CHECK-IADISABLED-NEXT: mov d5, v2.d[1]
-; CHECK-IADISABLED-NEXT: fmul v4.2s, v6.2s, v7.2s
-; CHECK-IADISABLED-NEXT: fmla v4.2s, v0.2s, v1.2s
-; CHECK-IADISABLED-NEXT: fmul v1.2s, v1.2s, v7.2s
-; CHECK-IADISABLED-NEXT: zip2 v7.2s, v2.2s, v5.2s
-; CHECK-IADISABLED-NEXT: zip1 v5.2s, v2.2s, v5.2s
-; CHECK-IADISABLED-NEXT: fneg v1.2s, v1.2s
-; CHECK-IADISABLED-NEXT: fmul v16.2s, v7.2s, v4.2s
-; CHECK-IADISABLED-NEXT: fmul v4.2s, v5.2s, v4.2s
-; CHECK-IADISABLED-NEXT: fmla v1.2s, v0.2s, v6.2s
-; CHECK-IADISABLED-NEXT: fneg v6.2s, v16.2s
-; CHECK-IADISABLED-NEXT: movi v0.2d, #0000000000000000
-; CHECK-IADISABLED-NEXT: fmla v4.2s, v1.2s, v7.2s
-; CHECK-IADISABLED-NEXT: fmla v6.2s, v1.2s, v5.2s
-; CHECK-IADISABLED-NEXT: fcmla v0.4s, v2.4s, v3.4s, #0
-; CHECK-IADISABLED-NEXT: str d1, [x0]
-; CHECK-IADISABLED-NEXT: mov v6.d[1], v4.d[0]
-; CHECK-IADISABLED-NEXT: fcmla v0.4s, v2.4s, v3.4s, #90
-; CHECK-IADISABLED-NEXT: rev64 v4.4s, v6.4s
-; CHECK-IADISABLED-NEXT: uzp1 v2.4s, v6.4s, v4.4s
-; CHECK-IADISABLED-NEXT: str q2, [x1]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: multiple_muls_shuffle_external_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov d5, v0.d[1]
+; CHECK-NEXT: mov d6, v1.d[1]
+; CHECK-NEXT: mov d4, v2.d[1]
+; CHECK-NEXT: uzp2 v7.2s, v0.2s, v5.2s
+; CHECK-NEXT: uzp2 v16.2s, v1.2s, v6.2s
+; CHECK-NEXT: uzp1 v1.2s, v1.2s, v6.2s
+; CHECK-NEXT: uzp1 v0.2s, v0.2s, v5.2s
+; CHECK-NEXT: fmul v5.2s, v1.2s, v7.2s
+; CHECK-NEXT: fmul v6.2s, v16.2s, v7.2s
+; CHECK-NEXT: uzp1 v7.2s, v2.2s, v4.2s
+; CHECK-NEXT: uzp2 v4.2s, v2.2s, v4.2s
+; CHECK-NEXT: fmla v5.2s, v0.2s, v16.2s
+; CHECK-NEXT: fneg v6.2s, v6.2s
+; CHECK-NEXT: fmla v6.2s, v0.2s, v1.2s
+; CHECK-NEXT: fmul v17.2s, v7.2s, v5.2s
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: fmul v1.2s, v4.2s, v5.2s
+; CHECK-NEXT: fmla v17.2s, v6.2s, v4.2s
+; CHECK-NEXT: fcmla v0.4s, v2.4s, v3.4s, #0
+; CHECK-NEXT: str d6, [x0]
+; CHECK-NEXT: fneg v16.2s, v1.2s
+; CHECK-NEXT: fcmla v0.4s, v2.4s, v3.4s, #90
+; CHECK-NEXT: fmla v16.2s, v6.2s, v7.2s
+; CHECK-NEXT: st2 { v16.2s, v17.2s }, [x1]
+; CHECK-NEXT: ret
entry:
%a.deinterleaved = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %a)
%strided.vec = extractvalue { <2 x float>, <2 x float> } %a.deinterleaved, 0
@@ -667,66 +634,30 @@ entry:
define <4 x float> @multiple_muls_shuffle_external_with_loads_intrinsic(ptr %ptr_a, ptr %ptr_b, ptr %ptr_c, ptr %ptr_d, ptr %p1, ptr %p2) {
-; CHECK-IAENABLED-LABEL: multiple_muls_shuffle_external_with_loads_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: ld2 { v0.2s, v1.2s }, [x0]
-; CHECK-IAENABLED-NEXT: ld2 { v2.2s, v3.2s }, [x1]
-; CHECK-IAENABLED-NEXT: fmul v4.2s, v3.2s, v1.2s
-; CHECK-IAENABLED-NEXT: fmul v6.2s, v2.2s, v1.2s
-; CHECK-IAENABLED-NEXT: fneg v4.2s, v4.2s
-; CHECK-IAENABLED-NEXT: fmla v6.2s, v0.2s, v3.2s
-; CHECK-IAENABLED-NEXT: fmla v4.2s, v0.2s, v2.2s
-; CHECK-IAENABLED-NEXT: str d4, [x4]
-; CHECK-IAENABLED-NEXT: ldr q5, [x2]
-; CHECK-IAENABLED-NEXT: mov d7, v5.d[1]
-; CHECK-IAENABLED-NEXT: zip1 v0.2s, v5.2s, v7.2s
-; CHECK-IAENABLED-NEXT: zip2 v1.2s, v5.2s, v7.2s
-; CHECK-IAENABLED-NEXT: fmul v3.2s, v0.2s, v6.2s
-; CHECK-IAENABLED-NEXT: fmul v6.2s, v1.2s, v6.2s
-; CHECK-IAENABLED-NEXT: fmla v3.2s, v4.2s, v1.2s
-; CHECK-IAENABLED-NEXT: fneg v2.2s, v6.2s
-; CHECK-IAENABLED-NEXT: fmla v2.2s, v4.2s, v0.2s
-; CHECK-IAENABLED-NEXT: movi v0.2d, #0000000000000000
-; CHECK-IAENABLED-NEXT: st2 { v2.2s, v3.2s }, [x5]
-; CHECK-IAENABLED-NEXT: ldr q1, [x3]
-; CHECK-IAENABLED-NEXT: fcmla v0.4s, v5.4s, v1.4s, #0
-; CHECK-IAENABLED-NEXT: fcmla v0.4s, v5.4s, v1.4s, #90
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: multiple_muls_shuffle_external_with_loads_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-IADISABLED-NEXT: ldr q1, [x1]
-; CHECK-IADISABLED-NEXT: mov d2, v0.d[1]
-; CHECK-IADISABLED-NEXT: mov d3, v1.d[1]
-; CHECK-IADISABLED-NEXT: zip2 v4.2s, v0.2s, v2.2s
-; CHECK-IADISABLED-NEXT: zip2 v5.2s, v1.2s, v3.2s
-; CHECK-IADISABLED-NEXT: zip1 v0.2s, v0.2s, v2.2s
-; CHECK-IADISABLED-NEXT: zip1 v1.2s, v1.2s, v3.2s
-; CHECK-IADISABLED-NEXT: fmul v6.2s, v5.2s, v4.2s
-; CHECK-IADISABLED-NEXT: fneg v2.2s, v6.2s
-; CHECK-IADISABLED-NEXT: fmla v2.2s, v0.2s, v1.2s
-; CHECK-IADISABLED-NEXT: fmul v1.2s, v1.2s, v4.2s
-; CHECK-IADISABLED-NEXT: str d2, [x4]
-; CHECK-IADISABLED-NEXT: fmla v1.2s, v0.2s, v5.2s
-; CHECK-IADISABLED-NEXT: ldr q3, [x2]
-; CHECK-IADISABLED-NEXT: mov d4, v3.d[1]
-; CHECK-IADISABLED-NEXT: zip2 v0.2s, v3.2s, v4.2s
-; CHECK-IADISABLED-NEXT: zip1 v4.2s, v3.2s, v4.2s
-; CHECK-IADISABLED-NEXT: fmul v5.2s, v0.2s, v1.2s
-; CHECK-IADISABLED-NEXT: fmul v1.2s, v4.2s, v1.2s
-; CHECK-IADISABLED-NEXT: fneg v5.2s, v5.2s
-; CHECK-IADISABLED-NEXT: fmla v1.2s, v2.2s, v0.2s
-; CHECK-IADISABLED-NEXT: fmla v5.2s, v2.2s, v4.2s
-; CHECK-IADISABLED-NEXT: mov v5.d[1], v1.d[0]
-; CHECK-IADISABLED-NEXT: rev64 v0.4s, v5.4s
-; CHECK-IADISABLED-NEXT: uzp1 v1.4s, v5.4s, v0.4s
-; CHECK-IADISABLED-NEXT: movi v0.2d, #0000000000000000
-; CHECK-IADISABLED-NEXT: str q1, [x5]
-; CHECK-IADISABLED-NEXT: ldr q1, [x3]
-; CHECK-IADISABLED-NEXT: fcmla v0.4s, v3.4s, v1.4s, #0
-; CHECK-IADISABLED-NEXT: fcmla v0.4s, v3.4s, v1.4s, #90
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: multiple_muls_shuffle_external_with_loads_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ld2 { v0.2s, v1.2s }, [x0]
+; CHECK-NEXT: ld2 { v2.2s, v3.2s }, [x1]
+; CHECK-NEXT: fmul v4.2s, v3.2s, v1.2s
+; CHECK-NEXT: fmul v5.2s, v2.2s, v1.2s
+; CHECK-NEXT: fneg v4.2s, v4.2s
+; CHECK-NEXT: fmla v5.2s, v0.2s, v3.2s
+; CHECK-NEXT: fmla v4.2s, v0.2s, v2.2s
+; CHECK-NEXT: str d4, [x4]
+; CHECK-NEXT: ldr q6, [x2]
+; CHECK-NEXT: uzp1 v0.4s, v6.4s, v0.4s
+; CHECK-NEXT: uzp2 v1.4s, v6.4s, v0.4s
+; CHECK-NEXT: fmul v3.2s, v0.2s, v5.2s
+; CHECK-NEXT: fmul v5.2s, v1.2s, v5.2s
+; CHECK-NEXT: fmla v3.2s, v4.2s, v1.2s
+; CHECK-NEXT: fneg v2.2s, v5.2s
+; CHECK-NEXT: fmla v2.2s, v4.2s, v0.2s
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: st2 { v2.2s, v3.2s }, [x5]
+; CHECK-NEXT: ldr q1, [x3]
+; CHECK-NEXT: fcmla v0.4s, v6.4s, v1.4s, #0
+; CHECK-NEXT: fcmla v0.4s, v6.4s, v1.4s, #90
+; CHECK-NEXT: ret
entry:
%a = load <4 x float>, ptr %ptr_a
%a.deinterleaved = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %a)
@@ -771,80 +702,39 @@ entry:
define <4 x float> @multiple_muls_mul_external_intrinsic(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, ptr %p1, ptr %p2) {
-; CHECK-IAENABLED-LABEL: multiple_muls_mul_external_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: mov d4, v0.d[1]
-; CHECK-IAENABLED-NEXT: mov d5, v1.d[1]
-; CHECK-IAENABLED-NEXT: mov d16, v2.d[1]
-; CHECK-IAENABLED-NEXT: mov d17, v3.d[1]
-; CHECK-IAENABLED-NEXT: zip2 v6.2s, v0.2s, v4.2s
-; CHECK-IAENABLED-NEXT: zip2 v7.2s, v1.2s, v5.2s
-; CHECK-IAENABLED-NEXT: zip2 v19.2s, v2.2s, v16.2s
-; CHECK-IAENABLED-NEXT: zip1 v2.2s, v2.2s, v16.2s
-; CHECK-IAENABLED-NEXT: zip2 v16.2s, v3.2s, v17.2s
-; CHECK-IAENABLED-NEXT: zip1 v0.2s, v0.2s, v4.2s
-; CHECK-IAENABLED-NEXT: zip1 v1.2s, v1.2s, v5.2s
-; CHECK-IAENABLED-NEXT: zip1 v3.2s, v3.2s, v17.2s
-; CHECK-IAENABLED-NEXT: fmul v18.2s, v6.2s, v7.2s
-; CHECK-IAENABLED-NEXT: fmul v5.2s, v2.2s, v16.2s
-; CHECK-IAENABLED-NEXT: fmul v16.2s, v19.2s, v16.2s
-; CHECK-IAENABLED-NEXT: fmul v7.2s, v0.2s, v7.2s
-; CHECK-IAENABLED-NEXT: fneg v4.2s, v18.2s
-; CHECK-IAENABLED-NEXT: fmla v5.2s, v3.2s, v19.2s
-; CHECK-IAENABLED-NEXT: fmla v7.2s, v1.2s, v6.2s
-; CHECK-IAENABLED-NEXT: fmla v4.2s, v1.2s, v0.2s
-; CHECK-IAENABLED-NEXT: fneg v0.2s, v16.2s
-; CHECK-IAENABLED-NEXT: fmla v0.2s, v3.2s, v2.2s
-; CHECK-IAENABLED-NEXT: fmul v2.2s, v4.2s, v5.2s
-; CHECK-IAENABLED-NEXT: fmul v3.2s, v7.2s, v5.2s
-; CHECK-IAENABLED-NEXT: str d4, [x0]
-; CHECK-IAENABLED-NEXT: fmla v2.2s, v0.2s, v7.2s
-; CHECK-IAENABLED-NEXT: fneg v1.2s, v3.2s
-; CHECK-IAENABLED-NEXT: fmla v1.2s, v0.2s, v4.2s
-; CHECK-IAENABLED-NEXT: mov v0.d[1], v5.d[0]
-; CHECK-IAENABLED-NEXT: rev64 v3.4s, v0.4s
-; CHECK-IAENABLED-NEXT: st2 { v1.2s, v2.2s }, [x1]
-; CHECK-IAENABLED-NEXT: uzp1 v0.4s, v0.4s, v3.4s
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: multiple_muls_mul_external_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: mov d4, v0.d[1]
-; CHECK-IADISABLED-NEXT: mov d5, v1.d[1]
-; CHECK-IADISABLED-NEXT: mov d6, v2.d[1]
-; CHECK-IADISABLED-NEXT: mov d7, v3.d[1]
-; CHECK-IADISABLED-NEXT: zip1 v16.2s, v0.2s, v4.2s
-; CHECK-IADISABLED-NEXT: zip2 v17.2s, v1.2s, v5.2s
-; CHECK-IADISABLED-NEXT: zip2 v0.2s, v0.2s, v4.2s
-; CHECK-IADISABLED-NEXT: zip1 v4.2s, v2.2s, v6.2s
-; CHECK-IADISABLED-NEXT: zip2 v18.2s, v3.2s, v7.2s
-; CHECK-IADISABLED-NEXT: zip1 v1.2s, v1.2s, v5.2s
-; CHECK-IADISABLED-NEXT: zip2 v2.2s, v2.2s, v6.2s
-; CHECK-IADISABLED-NEXT: zip1 v3.2s, v3.2s, v7.2s
-; CHECK-IADISABLED-NEXT: fmul v5.2s, v16.2s, v17.2s
-; CHECK-IADISABLED-NEXT: fmul v6.2s, v0.2s, v17.2s
-; CHECK-IADISABLED-NEXT: fmul v7.2s, v4.2s, v18.2s
-; CHECK-IADISABLED-NEXT: fmla v5.2s, v1.2s, v0.2s
-; CHECK-IADISABLED-NEXT: fmul v0.2s, v2.2s, v18.2s
-; CHECK-IADISABLED-NEXT: fmla v7.2s, v3.2s, v2.2s
-; CHECK-IADISABLED-NEXT: fneg v2.2s, v6.2s
-; CHECK-IADISABLED-NEXT: fneg v0.2s, v0.2s
-; CHECK-IADISABLED-NEXT: fmla v2.2s, v1.2s, v16.2s
-; CHECK-IADISABLED-NEXT: fmul v1.2s, v5.2s, v7.2s
-; CHECK-IADISABLED-NEXT: fmla v0.2s, v3.2s, v4.2s
-; CHECK-IADISABLED-NEXT: fmul v3.2s, v2.2s, v7.2s
-; CHECK-IADISABLED-NEXT: fneg v1.2s, v1.2s
-; CHECK-IADISABLED-NEXT: str d2, [x0]
-; CHECK-IADISABLED-NEXT: fmla v3.2s, v0.2s, v5.2s
-; CHECK-IADISABLED-NEXT: fmla v1.2s, v0.2s, v2.2s
-; CHECK-IADISABLED-NEXT: mov v0.d[1], v7.d[0]
-; CHECK-IADISABLED-NEXT: mov v1.d[1], v3.d[0]
-; CHECK-IADISABLED-NEXT: rev64 v3.4s, v0.4s
-; CHECK-IADISABLED-NEXT: rev64 v4.4s, v1.4s
-; CHECK-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v3.4s
-; CHECK-IADISABLED-NEXT: uzp1 v1.4s, v1.4s, v4.4s
-; CHECK-IADISABLED-NEXT: str q1, [x1]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: multiple_muls_mul_external_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov d4, v0.d[1]
+; CHECK-NEXT: mov d5, v1.d[1]
+; CHECK-NEXT: mov d16, v2.d[1]
+; CHECK-NEXT: mov d17, v3.d[1]
+; CHECK-NEXT: uzp2 v6.2s, v0.2s, v4.2s
+; CHECK-NEXT: uzp2 v7.2s, v1.2s, v5.2s
+; CHECK-NEXT: uzp2 v19.2s, v2.2s, v16.2s
+; CHECK-NEXT: uzp1 v2.2s, v2.2s, v16.2s
+; CHECK-NEXT: uzp2 v16.2s, v3.2s, v17.2s
+; CHECK-NEXT: uzp1 v0.2s, v0.2s, v4.2s
+; CHECK-NEXT: uzp1 v1.2s, v1.2s, v5.2s
+; CHECK-NEXT: uzp1 v3.2s, v3.2s, v17.2s
+; CHECK-NEXT: fmul v18.2s, v6.2s, v7.2s
+; CHECK-NEXT: fmul v5.2s, v2.2s, v16.2s
+; CHECK-NEXT: fmul v16.2s, v19.2s, v16.2s
+; CHECK-NEXT: fmul v7.2s, v0.2s, v7.2s
+; CHECK-NEXT: fneg v4.2s, v18.2s
+; CHECK-NEXT: fmla v5.2s, v3.2s, v19.2s
+; CHECK-NEXT: fneg v16.2s, v16.2s
+; CHECK-NEXT: fmla v7.2s, v1.2s, v6.2s
+; CHECK-NEXT: fmla v4.2s, v1.2s, v0.2s
+; CHECK-NEXT: fmla v16.2s, v3.2s, v2.2s
+; CHECK-NEXT: fmul v0.2s, v7.2s, v5.2s
+; CHECK-NEXT: fmul v2.2s, v4.2s, v5.2s
+; CHECK-NEXT: str d4, [x0]
+; CHECK-NEXT: fmla v2.2s, v16.2s, v7.2s
+; CHECK-NEXT: fneg v1.2s, v0.2s
+; CHECK-NEXT: zip1 v0.4s, v16.4s, v5.4s
+; CHECK-NEXT: fmla v1.2s, v16.2s, v4.2s
+; CHECK-NEXT: st2 { v1.2s, v2.2s }, [x1]
+; CHECK-NEXT: ret
entry:
%a.deinterleaved = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %a)
%strided.vec = extractvalue { <2 x float>, <2 x float> } %a.deinterleaved, 0
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
index 355adec955e4b..ad6f77773d9fc 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
@@ -31,8 +31,8 @@ define dso_local %"struct.std::complex" @complex_mul_v2f64(ptr %a, ptr %b) {
; CHECK-NEXT: fcmla v0.2d, v4.2d, v2.2d, #90
; CHECK-NEXT: b.ne .LBB0_1
; CHECK-NEXT: // %bb.2: // %middle.block
-; CHECK-NEXT: zip2 v2.2d, v1.2d, v0.2d
-; CHECK-NEXT: zip1 v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: uzp2 v2.2d, v1.2d, v0.2d
+; CHECK-NEXT: uzp1 v0.2d, v1.2d, v0.2d
; CHECK-NEXT: faddp d0, v0.2d
; CHECK-NEXT: faddp d1, v2.2d
; CHECK-NEXT: ret
@@ -98,8 +98,8 @@ define %"struct.std::complex" @complex_mul_nonzero_init_v2f64(ptr %a, ptr %b) {
; CHECK-NEXT: fcmla v0.2d, v4.2d, v2.2d, #90
; CHECK-NEXT: b.ne .LBB1_1
; CHECK-NEXT: // %bb.2: // %middle.block
-; CHECK-NEXT: zip2 v2.2d, v1.2d, v0.2d
-; CHECK-NEXT: zip1 v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: uzp2 v2.2d, v1.2d, v0.2d
+; CHECK-NEXT: uzp1 v0.2d, v1.2d, v0.2d
; CHECK-NEXT: faddp d0, v0.2d
; CHECK-NEXT: faddp d1, v2.2d
; CHECK-NEXT: ret
@@ -168,10 +168,10 @@ define %"struct.std::complex" @complex_mul_v2f64_unrolled(ptr %a, ptr %b) {
; CHECK-NEXT: fcmla v3.2d, v18.2d, v16.2d, #90
; CHECK-NEXT: b.ne .LBB2_1
; CHECK-NEXT: // %bb.2: // %middle.block
-; CHECK-NEXT: zip2 v4.2d, v0.2d, v3.2d
-; CHECK-NEXT: zip1 v0.2d, v0.2d, v3.2d
-; CHECK-NEXT: zip2 v3.2d, v2.2d, v1.2d
-; CHECK-NEXT: zip1 v1.2d, v2.2d, v1.2d
+; CHECK-NEXT: uzp2 v4.2d, v0.2d, v3.2d
+; CHECK-NEXT: uzp1 v0.2d, v0.2d, v3.2d
+; CHECK-NEXT: uzp2 v3.2d, v2.2d, v1.2d
+; CHECK-NEXT: uzp1 v1.2d, v2.2d, v1.2d
; CHECK-NEXT: fadd v0.2d, v0.2d, v1.2d
; CHECK-NEXT: fadd v1.2d, v4.2d, v3.2d
; CHECK-NEXT: faddp d0, v0.2d
diff --git a/llvm/test/CodeGen/AArch64/fixed-deinterleave-intrinsics.ll b/llvm/test/CodeGen/AArch64/fixed-deinterleave-intrinsics.ll
index 09b6072e8aee2..e427e05848b82 100644
--- a/llvm/test/CodeGen/AArch64/fixed-deinterleave-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/fixed-deinterleave-intrinsics.ll
@@ -5,91 +5,18 @@
; RUN: llc -mtriple=aarch64-linux-gnu --lower-interleaved-accesses=false < %s -mattr=+sve -force-streaming-compatible | FileCheck %s --check-prefixes=SVE-FIXED,SVE-FIXED-IADISABLED
define void @deinterleave_i8_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_i8_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.16b, v1.16b }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_i8_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: uzp1 v2.16b, v1.16b, v0.16b
-; NEON-IADISABLED-NEXT: uzp2 v0.16b, v1.16b, v0.16b
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_i8_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.16b, v1.16b }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_i8_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
-; SVE-FIXED-NEXT: .cfi_def_cfa_offset 16
-; SVE-FIXED-NEXT: .cfi_offset b8, -16
-; SVE-FIXED-NEXT: ldp q0, q1, [x0]
-; SVE-FIXED-NEXT: mov z2.b, z1.b[15]
-; SVE-FIXED-NEXT: mov z3.b, z1.b[13]
-; SVE-FIXED-NEXT: mov z4.b, z1.b[11]
-; SVE-FIXED-NEXT: mov z5.b, z1.b[9]
-; SVE-FIXED-NEXT: mov z6.b, z1.b[7]
-; SVE-FIXED-NEXT: mov z7.b, z1.b[5]
-; SVE-FIXED-NEXT: mov z18.b, z0.b[15]
-; SVE-FIXED-NEXT: mov z19.b, z0.b[13]
-; SVE-FIXED-NEXT: mov z20.b, z1.b[14]
-; SVE-FIXED-NEXT: mov z21.b, z1.b[12]
-; SVE-FIXED-NEXT: mov z16.b, z1.b[3]
-; SVE-FIXED-NEXT: mov z17.b, z1.b[1]
-; SVE-FIXED-NEXT: zip1 z2.b, z3.b, z2.b
-; SVE-FIXED-NEXT: zip1 z3.b, z5.b, z4.b
-; SVE-FIXED-NEXT: zip1 z4.b, z7.b, z6.b
-; SVE-FIXED-NEXT: zip1 z6.b, z19.b, z18.b
-; SVE-FIXED-NEXT: mov z22.b, z1.b[6]
-; SVE-FIXED-NEXT: mov z23.b, z1.b[4]
-; SVE-FIXED-NEXT: zip1 z19.b, z21.b, z20.b
-; SVE-FIXED-NEXT: mov z20.b, z1.b[10]
-; SVE-FIXED-NEXT: mov z21.b, z1.b[8]
-; SVE-FIXED-NEXT: mov z24.b, z1.b[2]
-; SVE-FIXED-NEXT: mov z25.b, z0.b[14]
-; SVE-FIXED-NEXT: mov z26.b, z0.b[12]
-; SVE-FIXED-NEXT: mov z27.b, z0.b[10]
-; SVE-FIXED-NEXT: mov z28.b, z0.b[8]
-; SVE-FIXED-NEXT: mov z29.b, z0.b[6]
-; SVE-FIXED-NEXT: mov z30.b, z0.b[4]
-; SVE-FIXED-NEXT: mov z31.b, z0.b[2]
-; SVE-FIXED-NEXT: zip1 z5.b, z17.b, z16.b
-; SVE-FIXED-NEXT: mov z7.b, z0.b[11]
-; SVE-FIXED-NEXT: mov z16.b, z0.b[9]
-; SVE-FIXED-NEXT: mov z17.b, z0.b[7]
-; SVE-FIXED-NEXT: mov z18.b, z0.b[5]
-; SVE-FIXED-NEXT: mov z8.b, z0.b[3]
-; SVE-FIXED-NEXT: zip1 z20.b, z21.b, z20.b
-; SVE-FIXED-NEXT: mov z21.b, z0.b[1]
-; SVE-FIXED-NEXT: zip1 z22.b, z23.b, z22.b
-; SVE-FIXED-NEXT: zip1 z1.b, z1.b, z24.b
-; SVE-FIXED-NEXT: zip1 z23.b, z26.b, z25.b
-; SVE-FIXED-NEXT: zip1 z24.b, z28.b, z27.b
-; SVE-FIXED-NEXT: zip1 z25.b, z30.b, z29.b
-; SVE-FIXED-NEXT: zip1 z0.b, z0.b, z31.b
-; SVE-FIXED-NEXT: zip1 z7.b, z16.b, z7.b
-; SVE-FIXED-NEXT: zip1 z16.b, z18.b, z17.b
-; SVE-FIXED-NEXT: zip1 z17.b, z21.b, z8.b
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z20.h, z19.h
-; SVE-FIXED-NEXT: zip1 z1.h, z1.h, z22.h
-; SVE-FIXED-NEXT: zip1 z18.h, z24.h, z23.h
-; SVE-FIXED-NEXT: zip1 z4.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z0.h, z0.h, z25.h
-; SVE-FIXED-NEXT: zip1 z5.h, z7.h, z6.h
-; SVE-FIXED-NEXT: zip1 z6.h, z17.h, z16.h
-; SVE-FIXED-NEXT: zip1 z1.s, z1.s, z3.s
-; SVE-FIXED-NEXT: zip1 z2.s, z4.s, z2.s
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z18.s
-; SVE-FIXED-NEXT: zip1 z3.s, z6.s, z5.s
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
-; SVE-FIXED-NEXT: // fake_use: $q1 $z1
-; SVE-FIXED-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
+; SVE-FIXED-NEXT: ld2 { v0.16b, v1.16b }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <32 x i8>, ptr %ptr, align 1
%deinterleave = tail call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2.v32i8(<32 x i8> %load)
@@ -101,55 +28,18 @@ define void @deinterleave_i8_factor2(ptr %ptr) {
}
define void @deinterleave_i16_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_i16_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_i16_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: uzp1 v2.8h, v1.8h, v0.8h
-; NEON-IADISABLED-NEXT: uzp2 v0.8h, v1.8h, v0.8h
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_i16_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_i16_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q1, q0, [x0]
-; SVE-FIXED-NEXT: mov z2.h, z0.h[7]
-; SVE-FIXED-NEXT: mov z3.h, z0.h[5]
-; SVE-FIXED-NEXT: mov z7.h, z0.h[6]
-; SVE-FIXED-NEXT: mov z16.h, z0.h[4]
-; SVE-FIXED-NEXT: mov z17.h, z0.h[2]
-; SVE-FIXED-NEXT: mov z18.h, z1.h[6]
-; SVE-FIXED-NEXT: mov z19.h, z1.h[4]
-; SVE-FIXED-NEXT: mov z20.h, z1.h[2]
-; SVE-FIXED-NEXT: mov z4.h, z0.h[3]
-; SVE-FIXED-NEXT: mov z5.h, z0.h[1]
-; SVE-FIXED-NEXT: mov z6.h, z1.h[7]
-; SVE-FIXED-NEXT: mov z21.h, z1.h[5]
-; SVE-FIXED-NEXT: mov z22.h, z1.h[3]
-; SVE-FIXED-NEXT: mov z23.h, z1.h[1]
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z16.h, z7.h
-; SVE-FIXED-NEXT: zip1 z0.h, z0.h, z17.h
-; SVE-FIXED-NEXT: zip1 z7.h, z19.h, z18.h
-; SVE-FIXED-NEXT: zip1 z1.h, z1.h, z20.h
-; SVE-FIXED-NEXT: zip1 z4.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z5.h, z21.h, z6.h
-; SVE-FIXED-NEXT: zip1 z6.h, z23.h, z22.h
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z3.s
-; SVE-FIXED-NEXT: zip1 z1.s, z1.s, z7.s
-; SVE-FIXED-NEXT: zip1 z2.s, z4.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z6.s, z5.s
-; SVE-FIXED-NEXT: zip1 z0.d, z1.d, z0.d
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
-; SVE-FIXED-NEXT: // fake_use: $q1 $z1
+; SVE-FIXED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <16 x i16>, ptr %ptr, align 2
%deinterleave = tail call { <8 x i16>, <8 x i16> } @llvm.vector.deinterleave2.v16i16(<16 x i16> %load)
@@ -161,39 +51,18 @@ define void @deinterleave_i16_factor2(ptr %ptr) {
}
define void @deinterleave_8xi32_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_8xi32_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_8xi32_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; NEON-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_8xi32_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_8xi32_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q0, q1, [x0]
-; SVE-FIXED-NEXT: mov z3.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z4.s, z0.s[2]
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z5.s, z1.s[1]
-; SVE-FIXED-NEXT: mov z6.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z7.s, z0.s[1]
-; SVE-FIXED-NEXT: zip1 z1.s, z1.s, z3.s
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z4.s
-; SVE-FIXED-NEXT: zip1 z2.s, z5.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z7.s, z6.s
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
-; SVE-FIXED-NEXT: // fake_use: $q1 $z1
+; SVE-FIXED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <8 x i32>, ptr %ptr, align 4
%deinterleave = tail call { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2.v8i32(<8 x i32> %load)
@@ -205,29 +74,18 @@ define void @deinterleave_8xi32_factor2(ptr %ptr) {
}
define void @deinterleave_i64_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_i64_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_i64_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: zip1 v2.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: zip2 v0.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_i64_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_i64_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q1, q0, [x0]
-; SVE-FIXED-NEXT: zip1 z2.d, z1.d, z0.d
-; SVE-FIXED-NEXT: trn2 z0.d, z1.d, z0.d
-; SVE-FIXED-NEXT: // fake_use: $q2 $z2
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
+; SVE-FIXED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <4 x i64>, ptr %ptr, align 8
%deinterleave = tail call { <2 x i64>, <2 x i64> } @llvm.vector.deinterleave2.v4i64(<4 x i64> %load)
@@ -239,39 +97,18 @@ define void @deinterleave_i64_factor2(ptr %ptr) {
}
define void @deinterleave_float_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_float_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_float_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; NEON-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_float_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_float_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q0, q1, [x0]
-; SVE-FIXED-NEXT: mov z3.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z4.s, z0.s[2]
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z5.s, z1.s[1]
-; SVE-FIXED-NEXT: mov z6.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z7.s, z0.s[1]
-; SVE-FIXED-NEXT: zip1 z1.s, z1.s, z3.s
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z4.s
-; SVE-FIXED-NEXT: zip1 z2.s, z5.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z7.s, z6.s
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
-; SVE-FIXED-NEXT: // fake_use: $q1 $z1
+; SVE-FIXED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <8 x float>, ptr %ptr, align 4
%deinterleave = tail call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %load)
@@ -283,29 +120,18 @@ define void @deinterleave_float_factor2(ptr %ptr) {
}
define void @deinterleave_double_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_double_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_double_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: zip1 v2.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: zip2 v0.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_double_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_double_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q1, q0, [x0]
-; SVE-FIXED-NEXT: zip1 z2.d, z1.d, z0.d
-; SVE-FIXED-NEXT: trn2 z0.d, z1.d, z0.d
-; SVE-FIXED-NEXT: // fake_use: $q2 $z2
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
+; SVE-FIXED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <4 x double>, ptr %ptr, align 8
%deinterleave = tail call { <2 x double>, <2 x double> } @llvm.vector.deinterleave2.v4f64(<4 x double> %load)
@@ -317,29 +143,18 @@ define void @deinterleave_double_factor2(ptr %ptr) {
}
define void @deinterleave_ptr_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_ptr_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_ptr_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: zip1 v2.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: zip2 v0.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_ptr_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_ptr_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q1, q0, [x0]
-; SVE-FIXED-NEXT: zip1 z2.d, z1.d, z0.d
-; SVE-FIXED-NEXT: trn2 z0.d, z1.d, z0.d
-; SVE-FIXED-NEXT: // fake_use: $q2 $z2
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
+; SVE-FIXED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <4 x ptr>, ptr %ptr, align 8
%deinterleave = tail call { <2 x ptr>, <2 x ptr> } @llvm.vector.deinterleave2.v4p0(<4 x ptr> %load)
@@ -351,57 +166,19 @@ define void @deinterleave_ptr_factor2(ptr %ptr) {
}
define void @interleave_i8_factor2(ptr %ptr, <16 x i8> %l, <16 x i8> %r) {
-; NEON-IAENABLED-LABEL: interleave_i8_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.16b, v1.16b }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i8_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.16b, v0.16b, v1.16b
-; NEON-IADISABLED-NEXT: zip1 v0.16b, v0.16b, v1.16b
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i8_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.16b, v1.16b }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i8_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.b, z1.b[15]
-; SVE-FIXED-NEXT: mov z3.b, z0.b[15]
-; SVE-FIXED-NEXT: mov z4.b, z1.b[14]
-; SVE-FIXED-NEXT: mov z5.b, z0.b[14]
-; SVE-FIXED-NEXT: mov z6.b, z1.b[13]
-; SVE-FIXED-NEXT: mov z7.b, z0.b[13]
-; SVE-FIXED-NEXT: mov z16.b, z1.b[12]
-; SVE-FIXED-NEXT: mov z17.b, z0.b[12]
-; SVE-FIXED-NEXT: mov z18.b, z1.b[11]
-; SVE-FIXED-NEXT: mov z19.b, z0.b[11]
-; SVE-FIXED-NEXT: mov z20.b, z1.b[10]
-; SVE-FIXED-NEXT: mov z21.b, z0.b[10]
-; SVE-FIXED-NEXT: mov z22.b, z1.b[9]
-; SVE-FIXED-NEXT: mov z23.b, z0.b[9]
-; SVE-FIXED-NEXT: mov z24.b, z1.b[8]
-; SVE-FIXED-NEXT: mov z25.b, z0.b[8]
-; SVE-FIXED-NEXT: zip1 z2.b, z3.b, z2.b
-; SVE-FIXED-NEXT: zip1 z3.b, z5.b, z4.b
-; SVE-FIXED-NEXT: zip1 z4.b, z7.b, z6.b
-; SVE-FIXED-NEXT: zip1 z5.b, z17.b, z16.b
-; SVE-FIXED-NEXT: zip1 z6.b, z19.b, z18.b
-; SVE-FIXED-NEXT: zip1 z7.b, z21.b, z20.b
-; SVE-FIXED-NEXT: zip1 z16.b, z23.b, z22.b
-; SVE-FIXED-NEXT: zip1 z0.b, z0.b, z1.b
-; SVE-FIXED-NEXT: zip1 z17.b, z25.b, z24.b
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z4.h, z7.h, z6.h
-; SVE-FIXED-NEXT: zip1 z5.h, z17.h, z16.h
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.b, vl16
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2b { z0.b, z1.b }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8> %l, <16 x i8> %r)
store <32 x i8> %interleave, ptr %ptr, align 1
@@ -409,41 +186,19 @@ define void @interleave_i8_factor2(ptr %ptr, <16 x i8> %l, <16 x i8> %r) {
}
define void @interleave_i16_factor2(ptr %ptr, <8 x i16> %l, <8 x i16> %r) {
-; NEON-IAENABLED-LABEL: interleave_i16_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.8h, v1.8h }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i16_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; NEON-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i16_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.8h, v1.8h }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i16_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.h, z1.h[7]
-; SVE-FIXED-NEXT: mov z3.h, z0.h[7]
-; SVE-FIXED-NEXT: mov z4.h, z1.h[6]
-; SVE-FIXED-NEXT: mov z5.h, z0.h[6]
-; SVE-FIXED-NEXT: mov z6.h, z1.h[5]
-; SVE-FIXED-NEXT: mov z7.h, z0.h[5]
-; SVE-FIXED-NEXT: mov z16.h, z1.h[4]
-; SVE-FIXED-NEXT: mov z17.h, z0.h[4]
-; SVE-FIXED-NEXT: zip1 z0.h, z0.h, z1.h
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z4.h, z7.h, z6.h
-; SVE-FIXED-NEXT: zip1 z5.h, z17.h, z16.h
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.h, vl8
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2h { z0.h, z1.h }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %l, <8 x i16> %r)
store <16 x i16> %interleave, ptr %ptr, align 2
@@ -451,33 +206,19 @@ define void @interleave_i16_factor2(ptr %ptr, <8 x i16> %l, <8 x i16> %r) {
}
define void @interleave_i32_factor2(ptr %ptr, <4 x i32> %l, <4 x i32> %r) {
-; NEON-IAENABLED-LABEL: interleave_i32_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i32_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i32_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i32_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z3.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z4.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z5.s, z0.s[2]
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z1.s
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.s, vl4
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %l, <4 x i32> %r)
store <8 x i32> %interleave, ptr %ptr, align 4
@@ -485,27 +226,19 @@ define void @interleave_i32_factor2(ptr %ptr, <4 x i32> %l, <4 x i32> %r) {
}
define void @interleave_i64_factor2(ptr %ptr, <2 x i64> %l, <2 x i64> %r) {
-; NEON-IAENABLED-LABEL: interleave_i64_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i64_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i64_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i64_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %l, <2 x i64> %r)
store <4 x i64> %interleave, ptr %ptr, align 8
@@ -513,33 +246,19 @@ define void @interleave_i64_factor2(ptr %ptr, <2 x i64> %l, <2 x i64> %r) {
}
define void @interleave_float_factor2(ptr %ptr, <4 x float> %l, <4 x float> %r) {
-; NEON-IAENABLED-LABEL: interleave_float_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_float_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_float_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_float_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z3.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z4.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z5.s, z0.s[2]
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z1.s
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.s, vl4
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %l, <4 x float> %r)
store <8 x float> %interleave, ptr %ptr, align 4
@@ -547,27 +266,19 @@ define void @interleave_float_factor2(ptr %ptr, <4 x float> %l, <4 x float> %r)
}
define void @interleave_double_factor2(ptr %ptr, <2 x double> %l, <2 x double> %r) {
-; NEON-IAENABLED-LABEL: interleave_double_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_double_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_double_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_double_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %l, <2 x double> %r)
store <4 x double> %interleave, ptr %ptr, align 4
@@ -575,27 +286,19 @@ define void @interleave_double_factor2(ptr %ptr, <2 x double> %l, <2 x double> %
}
define void @interleave_ptr_factor2(ptr %ptr, <2 x ptr> %l, <2 x ptr> %r) {
-; NEON-IAENABLED-LABEL: interleave_ptr_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_ptr_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_ptr_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_ptr_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x ptr> @llvm.vector.interleave2.v4p0(<2 x ptr> %l, <2 x ptr> %r)
store <4 x ptr> %interleave, ptr %ptr, align 4
@@ -770,27 +473,19 @@ define void @interleave_wide_ptr_factor2(ptr %ptr, <8 x ptr> %l, <8 x ptr> %r) {
}
define void @interleave_double_factor2_intrinsic(ptr %ptr, <2 x double> %l, <2 x double> %r) {
-; NEON-IAENABLED-LABEL: interleave_double_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_double_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_double_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_double_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %l, <2 x double> %r)
store <4 x double> %interleave, ptr %ptr, align 4
@@ -798,33 +493,19 @@ define void @interleave_double_factor2_intrinsic(ptr %ptr, <2 x double> %l, <2 x
}
define void @interleave_float_factor2_intrinsic(ptr %ptr, <4 x float> %l, <4 x float> %r) {
-; NEON-IAENABLED-LABEL: interleave_float_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_float_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_float_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_float_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z3.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z4.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z5.s, z0.s[2]
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z1.s
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.s, vl4
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %l, <4 x float> %r)
store <8 x float> %interleave, ptr %ptr, align 4
@@ -832,41 +513,19 @@ define void @interleave_float_factor2_intrinsic(ptr %ptr, <4 x float> %l, <4 x f
}
define void @interleave_i16_factor2_intrinsic(ptr %ptr, <8 x i16> %l, <8 x i16> %r) {
-; NEON-IAENABLED-LABEL: interleave_i16_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.8h, v1.8h }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i16_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; NEON-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i16_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.8h, v1.8h }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i16_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.h, z1.h[7]
-; SVE-FIXED-NEXT: mov z3.h, z0.h[7]
-; SVE-FIXED-NEXT: mov z4.h, z1.h[6]
-; SVE-FIXED-NEXT: mov z5.h, z0.h[6]
-; SVE-FIXED-NEXT: mov z6.h, z1.h[5]
-; SVE-FIXED-NEXT: mov z7.h, z0.h[5]
-; SVE-FIXED-NEXT: mov z16.h, z1.h[4]
-; SVE-FIXED-NEXT: mov z17.h, z0.h[4]
-; SVE-FIXED-NEXT: zip1 z0.h, z0.h, z1.h
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z4.h, z7.h, z6.h
-; SVE-FIXED-NEXT: zip1 z5.h, z17.h, z16.h
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.h, vl8
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2h { z0.h, z1.h }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %l, <8 x i16> %r)
store <16 x i16> %interleave, ptr %ptr, align 2
@@ -874,33 +533,19 @@ define void @interleave_i16_factor2_intrinsic(ptr %ptr, <8 x i16> %l, <8 x i16>
}
define void @interleave_i32_factor2_intrinsic(ptr %ptr, <4 x i32> %l, <4 x i32> %r) {
-; NEON-IAENABLED-LABEL: interleave_i32_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i32_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i32_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i32_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z3.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z4.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z5.s, z0.s[2]
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z1.s
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.s, vl4
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %l, <4 x i32> %r)
store <8 x i32> %interleave, ptr %ptr, align 4
@@ -908,27 +553,19 @@ define void @interleave_i32_factor2_intrinsic(ptr %ptr, <4 x i32> %l, <4 x i32>
}
define void @interleave_i64_factor2_intrinsic(ptr %ptr, <2 x i64> %l, <2 x i64> %r) {
-; NEON-IAENABLED-LABEL: interleave_i64_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i64_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i64_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i64_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %l, <2 x i64> %r)
store <4 x i64> %interleave, ptr %ptr, align 8
@@ -936,57 +573,19 @@ define void @interleave_i64_factor2_intrinsic(ptr %ptr, <2 x i64> %l, <2 x i64>
}
define void @interleave_i8_factor2_intrinsic(ptr %ptr, <16 x i8> %l, <16 x i8> %r) {
-; NEON-IAENABLED-LABEL: interleave_i8_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.16b, v1.16b }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i8_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.16b, v0.16b, v1.16b
-; NEON-IADISABLED-NEXT: zip1 v0.16b, v0.16b, v1.16b
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i8_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.16b, v1.16b }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i8_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.b, z1.b[15]
-; SVE-FIXED-NEXT: mov z3.b, z0.b[15]
-; SVE-FIXED-NEXT: mov z4.b, z1.b[14]
-; SVE-FIXED-NEXT: mov z5.b, z0.b[14]
-; SVE-FIXED-NEXT: mov z6.b, z1.b[13]
-; SVE-FIXED-NEXT: mov z7.b, z0.b[13]
-; SVE-FIXED-NEXT: mov z16.b, z1.b[12]
-; SVE-FIXED-NEXT: mov z17.b, z0.b[12]
-; SVE-FIXED-NEXT: mov z18.b, z1.b[11]
-; SVE-FIXED-NEXT: mov z19.b, z0.b[11]
-; SVE-FIXED-NEXT: mov z20.b, z1.b[10]
-; SVE-FIXED-NEXT: mov z21.b, z0.b[10]
-; SVE-FIXED-NEXT: mov z22.b, z1.b[9]
-; SVE-FIXED-NEXT: mov z23.b, z0.b[9]
-; SVE-FIXED-NEXT: mov z24.b, z1.b[8]
-; SVE-FIXED-NEXT: mov z25.b, z0.b[8]
-; SVE-FIXED-NEXT: zip1 z2.b, z3.b, z2.b
-; SVE-FIXED-NEXT: zip1 z3.b, z5.b, z4.b
-; SVE-FIXED-NEXT: zip1 z4.b, z7.b, z6.b
-; SVE-FIXED-NEXT: zip1 z5.b, z17.b, z16.b
-; SVE-FIXED-NEXT: zip1 z6.b, z19.b, z18.b
-; SVE-FIXED-NEXT: zip1 z7.b, z21.b, z20.b
-; SVE-FIXED-NEXT: zip1 z16.b, z23.b, z22.b
-; SVE-FIXED-NEXT: zip1 z0.b, z0.b, z1.b
-; SVE-FIXED-NEXT: zip1 z17.b, z25.b, z24.b
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z4.h, z7.h, z6.h
-; SVE-FIXED-NEXT: zip1 z5.h, z17.h, z16.h
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.b, vl16
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2b { z0.b, z1.b }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8> %l, <16 x i8> %r)
store <32 x i8> %interleave, ptr %ptr, align 1
@@ -994,27 +593,19 @@ define void @interleave_i8_factor2_intrinsic(ptr %ptr, <16 x i8> %l, <16 x i8> %
}
define void @interleave_ptr_factor2_intrinsic(ptr %ptr, <2 x ptr> %l, <2 x ptr> %r) {
-; NEON-IAENABLED-LABEL: interleave_ptr_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_ptr_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_ptr_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_ptr_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x ptr> @llvm.vector.interleave2.v4p0(<2 x ptr> %l, <2 x ptr> %r)
store <4 x ptr> %interleave, ptr %ptr, align 4
@@ -1086,6 +677,5 @@ define void @interleave_wide_ptr_factor2_intrinsic(ptr %ptr, <8 x ptr> %l, <8 x
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; NEON: {{.*}}
; SVE-FIXED-IADISABLED: {{.*}}
; SVE-FIXED-IAENABLED: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/fixed-length-sve-interleave.ll b/llvm/test/CodeGen/AArch64/fixed-length-sve-interleave.ll
index 1278606f5b63f..3c0dc8d99dc76 100644
--- a/llvm/test/CodeGen/AArch64/fixed-length-sve-interleave.ll
+++ b/llvm/test/CodeGen/AArch64/fixed-length-sve-interleave.ll
@@ -5,20 +5,15 @@
define void @store_factor2_intrinsic(ptr %ptr, <16 x i16> %v0, <16 x i16> %v1) vscale_range(2,2) {
; CHECK-LABEL: store_factor2_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.h, vl8
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: adrp x8, .LCPI0_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI0_0
-; CHECK-NEXT: ldr z4, [x8]
-; CHECK-NEXT: splice z1.h, p0, z1.h, z3.h
-; CHECK-NEXT: splice z0.h, p0, z0.h, z2.h
-; CHECK-NEXT: tbl z1.h, { z1.h }, z4.h
-; CHECK-NEXT: tbl z0.h, { z0.h }, z4.h
-; CHECK-NEXT: str z1, [x0, #1, mul vl]
-; CHECK-NEXT: str z0, [x0]
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.h, p0, z5.h, z3.h
+; CHECK-NEXT: splice z4.h, p0, z4.h, z1.h
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: st2h { z4.h, z5.h }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <32 x i16> @llvm.vector.interleave2.v32i16(<16 x i16> %v0, <16 x i16> %v1)
store <32 x i16> %interleaved.vec, ptr %ptr, align 4
diff --git a/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll b/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
index 426fb4b472cbe..7b4e622034c81 100644
--- a/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
+++ b/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
@@ -5,21 +5,12 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -lower-interleaved-accesses=false -global-isel -global-isel-abort=0 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define {<2 x half>, <2 x half>} @vector_deinterleave_v2f16_v4f16(<4 x half> %vec) {
-; CHECK-SD-LABEL: vector_deinterleave_v2f16_v4f16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: dup v1.2s, v0.s[1]
-; CHECK-SD-NEXT: zip1 v2.4h, v0.4h, v1.4h
-; CHECK-SD-NEXT: trn2 v1.4h, v0.4h, v1.4h
-; CHECK-SD-NEXT: fmov d0, d2
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vector_deinterleave_v2f16_v4f16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: uzp1 v2.4h, v0.4h, v0.4h
-; CHECK-GI-NEXT: uzp2 v1.4h, v0.4h, v0.4h
-; CHECK-GI-NEXT: fmov d0, d2
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vector_deinterleave_v2f16_v4f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: uzp1 v2.4h, v0.4h, v0.4h
+; CHECK-NEXT: uzp2 v1.4h, v0.4h, v0.4h
+; CHECK-NEXT: fmov d0, d2
+; CHECK-NEXT: ret
%retval = call {<2 x half>, <2 x half>} @llvm.vector.deinterleave2.v4f16(<4 x half> %vec)
ret {<2 x half>, <2 x half>} %retval
}
@@ -51,8 +42,8 @@ define {<2 x float>, <2 x float>} @vector_deinterleave_v2f32_v4f32(<4 x float> %
; CHECK-SD-LABEL: vector_deinterleave_v2f32_v4f32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov d1, v0.d[1]
-; CHECK-SD-NEXT: zip1 v2.2s, v0.2s, v1.2s
-; CHECK-SD-NEXT: zip2 v1.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: uzp1 v2.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: uzp2 v1.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: fmov d0, d2
; CHECK-SD-NEXT: ret
;
@@ -79,12 +70,19 @@ ret {<4 x float>, <4 x float>} %retval
}
define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double> %vec) {
-; CHECK-LABEL: vector_deinterleave_v2f64_v4f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-NEXT: zip2 v1.2d, v0.2d, v1.2d
-; CHECK-NEXT: mov v0.16b, v2.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vector_deinterleave_v2f64_v4f64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uzp1 v2.2d, v0.2d, v1.2d
+; CHECK-SD-NEXT: uzp2 v1.2d, v0.2d, v1.2d
+; CHECK-SD-NEXT: mov v0.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vector_deinterleave_v2f64_v4f64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: zip1 v2.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: zip2 v1.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%retval = call {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double> %vec)
ret {<2 x double>, <2 x double>} %retval
}
@@ -125,12 +123,19 @@ define {<4 x i32>, <4 x i32>} @vector_deinterleave_v4i32_v8i32(<8 x i32> %vec) {
}
define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
-; CHECK-LABEL: vector_deinterleave_v2i64_v4i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-NEXT: zip2 v1.2d, v0.2d, v1.2d
-; CHECK-NEXT: mov v0.16b, v2.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vector_deinterleave_v2i64_v4i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uzp1 v2.2d, v0.2d, v1.2d
+; CHECK-SD-NEXT: uzp2 v1.2d, v0.2d, v1.2d
+; CHECK-SD-NEXT: mov v0.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vector_deinterleave_v2i64_v4i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: zip1 v2.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: zip2 v1.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%retval = call {<2 x i64>, <2 x i64>} @llvm.vector.deinterleave2.v4i64(<4 x i64> %vec)
ret {<2 x i64>, <2 x i64>} %retval
}
diff --git a/llvm/test/CodeGen/AArch64/fixed-vector-interleave-odd-factor.ll b/llvm/test/CodeGen/AArch64/fixed-vector-interleave-odd-factor.ll
new file mode 100644
index 0000000000000..7efb4df681687
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/fixed-vector-interleave-odd-factor.ll
@@ -0,0 +1,131 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s
+
+define { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } @deinterleave5_v10i16(<10 x i16> %vec) {
+; CHECK-LABEL: deinterleave5_v10i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s1, w1
+; CHECK-NEXT: fmov s4, w4
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: fmov s3, w3
+; CHECK-NEXT: fmov s0, w0
+; CHECK-NEXT: add x9, sp, #8
+; CHECK-NEXT: fmov s2, w2
+; CHECK-NEXT: mov v1.s[1], w6
+; CHECK-NEXT: ld1 { v4.h }[2], [x9]
+; CHECK-NEXT: mov v0.s[1], w5
+; CHECK-NEXT: ld1 { v3.h }[2], [x8]
+; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
+; CHECK-NEXT: // kill: def $d4 killed $d4 killed $q4
+; CHECK-NEXT: mov v2.s[1], w7
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: // kill: def $d3 killed $d3 killed $q3
+; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NEXT: ret
+ %result = call { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } @llvm.vector.deinterleave5.v10i16(<10 x i16> %vec)
+ ret { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } %result
+}
+
+define <10 x i16> @interleave5_v10i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e) {
+; CHECK-LABEL: interleave5_v10i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d3 killed $d3 def $q3
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d4 killed $d4 def $q4
+; CHECK-NEXT: adrp x9, .LCPI1_0
+; CHECK-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: uzp1 v16.4s, v0.4s, v2.4s
+; CHECK-NEXT: uzp2 v1.4s, v0.4s, v2.4s
+; CHECK-NEXT: mov d17, v16.d[1]
+; CHECK-NEXT: ext v18.16b, v0.16b, v1.16b, #12
+; CHECK-NEXT: ldr q0, [x9, :lo12:.LCPI1_0]
+; CHECK-NEXT: mov d19, v18.d[1]
+; CHECK-NEXT: mov v18.s[0], v4.s[0]
+; CHECK-NEXT: mov v4.s[0], v3.s[1]
+; CHECK-NEXT: xtn v1.4h, v4.4s
+; CHECK-NEXT: tbl v0.16b, { v16.16b, v17.16b, v18.16b, v19.16b }, v0.16b
+; CHECK-NEXT: str s1, [x8, #16]
+; CHECK-NEXT: str q0, [x8]
+; CHECK-NEXT: ret
+ %result = call <10 x i16> @llvm.vector.interleave5.v10i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e)
+ ret <10 x i16> %result
+}
+
+define { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } @deinterleave7_v14i16(<14 x i16> %vec) {
+; CHECK-LABEL: deinterleave7_v14i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s3, w3
+; CHECK-NEXT: fmov s2, w2
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: fmov s1, w1
+; CHECK-NEXT: fmov s6, w6
+; CHECK-NEXT: add x9, sp, #8
+; CHECK-NEXT: fmov s5, w5
+; CHECK-NEXT: fmov s4, w4
+; CHECK-NEXT: add x10, sp, #16
+; CHECK-NEXT: fmov s0, w0
+; CHECK-NEXT: ld1 { v2.h }[2], [x9]
+; CHECK-NEXT: ld1 { v3.h }[2], [x10]
+; CHECK-NEXT: ld1 { v1.h }[2], [x8]
+; CHECK-NEXT: add x8, sp, #24
+; CHECK-NEXT: add x9, sp, #32
+; CHECK-NEXT: add x10, sp, #40
+; CHECK-NEXT: ld1 { v4.h }[2], [x8]
+; CHECK-NEXT: ld1 { v5.h }[2], [x9]
+; CHECK-NEXT: mov v0.s[1], w7
+; CHECK-NEXT: ld1 { v6.h }[2], [x10]
+; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
+; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NEXT: // kill: def $d3 killed $d3 killed $q3
+; CHECK-NEXT: // kill: def $d4 killed $d4 killed $q4
+; CHECK-NEXT: // kill: def $d5 killed $d5 killed $q5
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: // kill: def $d6 killed $d6 killed $q6
+; CHECK-NEXT: ret
+ %result = call { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } @llvm.vector.deinterleave7.v14i16(<14 x i16> %vec)
+ ret { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } %result
+}
+
+define <14 x i16> @interleave7_v14i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e, <2 x i16> %f, <2 x i16> %g) {
+; CHECK-LABEL: interleave7_v14i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d6 killed $d6 killed $q4_q5_q6 def $q4_q5_q6
+; CHECK-NEXT: fmov d7, d5
+; CHECK-NEXT: fmov d16, d4
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d3 killed $d3 def $q3
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: adrp x9, .LCPI3_1
+; CHECK-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: mov v1.d[1], v16.d[0]
+; CHECK-NEXT: mov v16.d[1], v7.d[0]
+; CHECK-NEXT: uzp1 v17.4s, v0.4s, v2.4s
+; CHECK-NEXT: uzp1 v3.4s, v0.4s, v16.4s
+; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s
+; CHECK-NEXT: mov d18, v17.d[1]
+; CHECK-NEXT: ext v19.16b, v3.16b, v0.16b, #8
+; CHECK-NEXT: ext v0.16b, v1.16b, v1.16b, #12
+; CHECK-NEXT: mov v2.16b, v19.16b
+; CHECK-NEXT: mov v2.s[2], v6.s[0]
+; CHECK-NEXT: uzp1 v4.4s, v1.4s, v0.4s
+; CHECK-NEXT: ldr q0, [x9, :lo12:.LCPI3_1]
+; CHECK-NEXT: adrp x9, .LCPI3_0
+; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI3_0]
+; CHECK-NEXT: mov d5, v4.d[1]
+; CHECK-NEXT: mov d20, v2.d[1]
+; CHECK-NEXT: mov v6.s[0], v7.s[1]
+; CHECK-NEXT: tbl v1.16b, { v17.16b, v18.16b, v19.16b, v20.16b }, v1.16b
+; CHECK-NEXT: tbl v0.16b, { v4.16b, v5.16b, v6.16b }, v0.16b
+; CHECK-NEXT: str q1, [x8]
+; CHECK-NEXT: mov s2, v0.s[2]
+; CHECK-NEXT: str d0, [x8, #16]
+; CHECK-NEXT: str s2, [x8, #24]
+; CHECK-NEXT: ret
+ %result = call <14 x i16> @llvm.vector.interleave7.v14i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e, <2 x i16> %f, <2 x i16> %g)
+ ret <14 x i16> %result
+}
diff --git a/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll b/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
index ab06111fb52ff..eb6326e946fb2 100644
--- a/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
+++ b/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
@@ -14,22 +14,12 @@ define <4 x half> @interleave2_v4f16(<2 x half> %vec0, <2 x half> %vec1) {
}
define <8 x half> @interleave2_v8f16(<4 x half> %vec0, <4 x half> %vec1) {
-; CHECK-SD-LABEL: interleave2_v8f16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-SD-NEXT: adrp x8, .LCPI1_0
-; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
-; CHECK-SD-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: interleave2_v8f16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-GI-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: interleave2_v8f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: zip1 v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
%retval = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %vec0, <4 x half> %vec1)
ret <8 x half> %retval
}
@@ -46,21 +36,12 @@ define <16 x half> @interleave2_v16f16(<8 x half> %vec0, <8 x half> %vec1) {
}
define <4 x float> @interleave2_v4f32(<2 x float> %vec0, <2 x float> %vec1) {
-; CHECK-SD-LABEL: interleave2_v4f32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-SD-NEXT: rev64 v1.4s, v0.4s
-; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: interleave2_v4f32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-GI-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: interleave2_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: zip1 v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
%retval = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %vec0, <2 x float> %vec1)
ret <4 x float> %retval
}
@@ -187,11 +168,10 @@ define <4 x i16> @interleave2_diff_nonconst_splat_v4i16(i16 %a, i16 %b) {
; CHECK-SD-LABEL: interleave2_diff_nonconst_splat_v4i16:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fmov s0, w0
-; CHECK-SD-NEXT: mov v0.h[1], w0
-; CHECK-SD-NEXT: mov v0.h[2], w1
+; CHECK-SD-NEXT: mov v0.h[1], w1
+; CHECK-SD-NEXT: mov v0.h[2], w0
; CHECK-SD-NEXT: mov v0.h[3], w1
-; CHECK-SD-NEXT: rev32 v1.4h, v0.4h
-; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v1.4h
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: interleave2_diff_nonconst_splat_v4i16:
diff --git a/llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll b/llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll
index da917119c6b25..d8ff031239b41 100644
--- a/llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll
+++ b/llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll
@@ -5,25 +5,17 @@
define { <16 x i8>, <16 x i8> } @foo_ld2_v16i8(<16 x i1> %mask, ptr %p) {
; CHECK-LABEL: foo_ld2_v16i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: zip2 v1.16b, v0.16b, v0.16b
; CHECK-NEXT: zip1 v0.16b, v0.16b, v0.16b
; CHECK-NEXT: adrp x8, .LCPI0_0
-; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT: shl v1.16b, v1.16b, #7
+; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
; CHECK-NEXT: shl v0.16b, v0.16b, #7
-; CHECK-NEXT: cmlt v1.16b, v1.16b, #0
; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
-; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: addp v1.16b, v1.16b, v1.16b
+; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: addp v0.16b, v0.16b, v0.16b
-; CHECK-NEXT: addp v1.16b, v1.16b, v1.16b
; CHECK-NEXT: addp v0.16b, v0.16b, v0.16b
-; CHECK-NEXT: addp v1.16b, v1.16b, v1.16b
; CHECK-NEXT: addp v0.16b, v0.16b, v0.16b
-; CHECK-NEXT: umov w9, v1.h[0]
; CHECK-NEXT: umov w8, v0.h[0]
-; CHECK-NEXT: bfi w8, w9, #16, #16
+; CHECK-NEXT: bfi w8, w8, #16, #16
; CHECK-NEXT: tbz w8, #0, .LBB0_2
; CHECK-NEXT: // %bb.1: // %cond.load
; CHECK-NEXT: ldr b1, [x0]
@@ -349,10 +341,11 @@ define { <8 x i16>, <8 x i16> } @foo_ld2_v8i16(<8 x i1> %mask, ptr %p) {
define { <4 x float>, <4 x float> } @foo_ld2_v4f32(<4 x i1> %mask, ptr %p) {
; CHECK-LABEL: foo_ld2_v4f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: uzp1 v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: adrp x8, .LCPI2_0
+; CHECK-NEXT: zip1 v0.8h, v0.8h, v0.8h
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI2_0]
-; CHECK-NEXT: zip1 v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: xtn v0.8b, v0.8h
; CHECK-NEXT: shl v0.8b, v0.8b, #7
; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
@@ -419,10 +412,11 @@ define { <4 x float>, <4 x float> } @foo_ld2_v4f32(<4 x i1> %mask, ptr %p) {
define { <2 x double>, <2 x double> } @foo_ld2_v2f64(<2 x i1> %mask, ptr %p) {
; CHECK-LABEL: foo_ld2_v2f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: adrp x8, .LCPI3_0
+; CHECK-NEXT: zip1 v0.4s, v0.4s, v0.4s
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI3_0]
-; CHECK-NEXT: zip1 v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: shl v0.4h, v0.4h, #15
; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
@@ -453,8 +447,8 @@ define { <2 x double>, <2 x double> } @foo_ld2_v2f64(<2 x i1> %mask, ptr %p) {
; CHECK-NEXT: add x8, x0, #24
; CHECK-NEXT: ld1 { v2.d }[1], [x8]
; CHECK-NEXT: .LBB3_8: // %else8
-; CHECK-NEXT: zip1 v0.2d, v1.2d, v2.2d
-; CHECK-NEXT: zip2 v1.2d, v1.2d, v2.2d
+; CHECK-NEXT: uzp1 v0.2d, v1.2d, v2.2d
+; CHECK-NEXT: uzp2 v1.2d, v1.2d, v2.2d
; CHECK-NEXT: ret
%interleaved.mask = call <4 x i1> @llvm.vector.interleave2.v4i1(<2 x i1> %mask, <2 x i1> %mask)
%wide.masked.vec = call <4 x double> @llvm.masked.load.v4f64.p0(ptr %p, i32 8, <4 x i1> %interleaved.mask, <4 x double> poison)
diff --git a/llvm/test/CodeGen/AArch64/fixed_masked_interleaved_stores.ll b/llvm/test/CodeGen/AArch64/fixed_masked_interleaved_stores.ll
index 972be0fca2089..5155be8cfed0d 100644
--- a/llvm/test/CodeGen/AArch64/fixed_masked_interleaved_stores.ll
+++ b/llvm/test/CodeGen/AArch64/fixed_masked_interleaved_stores.ll
@@ -5,26 +5,18 @@
define void @foo_st2_v16i8(<16 x i1> %mask, <16 x i8> %val1, <16 x i8> %val2, ptr %p) {
; CHECK-LABEL: foo_st2_v16i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: zip2 v3.16b, v0.16b, v0.16b
; CHECK-NEXT: zip1 v0.16b, v0.16b, v0.16b
; CHECK-NEXT: adrp x8, .LCPI0_0
-; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT: shl v3.16b, v3.16b, #7
+; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI0_0]
; CHECK-NEXT: shl v0.16b, v0.16b, #7
-; CHECK-NEXT: cmlt v3.16b, v3.16b, #0
; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
-; CHECK-NEXT: and v3.16b, v3.16b, v4.16b
-; CHECK-NEXT: and v0.16b, v0.16b, v4.16b
-; CHECK-NEXT: addp v3.16b, v3.16b, v3.16b
+; CHECK-NEXT: and v0.16b, v0.16b, v3.16b
; CHECK-NEXT: addp v0.16b, v0.16b, v0.16b
-; CHECK-NEXT: addp v3.16b, v3.16b, v3.16b
; CHECK-NEXT: addp v0.16b, v0.16b, v0.16b
-; CHECK-NEXT: addp v3.16b, v3.16b, v3.16b
; CHECK-NEXT: addp v0.16b, v0.16b, v0.16b
-; CHECK-NEXT: umov w9, v3.h[0]
; CHECK-NEXT: umov w8, v0.h[0]
; CHECK-NEXT: zip1 v0.16b, v1.16b, v2.16b
-; CHECK-NEXT: bfi w8, w9, #16, #16
+; CHECK-NEXT: bfi w8, w8, #16, #16
; CHECK-NEXT: tbnz w8, #0, .LBB0_33
; CHECK-NEXT: // %bb.1: // %else
; CHECK-NEXT: tbnz w8, #1, .LBB0_34
@@ -345,10 +337,11 @@ define void @foo_st2_v8i16(<8 x i1> %mask, <8 x i16> %val1, <8 x i16> %val2, ptr
define void @foo_st2_v4i32(<4 x i1> %mask, <4 x i32> %val1, <4 x i32> %val2, ptr %p) {
; CHECK-LABEL: foo_st2_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: uzp1 v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: adrp x8, .LCPI2_0
+; CHECK-NEXT: zip1 v0.8h, v0.8h, v0.8h
; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI2_0]
-; CHECK-NEXT: zip1 v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: xtn v0.8b, v0.8h
; CHECK-NEXT: shl v0.8b, v0.8b, #7
; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
; CHECK-NEXT: and v0.8b, v0.8b, v3.8b
@@ -413,10 +406,11 @@ define void @foo_st2_v4i32(<4 x i1> %mask, <4 x i32> %val1, <4 x i32> %val2, ptr
define void @foo_st2_v2i64(<2 x i1> %mask, <2 x i64> %val1, <2 x i64> %val2, ptr %p) {
; CHECK-LABEL: foo_st2_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: adrp x8, .LCPI3_0
+; CHECK-NEXT: zip1 v0.4s, v0.4s, v0.4s
; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI3_0]
-; CHECK-NEXT: zip1 v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: shl v0.4h, v0.4h, #15
; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
; CHECK-NEXT: and v0.8b, v0.8b, v3.8b
diff --git a/llvm/test/CodeGen/AArch64/interleaved-accesses.ll b/llvm/test/CodeGen/AArch64/interleaved-accesses.ll
index bedce9ec6a86e..5f75d41378361 100644
--- a/llvm/test/CodeGen/AArch64/interleaved-accesses.ll
+++ b/llvm/test/CodeGen/AArch64/interleaved-accesses.ll
@@ -2195,23 +2195,12 @@ define <4 x i1> @load_large_vector_intrinsic(ptr %p) {
}
define void @store_factor2_intrinsic(ptr %ptr, <8 x i8> %v0, <8 x i8> %v1) {
-; NEON-IAENABLED-LABEL: store_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; NEON-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; NEON-IAENABLED-NEXT: st2 { v0.8b, v1.8b }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: store_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; NEON-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; NEON-IADISABLED-NEXT: adrp x8, .LCPI41_0
-; NEON-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; NEON-IADISABLED-NEXT: ldr q1, [x8, :lo12:.LCPI41_0]
-; NEON-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; NEON-IADISABLED-NEXT: str q0, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: store_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; NEON-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; NEON-NEXT: st2 { v0.8b, v1.8b }, [x0]
+; NEON-NEXT: ret
;
; NO_NEON-LABEL: store_factor2_intrinsic:
; NO_NEON: // %bb.0:
@@ -2873,19 +2862,12 @@ define void @store_general_mask_factor4_undefmulti_intrinsic(ptr %ptr, <32 x i32
}
define void @store_ptrvec_factor2_intrinsic(ptr %ptr, <2 x ptr> %v0, <2 x ptr> %v1) {
-; NEON-IAENABLED-LABEL: store_ptrvec_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: store_ptrvec_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: store_ptrvec_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; NO_NEON-LABEL: store_ptrvec_factor2_intrinsic:
; NO_NEON: // %bb.0:
@@ -2942,19 +2924,12 @@ define void @store_ptrvec_factor4_intrinsic(ptr %ptr, <2 x ptr> %v0, <2 x ptr> %
}
define void @store_undef_mask_factor2_intrinsic(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1) {
-; NEON-IAENABLED-LABEL: store_undef_mask_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: store_undef_mask_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: store_undef_mask_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: ret
;
; NO_NEON-LABEL: store_undef_mask_factor2_intrinsic:
; NO_NEON: // %bb.0:
diff --git a/llvm/test/CodeGen/AArch64/nontemporal-load-interleaved.ll b/llvm/test/CodeGen/AArch64/nontemporal-load-interleaved.ll
index 951f356ee1da5..32f43f03b2b16 100644
--- a/llvm/test/CodeGen/AArch64/nontemporal-load-interleaved.ll
+++ b/llvm/test/CodeGen/AArch64/nontemporal-load-interleaved.ll
@@ -2425,39 +2425,19 @@ entry:
}
define void @test_ldnp_interleaved_load2_v2i32_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str d0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str d1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: zip1 v2.2s, v0.2s, v1.2s
-; CHECK-LE-IADISABLED-NEXT: zip2 v0.2s, v0.2s, v1.2s
-; CHECK-LE-IADISABLED-NEXT: str d2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str d0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.2s, v1.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.2s }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.2s }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: str d0, [x1]
+; CHECK-LE-NEXT: str d1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-BE-IADISABLED-NEXT: zip1 v2.2s, v0.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: zip2 v0.2s, v0.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2s }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2s }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.2s, v1.2s }, [x0]
+; CHECK-BE-NEXT: st1 { v0.2s }, [x1]
+; CHECK-BE-NEXT: st1 { v1.2s }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <4 x i32>, ptr %ptr, align 4, !nontemporal !0
%deinterleaved = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %loaded)
@@ -2470,37 +2450,19 @@ entry:
define void @test_ldnp_interleaved_load2_v4i16_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.4h, v1.4h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str d0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str d1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: xtn v1.4h, v0.4s
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v0.8h
-; CHECK-LE-IADISABLED-NEXT: str d1, [x1]
-; CHECK-LE-IADISABLED-NEXT: str d0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.4h, v1.4h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.4h }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.4h }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.4h, v1.4h }, [x0]
+; CHECK-LE-NEXT: str d0, [x1]
+; CHECK-LE-NEXT: str d1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v1.8h, v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v1.4h }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4h }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.4h, v1.4h }, [x0]
+; CHECK-BE-NEXT: st1 { v0.4h }, [x1]
+; CHECK-BE-NEXT: st1 { v1.4h }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <8 x i16>, ptr %ptr, align 2, !nontemporal !0
%deinterleaved = call { <4 x i16>, <4 x i16> } @llvm.vector.deinterleave2.v8i16(<8 x i16> %loaded)
@@ -2513,37 +2475,19 @@ entry:
define void @test_ldnp_interleaved_load2_v8i8_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.8b, v1.8b }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str d0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str d1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: xtn v1.8b, v0.8h
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.16b, v0.16b, v0.16b
-; CHECK-LE-IADISABLED-NEXT: str d1, [x1]
-; CHECK-LE-IADISABLED-NEXT: str d0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.8b, v1.8b }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.8b }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.8b }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.8b, v1.8b }, [x0]
+; CHECK-LE-NEXT: str d0, [x1]
+; CHECK-LE-NEXT: str d1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v1.16b, v0.16b, v0.16b
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.16b, v0.16b, v0.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v1.8b }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.8b }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.8b, v1.8b }, [x0]
+; CHECK-BE-NEXT: st1 { v0.8b }, [x1]
+; CHECK-BE-NEXT: st1 { v1.8b }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <16 x i8>, ptr %ptr, align 1, !nontemporal !0
%deinterleaved = call { <8 x i8>, <8 x i8> } @llvm.vector.deinterleave2.v16i8(<16 x i8> %loaded)
@@ -2556,39 +2500,19 @@ entry:
define void @test_ldnp_interleaved_load2_v2f32_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str d0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str d1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: zip1 v2.2s, v0.2s, v1.2s
-; CHECK-LE-IADISABLED-NEXT: zip2 v0.2s, v0.2s, v1.2s
-; CHECK-LE-IADISABLED-NEXT: str d2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str d0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.2s, v1.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.2s }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.2s }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: str d0, [x1]
+; CHECK-LE-NEXT: str d1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-BE-IADISABLED-NEXT: zip1 v2.2s, v0.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: zip2 v0.2s, v0.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2s }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2s }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.2s, v1.2s }, [x0]
+; CHECK-BE-NEXT: st1 { v0.2s }, [x1]
+; CHECK-BE-NEXT: st1 { v1.2s }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <4 x float>, ptr %ptr, align 4, !nontemporal !0
%deinterleaved = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %loaded)
@@ -2601,37 +2525,19 @@ entry:
define void @test_ldnp_interleaved_load2_v4f16_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.4h, v1.4h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str d0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str d1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v1.8h, v0.8h, v0.8h
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v0.8h
-; CHECK-LE-IADISABLED-NEXT: str d1, [x1]
-; CHECK-LE-IADISABLED-NEXT: str d0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.4h, v1.4h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.4h }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.4h }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.4h, v1.4h }, [x0]
+; CHECK-LE-NEXT: str d0, [x1]
+; CHECK-LE-NEXT: str d1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v1.8h, v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v1.4h }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4h }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.4h, v1.4h }, [x0]
+; CHECK-BE-NEXT: st1 { v0.4h }, [x1]
+; CHECK-BE-NEXT: st1 { v1.4h }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <8 x half>, ptr %ptr, align 2, !nontemporal !0
%deinterleaved = call { <4 x half>, <4 x half> } @llvm.vector.deinterleave2.v8f16(<8 x half> %loaded)
@@ -2644,39 +2550,19 @@ entry:
define void @test_ldnp_interleaved_load2_v2i64_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.2d }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.2d }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; CHECK-BE-NEXT: st1 { v0.2d }, [x1]
+; CHECK-BE-NEXT: st1 { v1.2d }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <4 x i64>, ptr %ptr, align 8, !nontemporal !0
%deinterleaved = call { <2 x i64>, <2 x i64> } @llvm.vector.deinterleave2.v4i64(<4 x i64> %loaded)
@@ -2689,39 +2575,19 @@ entry:
define void @test_ldnp_interleaved_load2_v4i32_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v2.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.4s }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.4s }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.4s }, [x8]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v2.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.4s }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; CHECK-BE-NEXT: st1 { v0.4s }, [x1]
+; CHECK-BE-NEXT: st1 { v1.4s }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <8 x i32>, ptr %ptr, align 4, !nontemporal !0
%deinterleaved = call { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2.v8i32(<8 x i32> %loaded)
@@ -2734,39 +2600,19 @@ entry:
define void @test_ldnp_interleaved_load2_v8i16_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v2.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.8h }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.8h }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.8h }, [x8]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v2.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.8h }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.8h }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; CHECK-BE-NEXT: st1 { v0.8h }, [x1]
+; CHECK-BE-NEXT: st1 { v1.8h }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <16 x i16>, ptr %ptr, align 2, !nontemporal !0
%deinterleaved = call { <8 x i16>, <8 x i16> } @llvm.vector.deinterleave2.v16i16(<16 x i16> %loaded)
@@ -2779,39 +2625,19 @@ entry:
define void @test_ldnp_interleaved_load2_v16i8_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.16b, v1.16b }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v2.16b, v0.16b, v1.16b
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.16b, v0.16b, v1.16b
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.16b, v1.16b }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.16b }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.16b }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.16b, v1.16b }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.16b }, [x8]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v2.16b, v0.16b, v1.16b
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.16b, v0.16b, v1.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.16b }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.16b }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.16b, v1.16b }, [x0]
+; CHECK-BE-NEXT: st1 { v0.16b }, [x1]
+; CHECK-BE-NEXT: st1 { v1.16b }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <32 x i8>, ptr %ptr, align 1, !nontemporal !0
%deinterleaved = call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2.v32i8(<32 x i8> %loaded)
@@ -2824,39 +2650,19 @@ entry:
define void @test_ldnp_interleaved_load2_v2f64_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.2d }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.2d }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; CHECK-BE-NEXT: st1 { v0.2d }, [x1]
+; CHECK-BE-NEXT: st1 { v1.2d }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <4 x double>, ptr %ptr, align 8, !nontemporal !0
%deinterleaved = call { <2 x double>, <2 x double> } @llvm.vector.deinterleave2.v4f64(<4 x double> %loaded)
@@ -2869,39 +2675,19 @@ entry:
define void @test_ldnp_interleaved_load2_v4f32_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v2.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.4s }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.4s }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.4s }, [x8]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v2.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.4s }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; CHECK-BE-NEXT: st1 { v0.4s }, [x1]
+; CHECK-BE-NEXT: st1 { v1.4s }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <8 x float>, ptr %ptr, align 4, !nontemporal !0
%deinterleaved = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %loaded)
@@ -2914,39 +2700,19 @@ entry:
define void @test_ldnp_interleaved_load2_v8f16_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v2.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.8h }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.8h }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.8h }, [x8]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v2.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.8h }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.8h }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; CHECK-BE-NEXT: st1 { v0.8h }, [x1]
+; CHECK-BE-NEXT: st1 { v1.8h }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <16 x half>, ptr %ptr, align 2, !nontemporal !0
%deinterleaved = call { <8 x half>, <8 x half> } @llvm.vector.deinterleave2.v16f16(<16 x half> %loaded)
diff --git a/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved-optsize.ll b/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved-optsize.ll
index ca1f86d83710c..452e2e56c8625 100644
--- a/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved-optsize.ll
+++ b/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved-optsize.ll
@@ -166,39 +166,19 @@ entry:
}
define void @test_stnp_interleaved_store2_v2i32_Os_intrinsic(<2 x i32> %v0, <2 x i32> %v1, ptr %ptr) #0 {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-LE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: str q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.2s, v1.2s
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.2s, v0.2s
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2s, v2.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
-;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.2s, v0.2s
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: ret
+;
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.2s, v1.2s
+; CHECK-BE-NEXT: rev64 v1.2s, v0.2s
+; CHECK-BE-NEXT: st2 { v1.2s, v2.2s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %v0, <2 x i32> %v1)
store <4 x i32> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -207,39 +187,19 @@ entry:
define void @test_stnp_interleaved_store2_v2i32_Oz_intrinsic(<2 x i32> %v0, <2 x i32> %v1, ptr %ptr) #1 {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-LE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: str q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.2s, v1.2s
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.2s, v0.2s
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2s, v2.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
-;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.2s, v0.2s
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: ret
+;
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.2s, v1.2s
+; CHECK-BE-NEXT: rev64 v1.2s, v0.2s
+; CHECK-BE-NEXT: st2 { v1.2s, v2.2s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %v0, <2 x i32> %v1)
store <4 x i32> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -248,37 +208,19 @@ entry:
define void @test_stnp_interleaved_store2_v2i64_Os_intrinsic(<2 x i64> %v0, <2 x i64> %v1, ptr %ptr) #0 {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: stp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2d, v2.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
-;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: ret
+;
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.2d, v2.2d }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %v0, <2 x i64> %v1)
store <4 x i64> %interleave, ptr %ptr, align 8, !nontemporal !0
@@ -287,37 +229,19 @@ entry:
define void @test_stnp_interleaved_store2_v2i64_Oz_intrinsic(<2 x i64> %v0, <2 x i64> %v1, ptr %ptr) #1 {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: stp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2d, v2.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
-;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: ret
+;
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.2d, v2.2d }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %v0, <2 x i64> %v1)
store <4 x i64> %interleave, ptr %ptr, align 8, !nontemporal !0
@@ -328,6 +252,3 @@ entry:
attributes #0 = { optsize }
attributes #1 = { minsize optsize }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK-BE: {{.*}}
-; CHECK-LE: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved.ll b/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved.ll
index 76b77530f2d16..9cbc98fc96814 100644
--- a/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved.ll
+++ b/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved.ll
@@ -2376,40 +2376,19 @@ entry:
}
define void @test_stnp_interleaved_store2_v2i32_intrinsic(<2 x i32> %v0, <2 x i32> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-LE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: stnp d0, d1, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.2s, v1.2s
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.2s, v0.2s
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2s, v2.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.2s, v0.2s
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.2s, v1.2s
+; CHECK-BE-NEXT: rev64 v1.2s, v0.2s
+; CHECK-BE-NEXT: st2 { v1.2s, v2.2s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %v0, <2 x i32> %v1)
store <4 x i32> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -2418,44 +2397,19 @@ entry:
define void @test_stnp_interleaved_store2_v4i16_intrinsic(<4 x i16> %v0, <4 x i16> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.4h, v1.4h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: adrp x8, .LCPI39_0
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: ldr q1, [x8, :lo12:.LCPI39_0]
-; CHECK-LE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: stnp d0, d1, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.4h, v1.4h
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.4h, v0.4h
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.4h, v2.4h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.4h, v1.4h }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.4h, v0.4h
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4h, v1.4h
-; CHECK-BE-IADISABLED-NEXT: adrp x8, .LCPI39_0
-; CHECK-BE-IADISABLED-NEXT: add x8, x8, :lo12:.LCPI39_0
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.16b }, [x8]
-; CHECK-BE-IADISABLED-NEXT: rev16 v0.16b, v0.16b
-; CHECK-BE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.4h, v1.4h
+; CHECK-BE-NEXT: rev64 v1.4h, v0.4h
+; CHECK-BE-NEXT: st2 { v1.4h, v2.4h }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <8 x i16> @llvm.vector.interleave2.v8i16(<4 x i16> %v0, <4 x i16> %v1)
store <8 x i16> %interleave, ptr %ptr, align 2, !nontemporal !0
@@ -2464,43 +2418,19 @@ entry:
define void @test_stnp_interleaved_store2_v8i8_intrinsic(<8 x i8> %v0, <8 x i8> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.8b, v1.8b }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: adrp x8, .LCPI40_0
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: ldr q1, [x8, :lo12:.LCPI40_0]
-; CHECK-LE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: stnp d0, d1, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.8b, v1.8b
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.8b, v0.8b
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.8b, v2.8b }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.8b, v1.8b }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.8b, v0.8b
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.8b, v1.8b
-; CHECK-BE-IADISABLED-NEXT: adrp x8, .LCPI40_0
-; CHECK-BE-IADISABLED-NEXT: add x8, x8, :lo12:.LCPI40_0
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.16b }, [x8]
-; CHECK-BE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.8b, v1.8b
+; CHECK-BE-NEXT: rev64 v1.8b, v0.8b
+; CHECK-BE-NEXT: st2 { v1.8b, v2.8b }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <16 x i8> @llvm.vector.interleave2.v16i8(<8 x i8> %v0, <8 x i8> %v1)
store <16 x i8> %interleave, ptr %ptr, align 1, !nontemporal !0
@@ -2509,40 +2439,19 @@ entry:
define void @test_stnp_interleaved_store2_v2f32_intrinsic(<2 x float> %v0, <2 x float> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-LE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: stnp d0, d1, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.2s, v1.2s
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.2s, v0.2s
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2s, v2.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.2s, v0.2s
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.2s, v1.2s
+; CHECK-BE-NEXT: rev64 v1.2s, v0.2s
+; CHECK-BE-NEXT: st2 { v1.2s, v2.2s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %v0, <2 x float> %v1)
store <4 x float> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -2551,44 +2460,19 @@ entry:
define void @test_stnp_interleaved_store2_v4f16_intrinsic(<4 x half> %v0, <4 x half> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.4h, v1.4h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: adrp x8, .LCPI42_0
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: ldr q1, [x8, :lo12:.LCPI42_0]
-; CHECK-LE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: stnp d0, d1, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.4h, v1.4h
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.4h, v0.4h
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.4h, v2.4h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.4h, v1.4h }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.4h, v0.4h
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4h, v1.4h
-; CHECK-BE-IADISABLED-NEXT: adrp x8, .LCPI42_0
-; CHECK-BE-IADISABLED-NEXT: add x8, x8, :lo12:.LCPI42_0
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.16b }, [x8]
-; CHECK-BE-IADISABLED-NEXT: rev16 v0.16b, v0.16b
-; CHECK-BE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.4h, v1.4h
+; CHECK-BE-NEXT: rev64 v1.4h, v0.4h
+; CHECK-BE-NEXT: st2 { v1.4h, v2.4h }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %v0, <4 x half> %v1)
store <8 x half> %interleave, ptr %ptr, align 2, !nontemporal !0
@@ -2597,37 +2481,19 @@ entry:
define void @test_stnp_interleaved_store2_v2i64_intrinsic(<2 x i64> %v0, <2 x i64> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2d, v2.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.2d, v2.2d }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %v0, <2 x i64> %v1)
store <4 x i64> %interleave, ptr %ptr, align 8, !nontemporal !0
@@ -2636,41 +2502,21 @@ entry:
define void @test_stnp_interleaved_store2_v4i32_intrinsic(<4 x i32> %v0, <4 x i32> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.4s, v1.4s
-; CHECK-BE-IAENABLED-NEXT: rev64 v0.4s, v0.4s
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.4s, v2.4s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.4s }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v1.4s, v1.4s
+; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.4s, v2.4s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %v0, <4 x i32> %v1)
store <8 x i32> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -2679,41 +2525,21 @@ entry:
define void @test_stnp_interleaved_store2_v8i16_intrinsic(<8 x i16> %v0, <8 x i16> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.8h, v1.8h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.8h, v1.8h
-; CHECK-BE-IAENABLED-NEXT: rev64 v0.8h, v0.8h
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.8h, v2.8h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.8h, v1.8h }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.8h }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v1.8h, v1.8h
+; CHECK-BE-NEXT: rev64 v0.8h, v0.8h
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.8h, v2.8h }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %v0, <8 x i16> %v1)
store <16 x i16> %interleave, ptr %ptr, align 2, !nontemporal !0
@@ -2722,41 +2548,21 @@ entry:
define void @test_stnp_interleaved_store2_v16i8_intrinsic(<16 x i8> %v0, <16 x i8> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.16b, v1.16b }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.16b, v0.16b, v1.16b
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.16b, v0.16b, v1.16b
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.16b, v1.16b
-; CHECK-BE-IAENABLED-NEXT: rev64 v0.16b, v0.16b
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.16b, v2.16b }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.16b, v1.16b }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.16b, v1.16b
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.16b, v0.16b
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.16b, v0.16b, v1.16b
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.16b, v0.16b, v1.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.16b }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v1.16b, v1.16b
+; CHECK-BE-NEXT: rev64 v0.16b, v0.16b
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.16b, v2.16b }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8> %v0, <16 x i8> %v1)
store <32 x i8> %interleave, ptr %ptr, align 1, !nontemporal !0
@@ -2765,37 +2571,19 @@ entry:
define void @test_stnp_interleaved_store2_v2f64_intrinsic(<2 x double> %v0, <2 x double> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2d, v2.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.2d, v2.2d }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %v0, <2 x double> %v1)
store <4 x double> %interleave, ptr %ptr, align 8, !nontemporal !0
@@ -2804,41 +2592,21 @@ entry:
define void @test_stnp_interleaved_store2_v4f32_intrinsic(<4 x float> %v0, <4 x float> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.4s, v1.4s
-; CHECK-BE-IAENABLED-NEXT: rev64 v0.4s, v0.4s
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.4s, v2.4s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.4s }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v1.4s, v1.4s
+; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.4s, v2.4s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %v0, <4 x float> %v1)
store <8 x float> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -2847,41 +2615,21 @@ entry:
define void @test_stnp_interleaved_store2_v8f16_intrinsic(<8 x half> %v0, <8 x half> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.8h, v1.8h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.8h, v1.8h
-; CHECK-BE-IAENABLED-NEXT: rev64 v0.8h, v0.8h
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.8h, v2.8h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.8h, v1.8h }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.8h }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v1.8h, v1.8h
+; CHECK-BE-NEXT: rev64 v0.8h, v0.8h
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.8h, v2.8h }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %v0, <8 x half> %v1)
store <16 x half> %interleave, ptr %ptr, align 2, !nontemporal !0
@@ -3503,11 +3251,14 @@ entry:
define void @test_stnp_interleaved_store2_v3i32_non_pow2_elt_count_intrinsic(<3 x i32> %v0, <3 x i32> %v1, ptr %ptr) {
; CHECK-LE-LABEL: test_stnp_interleaved_store2_v3i32_non_pow2_elt_count_intrinsic:
; CHECK-LE: // %bb.0: // %entry
-; CHECK-LE-NEXT: zip1 v2.4s, v0.4s, v1.4s
-; CHECK-LE-NEXT: zip2 v0.4s, v0.4s, v1.4s
-; CHECK-LE-NEXT: mov d3, v2.d[1]
-; CHECK-LE-NEXT: str d0, [x0, #16]
-; CHECK-LE-NEXT: stnp d2, d3, [x0]
+; CHECK-LE-NEXT: zip2 v2.4s, v0.4s, v1.4s
+; CHECK-LE-NEXT: zip1 v0.4s, v0.4s, v1.4s
+; CHECK-LE-NEXT: ext v1.16b, v0.16b, v2.16b, #12
+; CHECK-LE-NEXT: mov v0.s[3], v1.s[0]
+; CHECK-LE-NEXT: mov d2, v0.d[1]
+; CHECK-LE-NEXT: ext v1.16b, v1.16b, v0.16b, #4
+; CHECK-LE-NEXT: stnp d0, d2, [x0]
+; CHECK-LE-NEXT: str d1, [x0, #16]
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: test_stnp_interleaved_store2_v3i32_non_pow2_elt_count_intrinsic:
@@ -3518,6 +3269,9 @@ define void @test_stnp_interleaved_store2_v3i32_non_pow2_elt_count_intrinsic(<3
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: zip2 v2.4s, v0.4s, v1.4s
; CHECK-BE-NEXT: zip1 v0.4s, v0.4s, v1.4s
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v2.16b, #12
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v0.16b, #4
+; CHECK-BE-NEXT: mov v0.s[3], v1.s[0]
; CHECK-BE-NEXT: rev64 v1.4s, v2.4s
; CHECK-BE-NEXT: st1 { v0.4s }, [x0]
; CHECK-BE-NEXT: str d1, [x0, #16]
@@ -3532,54 +3286,48 @@ entry:
define void @test_stnp_interleaved_store2_v2i24_non_pow2_elt_size_intrinsic(<2 x i24> %v0, <2 x i24> %v1, ptr %ptr) {
; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i24_non_pow2_elt_size_intrinsic:
; CHECK-LE: // %bb.0: // %entry
-; CHECK-LE-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-NEXT: mov v2.16b, v0.16b
-; CHECK-LE-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-NEXT: fmov w9, s0
+; CHECK-LE-NEXT: zip2 v2.2s, v0.2s, v1.2s
+; CHECK-LE-NEXT: zip1 v0.2s, v0.2s, v1.2s
+; CHECK-LE-NEXT: fmov w9, s2
+; CHECK-LE-NEXT: mov w8, v2.s[1]
+; CHECK-LE-NEXT: mov w10, v0.s[1]
+; CHECK-LE-NEXT: str h2, [x0, #6]
; CHECK-LE-NEXT: str h0, [x0]
-; CHECK-LE-NEXT: mov w8, v1.s[1]
-; CHECK-LE-NEXT: mov v2.d[1], v1.d[0]
; CHECK-LE-NEXT: lsr w9, w9, #16
-; CHECK-LE-NEXT: strb w9, [x0, #2]
-; CHECK-LE-NEXT: lsr w9, w8, #16
; CHECK-LE-NEXT: sturh w8, [x0, #9]
-; CHECK-LE-NEXT: rev64 v3.4s, v2.4s
-; CHECK-LE-NEXT: strb w9, [x0, #11]
-; CHECK-LE-NEXT: uzp1 v2.4s, v2.4s, v3.4s
-; CHECK-LE-NEXT: mov w10, v2.s[2]
-; CHECK-LE-NEXT: mov w11, v2.s[1]
-; CHECK-LE-NEXT: lsr w8, w10, #16
-; CHECK-LE-NEXT: lsr w9, w11, #16
-; CHECK-LE-NEXT: strh w10, [x0, #6]
-; CHECK-LE-NEXT: sturh w11, [x0, #3]
-; CHECK-LE-NEXT: strb w8, [x0, #8]
-; CHECK-LE-NEXT: strb w9, [x0, #5]
+; CHECK-LE-NEXT: lsr w8, w8, #16
+; CHECK-LE-NEXT: strb w9, [x0, #8]
+; CHECK-LE-NEXT: fmov w9, s0
+; CHECK-LE-NEXT: sturh w10, [x0, #3]
+; CHECK-LE-NEXT: lsr w10, w10, #16
+; CHECK-LE-NEXT: strb w8, [x0, #11]
+; CHECK-LE-NEXT: lsr w8, w9, #16
+; CHECK-LE-NEXT: strb w10, [x0, #5]
+; CHECK-LE-NEXT: strb w8, [x0, #2]
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i24_non_pow2_elt_size_intrinsic:
; CHECK-BE: // %bb.0: // %entry
-; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
; CHECK-BE-NEXT: rev64 v1.2s, v1.2s
-; CHECK-BE-NEXT: mov v2.16b, v0.16b
-; CHECK-BE-NEXT: fmov w9, s0
-; CHECK-BE-NEXT: mov w8, v1.s[1]
+; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
+; CHECK-BE-NEXT: zip2 v2.2s, v0.2s, v1.2s
+; CHECK-BE-NEXT: zip1 v0.2s, v0.2s, v1.2s
+; CHECK-BE-NEXT: fmov w9, s2
+; CHECK-BE-NEXT: mov w8, v2.s[1]
+; CHECK-BE-NEXT: mov w10, v0.s[1]
+; CHECK-BE-NEXT: stur b2, [x0, #8]
; CHECK-BE-NEXT: stur b0, [x0, #2]
-; CHECK-BE-NEXT: mov v2.d[1], v1.d[0]
; CHECK-BE-NEXT: lsr w9, w9, #8
; CHECK-BE-NEXT: strb w8, [x0, #11]
-; CHECK-BE-NEXT: strh w9, [x0]
-; CHECK-BE-NEXT: lsr w9, w8, #8
-; CHECK-BE-NEXT: rev64 v3.4s, v2.4s
-; CHECK-BE-NEXT: sturh w9, [x0, #9]
-; CHECK-BE-NEXT: uzp1 v2.4s, v2.4s, v3.4s
-; CHECK-BE-NEXT: mov w10, v2.s[2]
-; CHECK-BE-NEXT: mov w11, v2.s[1]
-; CHECK-BE-NEXT: lsr w8, w10, #8
-; CHECK-BE-NEXT: lsr w9, w11, #8
-; CHECK-BE-NEXT: strb w10, [x0, #8]
-; CHECK-BE-NEXT: strb w11, [x0, #5]
-; CHECK-BE-NEXT: strh w8, [x0, #6]
-; CHECK-BE-NEXT: sturh w9, [x0, #3]
+; CHECK-BE-NEXT: lsr w8, w8, #8
+; CHECK-BE-NEXT: strh w9, [x0, #6]
+; CHECK-BE-NEXT: fmov w9, s0
+; CHECK-BE-NEXT: strb w10, [x0, #5]
+; CHECK-BE-NEXT: lsr w10, w10, #8
+; CHECK-BE-NEXT: sturh w8, [x0, #9]
+; CHECK-BE-NEXT: lsr w8, w9, #8
+; CHECK-BE-NEXT: sturh w10, [x0, #3]
+; CHECK-BE-NEXT: strh w8, [x0]
; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i24> @llvm.vector.interleave2.v4i24(<2 x i24> %v0, <2 x i24> %v1)
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
index 4300bcf317d12..1a51a03a4f5b3 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
@@ -50,25 +50,13 @@ exit:
define void @hang_when_merging_stores_after_legalisation_intrinsic(ptr %a, <2 x i32> %b) vscale_range(2,2) #0 {
-; CHECK-IAENABLED-LABEL: hang_when_merging_stores_after_legalisation_intrinsic:
-; CHECK-IAENABLED: // %bb.0:
-; CHECK-IAENABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-IAENABLED-NEXT: dup v0.4s, v0.s[0]
-; CHECK-IAENABLED-NEXT: mov v1.16b, v0.16b
-; CHECK-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: hang_when_merging_stores_after_legalisation_intrinsic:
-; CHECK-IADISABLED: // %bb.0:
-; CHECK-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-IADISABLED-NEXT: adrp x8, .LCPI2_0
-; CHECK-IADISABLED-NEXT: add x8, x8, :lo12:.LCPI2_0
-; CHECK-IADISABLED-NEXT: dup v0.4s, v0.s[0]
-; CHECK-IADISABLED-NEXT: ldr z1, [x8]
-; CHECK-IADISABLED-NEXT: mov z0.q, q0
-; CHECK-IADISABLED-NEXT: tbl z0.s, { z0.s }, z1.s
-; CHECK-IADISABLED-NEXT: str z0, [x0]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: hang_when_merging_stores_after_legalisation_intrinsic:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.4s, v0.s[0]
+; CHECK-NEXT: mov v1.16b, v0.16b
+; CHECK-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; CHECK-NEXT: ret
%splat = shufflevector <2 x i32> %b, <2 x i32> poison, <4 x i32> zeroinitializer
%interleaved.vec = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %splat, <4 x i32> %splat)
store <8 x i32> %interleaved.vec, ptr %a, align 4
diff --git a/llvm/test/CodeGen/AArch64/sve-interleaved-accesses.ll b/llvm/test/CodeGen/AArch64/sve-interleaved-accesses.ll
index 30f944e0a050d..db042ba1d2bc2 100644
--- a/llvm/test/CodeGen/AArch64/sve-interleaved-accesses.ll
+++ b/llvm/test/CodeGen/AArch64/sve-interleaved-accesses.ll
@@ -1654,20 +1654,15 @@ define void @deinterleave_nxptr_factor2(ptr %ptr) #2 {
define void @store_factor2_intrinsic(ptr %ptr, <16 x i16> %v0, <16 x i16> %v1) #0 {
; CHECK-LABEL: store_factor2_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.h, vl8
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: adrp x8, .LCPI29_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI29_0
-; CHECK-NEXT: ldr z4, [x8]
-; CHECK-NEXT: splice z1.h, p0, z1.h, z3.h
-; CHECK-NEXT: splice z0.h, p0, z0.h, z2.h
-; CHECK-NEXT: tbl z1.h, { z1.h }, z4.h
-; CHECK-NEXT: tbl z0.h, { z0.h }, z4.h
-; CHECK-NEXT: str z1, [x0, #1, mul vl]
-; CHECK-NEXT: str z0, [x0]
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.h, p0, z5.h, z3.h
+; CHECK-NEXT: splice z4.h, p0, z4.h, z1.h
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: st2h { z4.h, z5.h }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <32 x i16> @llvm.vector.interleave2.v32i16(<16 x i16> %v0, <16 x i16> %v1)
store <32 x i16> %interleaved.vec, ptr %ptr, align 4
@@ -1722,20 +1717,15 @@ define void @store_factor4_intrinsic(ptr %ptr, <4 x i64> %v0, <4 x i64> %v1, <4
define void @store_ptrvec_factor2_intrinsic(ptr %ptr, <4 x ptr> %v0, <4 x ptr> %v1) #0 {
; CHECK-LABEL: store_ptrvec_factor2_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.d, vl2
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: adrp x8, .LCPI32_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI32_0
-; CHECK-NEXT: ldr z4, [x8]
-; CHECK-NEXT: splice z1.d, p0, z1.d, z3.d
-; CHECK-NEXT: splice z0.d, p0, z0.d, z2.d
-; CHECK-NEXT: tbl z1.d, { z1.d }, z4.d
-; CHECK-NEXT: tbl z0.d, { z0.d }, z4.d
-; CHECK-NEXT: str z1, [x0, #1, mul vl]
-; CHECK-NEXT: str z0, [x0]
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.d, p0, z5.d, z3.d
+; CHECK-NEXT: splice z4.d, p0, z4.d, z1.d
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: st2d { z4.d, z5.d }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <8 x ptr> @llvm.vector.interleave2.v8p0(<4 x ptr> %v0, <4 x ptr> %v1)
store <8 x ptr> %interleaved.vec, ptr %ptr, align 4
@@ -1823,22 +1813,15 @@ define void @store_factor2_wide_intrinsic(ptr %ptr, <8 x i64> %v0, <8 x i64> %v1
define void @store_min_not_max_intrinsic(ptr %ptr, <4 x i64> %v0, <4 x i64> %v1) #1 {
; CHECK-LABEL: store_min_not_max_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.d, vl2
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: adrp x8, .LCPI36_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI36_0
-; CHECK-NEXT: ptrue p1.d, vl4
-; CHECK-NEXT: splice z1.d, p0, z1.d, z3.d
-; CHECK-NEXT: splice z0.d, p0, z0.d, z2.d
-; CHECK-NEXT: ld1d { z2.d }, p1/z, [x8]
-; CHECK-NEXT: mov x8, #4 // =0x4
-; CHECK-NEXT: tbl z1.d, { z1.d }, z2.d
-; CHECK-NEXT: tbl z0.d, { z0.d }, z2.d
-; CHECK-NEXT: st1d { z1.d }, p1, [x0, x8, lsl #3]
-; CHECK-NEXT: st1d { z0.d }, p1, [x0]
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.d, p0, z5.d, z3.d
+; CHECK-NEXT: splice z4.d, p0, z4.d, z1.d
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: st2d { z4.d, z5.d }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <8 x i64> @llvm.vector.interleave2.v8i64(<4 x i64> %v0, <4 x i64> %v1)
store <8 x i64> %interleaved.vec, ptr %ptr, align 4
@@ -1848,20 +1831,15 @@ define void @store_min_not_max_intrinsic(ptr %ptr, <4 x i64> %v0, <4 x i64> %v1)
define void @store_min_ge_type_intrinsic(ptr %ptr, <4 x i64> %v0, <4 x i64> %v1) #2 {
; CHECK-LABEL: store_min_ge_type_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.d, vl2
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: adrp x8, .LCPI37_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI37_0
-; CHECK-NEXT: splice z2.d, p0, z2.d, z3.d
-; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.d, p0, z5.d, z3.d
+; CHECK-NEXT: splice z4.d, p0, z4.d, z1.d
; CHECK-NEXT: ptrue p0.d, vl4
-; CHECK-NEXT: ldr z1, [x8]
-; CHECK-NEXT: splice z0.d, p0, z0.d, z2.d
-; CHECK-NEXT: tbl z0.d, { z0.d }, z1.d
-; CHECK-NEXT: str z0, [x0]
+; CHECK-NEXT: st2d { z4.d, z5.d }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <8 x i64> @llvm.vector.interleave2.v8i64(<4 x i64> %v0, <4 x i64> %v1)
store <8 x i64> %interleaved.vec, ptr %ptr, align 4
@@ -1916,20 +1894,15 @@ define void @store_float_factor3_intrinsic(ptr %ptr, <8 x float> %v0, <8 x float
define void @store_half_factor2_intrinsic(ptr %ptr, <16 x half> %v0, <16 x half> %v1) #0 {
; CHECK-LABEL: store_half_factor2_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.h, vl8
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: adrp x8, .LCPI40_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI40_0
-; CHECK-NEXT: ldr z4, [x8]
-; CHECK-NEXT: splice z1.h, p0, z1.h, z3.h
-; CHECK-NEXT: splice z0.h, p0, z0.h, z2.h
-; CHECK-NEXT: tbl z1.h, { z1.h }, z4.h
-; CHECK-NEXT: tbl z0.h, { z0.h }, z4.h
-; CHECK-NEXT: str z1, [x0, #1, mul vl]
-; CHECK-NEXT: str z0, [x0]
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.h, p0, z5.h, z3.h
+; CHECK-NEXT: splice z4.h, p0, z4.h, z1.h
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: st2h { z4.h, z5.h }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <32 x half> @llvm.vector.interleave2.v32f16(<16 x half> %v0, <16 x half> %v1)
store <32 x half> %interleaved.vec, ptr %ptr, align 4
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-interleave.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-interleave.ll
index d87b6b0404874..4f4dac8fe9f65 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-interleave.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-interleave.ll
@@ -9,23 +9,15 @@ define void @store_factor2_64bit(ptr %ptr, <2 x i32> %v0, <2 x i32> %v1) {
; CHECK-COMPAT-LABEL: store_factor2_64bit:
; CHECK-COMPAT: // %bb.0:
; CHECK-COMPAT-NEXT: ptrue p0.s, vl2
-; CHECK-COMPAT-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-COMPAT-NEXT: // kill: def $d1 killed $d1 def $z1
-; CHECK-COMPAT-NEXT: adrp x8, .LCPI0_0
-; CHECK-COMPAT-NEXT: splice z0.s, p0, z0.s, z1.s
-; CHECK-COMPAT-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
-; CHECK-COMPAT-NEXT: tbl z0.s, { z0.s }, z1.s
-; CHECK-COMPAT-NEXT: str q0, [x0]
+; CHECK-COMPAT-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1
+; CHECK-COMPAT-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1
+; CHECK-COMPAT-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-COMPAT-NEXT: ret
;
; CHECK-STREAMING-LABEL: store_factor2_64bit:
; CHECK-STREAMING: // %bb.0:
; CHECK-STREAMING-NEXT: ptrue p0.s, vl2
-; CHECK-STREAMING-NEXT: adrp x8, .LCPI0_0
-; CHECK-STREAMING-NEXT: splice z0.s, p0, { z0.s, z1.s }
-; CHECK-STREAMING-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
-; CHECK-STREAMING-NEXT: tbl z0.s, { z0.s }, z1.s
-; CHECK-STREAMING-NEXT: str q0, [x0]
+; CHECK-STREAMING-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-STREAMING-NEXT: ret
%interleaved = call <4 x i32> @llvm.vector.interleave2.v4i32(
<2 x i32> %v0, <2 x i32> %v1)
@@ -36,30 +28,16 @@ define void @store_factor2_64bit(ptr %ptr, <2 x i32> %v0, <2 x i32> %v1) {
define void @store_factor2_128bit(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1) {
; CHECK-COMPAT-LABEL: store_factor2_128bit:
; CHECK-COMPAT: // %bb.0:
-; CHECK-COMPAT-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-COMPAT-NEXT: // kill: def $q0 killed $q0 def $z0
-; CHECK-COMPAT-NEXT: mov z2.s, z1.s[3]
-; CHECK-COMPAT-NEXT: mov z3.s, z0.s[3]
-; CHECK-COMPAT-NEXT: mov z4.s, z1.s[2]
-; CHECK-COMPAT-NEXT: mov z5.s, z0.s[2]
-; CHECK-COMPAT-NEXT: zip1 z0.s, z0.s, z1.s
-; CHECK-COMPAT-NEXT: zip1 z2.s, z3.s, z2.s
-; CHECK-COMPAT-NEXT: zip1 z3.s, z5.s, z4.s
-; CHECK-COMPAT-NEXT: zip1 z1.d, z3.d, z2.d
-; CHECK-COMPAT-NEXT: stp q0, q1, [x0]
+; CHECK-COMPAT-NEXT: ptrue p0.s, vl4
+; CHECK-COMPAT-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; CHECK-COMPAT-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; CHECK-COMPAT-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-COMPAT-NEXT: ret
;
; CHECK-STREAMING-LABEL: store_factor2_128bit:
; CHECK-STREAMING: // %bb.0:
-; CHECK-STREAMING-NEXT: mov z2.s, z1.s[3]
-; CHECK-STREAMING-NEXT: mov z3.s, z0.s[3]
-; CHECK-STREAMING-NEXT: mov z4.s, z1.s[2]
-; CHECK-STREAMING-NEXT: mov z5.s, z0.s[2]
-; CHECK-STREAMING-NEXT: zip1 z0.s, z0.s, z1.s
-; CHECK-STREAMING-NEXT: zip1 z2.s, z3.s, z2.s
-; CHECK-STREAMING-NEXT: zip1 z3.s, z5.s, z4.s
-; CHECK-STREAMING-NEXT: zip1 z1.d, z3.d, z2.d
-; CHECK-STREAMING-NEXT: stp q0, q1, [x0]
+; CHECK-STREAMING-NEXT: ptrue p0.s, vl4
+; CHECK-STREAMING-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-STREAMING-NEXT: ret
%interleaved = call <8 x i32> @llvm.vector.interleave2.v8i32(
<4 x i32> %v0, <4 x i32> %v1)
@@ -157,40 +135,22 @@ define void @masked_store_factor2_64bit(ptr %ptr, <2 x i32> %v0, <2 x i32> %v1,
; CHECK-COMPAT-LABEL: masked_store_factor2_64bit:
; CHECK-COMPAT: // %bb.0:
; CHECK-COMPAT-NEXT: // kill: def $d2 killed $d2 def $z2
-; CHECK-COMPAT-NEXT: mov z3.s, z2.s[1]
; CHECK-COMPAT-NEXT: ptrue p0.s, vl2
-; CHECK-COMPAT-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-COMPAT-NEXT: // kill: def $d1 killed $d1 def $z1
-; CHECK-COMPAT-NEXT: adrp x8, .LCPI6_0
-; CHECK-COMPAT-NEXT: splice z0.s, p0, z0.s, z1.s
-; CHECK-COMPAT-NEXT: ptrue p0.s, vl4
-; CHECK-COMPAT-NEXT: zip1 z2.h, z2.h, z3.h
-; CHECK-COMPAT-NEXT: zip1 z2.h, z2.h, z2.h
-; CHECK-COMPAT-NEXT: uunpklo z2.s, z2.h
+; CHECK-COMPAT-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1
; CHECK-COMPAT-NEXT: lsl z2.s, z2.s, #31
-; CHECK-COMPAT-NEXT: asr z1.s, z2.s, #31
-; CHECK-COMPAT-NEXT: ldr q2, [x8, :lo12:.LCPI6_0]
-; CHECK-COMPAT-NEXT: tbl z0.s, { z0.s }, z2.s
-; CHECK-COMPAT-NEXT: cmpne p1.s, p0/z, z1.s, #0
-; CHECK-COMPAT-NEXT: st1w { z0.s }, p1, [x0]
+; CHECK-COMPAT-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1
+; CHECK-COMPAT-NEXT: asr z2.s, z2.s, #31
+; CHECK-COMPAT-NEXT: cmpne p1.s, p0/z, z2.s, #0
+; CHECK-COMPAT-NEXT: st2w { z0.s, z1.s }, p1, [x0]
; CHECK-COMPAT-NEXT: ret
;
; CHECK-STREAMING-LABEL: masked_store_factor2_64bit:
; CHECK-STREAMING: // %bb.0:
-; CHECK-STREAMING-NEXT: mov z3.s, z2.s[1]
-; CHECK-STREAMING-NEXT: ptrue p0.s, vl2
-; CHECK-STREAMING-NEXT: adrp x8, .LCPI6_0
-; CHECK-STREAMING-NEXT: splice z0.s, p0, { z0.s, z1.s }
-; CHECK-STREAMING-NEXT: ptrue p0.s, vl4
-; CHECK-STREAMING-NEXT: zip1 z2.h, z2.h, z3.h
-; CHECK-STREAMING-NEXT: zip1 z2.h, z2.h, z2.h
-; CHECK-STREAMING-NEXT: uunpklo z2.s, z2.h
; CHECK-STREAMING-NEXT: lsl z2.s, z2.s, #31
-; CHECK-STREAMING-NEXT: asr z1.s, z2.s, #31
-; CHECK-STREAMING-NEXT: ldr q2, [x8, :lo12:.LCPI6_0]
-; CHECK-STREAMING-NEXT: tbl z0.s, { z0.s }, z2.s
-; CHECK-STREAMING-NEXT: cmpne p1.s, p0/z, z1.s, #0
-; CHECK-STREAMING-NEXT: st1w { z0.s }, p1, [x0]
+; CHECK-STREAMING-NEXT: ptrue p0.s, vl2
+; CHECK-STREAMING-NEXT: asr z2.s, z2.s, #31
+; CHECK-STREAMING-NEXT: cmpne p1.s, p0/z, z2.s, #0
+; CHECK-STREAMING-NEXT: st2w { z0.s, z1.s }, p1, [x0]
; CHECK-STREAMING-NEXT: ret
%interleaved = call <4 x i32> @llvm.vector.interleave2.v4i32(
<2 x i32> %v0, <2 x i32> %v1)
@@ -204,61 +164,25 @@ define void @masked_store_factor2_64bit(ptr %ptr, <2 x i32> %v0, <2 x i32> %v1,
define void @masked_store_factor2_128bit(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i1> %mask) {
; CHECK-COMPAT-LABEL: masked_store_factor2_128bit:
; CHECK-COMPAT: // %bb.0:
-; CHECK-COMPAT-NEXT: adrp x8, .LCPI7_0
; CHECK-COMPAT-NEXT: // kill: def $d2 killed $d2 def $z2
-; CHECK-COMPAT-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-COMPAT-NEXT: // kill: def $q0 killed $q0 def $z0
-; CHECK-COMPAT-NEXT: mov z4.s, z1.s[3]
-; CHECK-COMPAT-NEXT: mov z5.s, z0.s[3]
-; CHECK-COMPAT-NEXT: ldr q3, [x8, :lo12:.LCPI7_0]
-; CHECK-COMPAT-NEXT: mov z6.s, z1.s[2]
-; CHECK-COMPAT-NEXT: mov z7.s, z0.s[2]
; CHECK-COMPAT-NEXT: ptrue p0.s, vl4
-; CHECK-COMPAT-NEXT: zip1 z0.s, z0.s, z1.s
-; CHECK-COMPAT-NEXT: mov x8, #4 // =0x4
-; CHECK-COMPAT-NEXT: tbl z3.h, { z2.h }, z3.h
-; CHECK-COMPAT-NEXT: zip1 z2.h, z2.h, z2.h
-; CHECK-COMPAT-NEXT: zip1 z4.s, z5.s, z4.s
-; CHECK-COMPAT-NEXT: zip1 z5.s, z7.s, z6.s
+; CHECK-COMPAT-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
; CHECK-COMPAT-NEXT: uunpklo z2.s, z2.h
-; CHECK-COMPAT-NEXT: uunpklo z3.s, z3.h
+; CHECK-COMPAT-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
; CHECK-COMPAT-NEXT: lsl z2.s, z2.s, #31
-; CHECK-COMPAT-NEXT: lsl z3.s, z3.s, #31
; CHECK-COMPAT-NEXT: asr z2.s, z2.s, #31
-; CHECK-COMPAT-NEXT: asr z3.s, z3.s, #31
-; CHECK-COMPAT-NEXT: cmpne p2.s, p0/z, z2.s, #0
-; CHECK-COMPAT-NEXT: cmpne p1.s, p0/z, z3.s, #0
-; CHECK-COMPAT-NEXT: zip1 z3.d, z5.d, z4.d
-; CHECK-COMPAT-NEXT: st1w { z3.s }, p1, [x0, x8, lsl #2]
-; CHECK-COMPAT-NEXT: st1w { z0.s }, p2, [x0]
+; CHECK-COMPAT-NEXT: cmpne p1.s, p0/z, z2.s, #0
+; CHECK-COMPAT-NEXT: st2w { z0.s, z1.s }, p1, [x0]
; CHECK-COMPAT-NEXT: ret
;
; CHECK-STREAMING-LABEL: masked_store_factor2_128bit:
; CHECK-STREAMING: // %bb.0:
-; CHECK-STREAMING-NEXT: adrp x8, .LCPI7_0
-; CHECK-STREAMING-NEXT: mov z4.s, z1.s[3]
-; CHECK-STREAMING-NEXT: mov z5.s, z0.s[3]
-; CHECK-STREAMING-NEXT: ldr q3, [x8, :lo12:.LCPI7_0]
-; CHECK-STREAMING-NEXT: mov z6.s, z1.s[2]
-; CHECK-STREAMING-NEXT: mov z7.s, z0.s[2]
-; CHECK-STREAMING-NEXT: ptrue p0.s, vl4
-; CHECK-STREAMING-NEXT: zip1 z0.s, z0.s, z1.s
-; CHECK-STREAMING-NEXT: mov x8, #4 // =0x4
-; CHECK-STREAMING-NEXT: tbl z3.h, { z2.h }, z3.h
-; CHECK-STREAMING-NEXT: zip1 z2.h, z2.h, z2.h
-; CHECK-STREAMING-NEXT: zip1 z4.s, z5.s, z4.s
-; CHECK-STREAMING-NEXT: zip1 z5.s, z7.s, z6.s
; CHECK-STREAMING-NEXT: uunpklo z2.s, z2.h
-; CHECK-STREAMING-NEXT: uunpklo z3.s, z3.h
+; CHECK-STREAMING-NEXT: ptrue p0.s, vl4
; CHECK-STREAMING-NEXT: lsl z2.s, z2.s, #31
-; CHECK-STREAMING-NEXT: lsl z3.s, z3.s, #31
; CHECK-STREAMING-NEXT: asr z2.s, z2.s, #31
-; CHECK-STREAMING-NEXT: asr z3.s, z3.s, #31
-; CHECK-STREAMING-NEXT: cmpne p2.s, p0/z, z2.s, #0
-; CHECK-STREAMING-NEXT: cmpne p1.s, p0/z, z3.s, #0
-; CHECK-STREAMING-NEXT: zip1 z3.d, z5.d, z4.d
-; CHECK-STREAMING-NEXT: st1w { z3.s }, p1, [x0, x8, lsl #2]
-; CHECK-STREAMING-NEXT: st1w { z0.s }, p2, [x0]
+; CHECK-STREAMING-NEXT: cmpne p1.s, p0/z, z2.s, #0
+; CHECK-STREAMING-NEXT: st2w { z0.s, z1.s }, p1, [x0]
; CHECK-STREAMING-NEXT: ret
%interleaved = call <8 x i32> @llvm.vector.interleave2.v8i32(
<4 x i32> %v0, <4 x i32> %v1)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
index 133bac768d59e..70f02aeb91c6f 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
@@ -266,11 +266,9 @@ define void @alloc_v4i8_intrinsic(ptr %st_ptr) nounwind {
; CHECK-NEXT: ptrue p0.h, vl4
; CHECK-NEXT: ld1b { z0.h }, p0/z, [x20]
; CHECK-NEXT: ptrue p0.s, vl2
-; CHECK-NEXT: mov z1.h, z0.h[2]
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: fmov w9, s1
-; CHECK-NEXT: mov z0.s, w8
-; CHECK-NEXT: mov z1.s, w9
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8
; CHECK-NEXT: zip1 z0.s, z0.s, z1.s
; CHECK-NEXT: st1b { z0.s }, p0, [x19]
; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
index 986b776a9a586..3d7e5eec7be63 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
@@ -194,7 +194,9 @@ define void @hang_when_merging_stores_after_legalisation_intrinsic(ptr %a, <2 x
; CHECK-LABEL: hang_when_merging_stores_after_legalisation_intrinsic:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.s, s0
-; CHECK-NEXT: stp q0, q0, [x0]
+; CHECK-NEXT: ptrue p0.s, vl4
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: hang_when_merging_stores_after_legalisation_intrinsic:
@@ -219,15 +221,8 @@ define void @hang_when_merging_stores_after_legalisation_intrinsic(ptr %a, <2 x
define void @interleave_store_without_splat_intrinsic(ptr %a, <4 x i32> %v1, <4 x i32> %v2) {
; CHECK-LABEL: interleave_store_without_splat_intrinsic:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z2.s, z1.s[3]
-; CHECK-NEXT: mov z3.s, z0.s[3]
-; CHECK-NEXT: mov z4.s, z1.s[2]
-; CHECK-NEXT: mov z5.s, z0.s[2]
-; CHECK-NEXT: zip1 z0.s, z0.s, z1.s
-; CHECK-NEXT: zip1 z2.s, z3.s, z2.s
-; CHECK-NEXT: zip1 z3.s, z5.s, z4.s
-; CHECK-NEXT: zip1 z1.d, z3.d, z2.d
-; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ptrue p0.s, vl4
+; CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: interleave_store_without_splat_intrinsic:
diff --git a/llvm/test/CodeGen/AArch64/tbl-loops.ll b/llvm/test/CodeGen/AArch64/tbl-loops.ll
index 4870243e0e4a4..3ad43f71dc2a1 100644
--- a/llvm/test/CodeGen/AArch64/tbl-loops.ll
+++ b/llvm/test/CodeGen/AArch64/tbl-loops.ll
@@ -1064,159 +1064,82 @@ for.body: ; preds = %for.body.preheader5
define void @loop2_intrinsic(ptr noalias nocapture noundef writeonly %dst, ptr nocapture noundef readonly %data, i32 noundef %width) {
-; CHECK-IAENABLED-LABEL: loop2_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: subs w8, w2, #1
-; CHECK-IAENABLED-NEXT: b.lt .LBB4_6
-; CHECK-IAENABLED-NEXT: // %bb.1: // %for.body.preheader
-; CHECK-IAENABLED-NEXT: cmp w8, #2
-; CHECK-IAENABLED-NEXT: b.ls .LBB4_3
-; CHECK-IAENABLED-NEXT: // %bb.2: // %vector.memcheck
-; CHECK-IAENABLED-NEXT: ubfiz x9, x8, #1, #32
-; CHECK-IAENABLED-NEXT: add x9, x9, #2
-; CHECK-IAENABLED-NEXT: add x10, x0, x9
-; CHECK-IAENABLED-NEXT: add x9, x1, x9, lsl #2
-; CHECK-IAENABLED-NEXT: cmp x10, x1
-; CHECK-IAENABLED-NEXT: ccmp x9, x0, #0, hi
-; CHECK-IAENABLED-NEXT: b.ls .LBB4_7
-; CHECK-IAENABLED-NEXT: .LBB4_3:
-; CHECK-IAENABLED-NEXT: mov w10, wzr
-; CHECK-IAENABLED-NEXT: mov x8, x1
-; CHECK-IAENABLED-NEXT: mov x9, x0
-; CHECK-IAENABLED-NEXT: .LBB4_4: // %for.body.preheader1
-; CHECK-IAENABLED-NEXT: movi d0, #0000000000000000
-; CHECK-IAENABLED-NEXT: mov w11, #1132396544 // =0x437f0000
-; CHECK-IAENABLED-NEXT: sub w10, w2, w10
-; CHECK-IAENABLED-NEXT: fmov s1, w11
-; CHECK-IAENABLED-NEXT: .LBB4_5: // %for.body
-; CHECK-IAENABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IAENABLED-NEXT: ldp s2, s3, [x8], #8
-; CHECK-IAENABLED-NEXT: fcmp s2, s1
-; CHECK-IAENABLED-NEXT: fcsel s4, s1, s2, gt
-; CHECK-IAENABLED-NEXT: fcmp s2, #0.0
-; CHECK-IAENABLED-NEXT: fcsel s2, s0, s4, mi
-; CHECK-IAENABLED-NEXT: fcmp s3, s1
-; CHECK-IAENABLED-NEXT: fcsel s4, s1, s3, gt
-; CHECK-IAENABLED-NEXT: fcmp s3, #0.0
-; CHECK-IAENABLED-NEXT: fcvtzs s2, s2
-; CHECK-IAENABLED-NEXT: fcsel s3, s0, s4, mi
-; CHECK-IAENABLED-NEXT: subs w10, w10, #1
-; CHECK-IAENABLED-NEXT: str b2, [x9]
-; CHECK-IAENABLED-NEXT: fcvtzs s3, s3
-; CHECK-IAENABLED-NEXT: stur b3, [x9, #1]
-; CHECK-IAENABLED-NEXT: add x9, x9, #2
-; CHECK-IAENABLED-NEXT: b.ne .LBB4_5
-; CHECK-IAENABLED-NEXT: .LBB4_6: // %for.cond.cleanup
-; CHECK-IAENABLED-NEXT: ret
-; CHECK-IAENABLED-NEXT: .LBB4_7: // %vector.ph
-; CHECK-IAENABLED-NEXT: add x11, x8, #1
-; CHECK-IAENABLED-NEXT: mov w8, #1132396544 // =0x437f0000
-; CHECK-IAENABLED-NEXT: and x10, x11, #0x1fffffffc
-; CHECK-IAENABLED-NEXT: dup v0.4s, w8
-; CHECK-IAENABLED-NEXT: and x12, x11, #0x1fffffffc
-; CHECK-IAENABLED-NEXT: add x8, x1, x10, lsl #3
-; CHECK-IAENABLED-NEXT: add x9, x0, x10, lsl #1
-; CHECK-IAENABLED-NEXT: .LBB4_8: // %vector.body
-; CHECK-IAENABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IAENABLED-NEXT: ld2 { v1.4s, v2.4s }, [x1], #32
-; CHECK-IAENABLED-NEXT: subs x12, x12, #4
-; CHECK-IAENABLED-NEXT: fcmgt v3.4s, v1.4s, v0.4s
-; CHECK-IAENABLED-NEXT: fcmgt v4.4s, v2.4s, v0.4s
-; CHECK-IAENABLED-NEXT: fcmlt v5.4s, v1.4s, #0.0
-; CHECK-IAENABLED-NEXT: bsl v3.16b, v0.16b, v1.16b
-; CHECK-IAENABLED-NEXT: bsl v4.16b, v0.16b, v2.16b
-; CHECK-IAENABLED-NEXT: fcmlt v1.4s, v2.4s, #0.0
-; CHECK-IAENABLED-NEXT: bic v2.16b, v3.16b, v5.16b
-; CHECK-IAENABLED-NEXT: bic v1.16b, v4.16b, v1.16b
-; CHECK-IAENABLED-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-IAENABLED-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-IAENABLED-NEXT: xtn v2.4h, v2.4s
-; CHECK-IAENABLED-NEXT: xtn v1.4h, v1.4s
-; CHECK-IAENABLED-NEXT: trn1 v1.8b, v2.8b, v1.8b
-; CHECK-IAENABLED-NEXT: str d1, [x0], #8
-; CHECK-IAENABLED-NEXT: b.ne .LBB4_8
-; CHECK-IAENABLED-NEXT: // %bb.9: // %middle.block
-; CHECK-IAENABLED-NEXT: cmp x11, x10
-; CHECK-IAENABLED-NEXT: b.ne .LBB4_4
-; CHECK-IAENABLED-NEXT: b .LBB4_6
-;
-; CHECK-IADISABLED-LABEL: loop2_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: subs w8, w2, #1
-; CHECK-IADISABLED-NEXT: b.lt .LBB4_6
-; CHECK-IADISABLED-NEXT: // %bb.1: // %for.body.preheader
-; CHECK-IADISABLED-NEXT: cmp w8, #2
-; CHECK-IADISABLED-NEXT: b.ls .LBB4_3
-; CHECK-IADISABLED-NEXT: // %bb.2: // %vector.memcheck
-; CHECK-IADISABLED-NEXT: ubfiz x9, x8, #1, #32
-; CHECK-IADISABLED-NEXT: add x9, x9, #2
-; CHECK-IADISABLED-NEXT: add x10, x0, x9
-; CHECK-IADISABLED-NEXT: add x9, x1, x9, lsl #2
-; CHECK-IADISABLED-NEXT: cmp x10, x1
-; CHECK-IADISABLED-NEXT: ccmp x9, x0, #0, hi
-; CHECK-IADISABLED-NEXT: b.ls .LBB4_7
-; CHECK-IADISABLED-NEXT: .LBB4_3:
-; CHECK-IADISABLED-NEXT: mov w10, wzr
-; CHECK-IADISABLED-NEXT: mov x8, x1
-; CHECK-IADISABLED-NEXT: mov x9, x0
-; CHECK-IADISABLED-NEXT: .LBB4_4: // %for.body.preheader1
-; CHECK-IADISABLED-NEXT: movi d0, #0000000000000000
-; CHECK-IADISABLED-NEXT: mov w11, #1132396544 // =0x437f0000
-; CHECK-IADISABLED-NEXT: sub w10, w2, w10
-; CHECK-IADISABLED-NEXT: fmov s1, w11
-; CHECK-IADISABLED-NEXT: .LBB4_5: // %for.body
-; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ldp s2, s3, [x8], #8
-; CHECK-IADISABLED-NEXT: fcmp s2, s1
-; CHECK-IADISABLED-NEXT: fcsel s4, s1, s2, gt
-; CHECK-IADISABLED-NEXT: fcmp s2, #0.0
-; CHECK-IADISABLED-NEXT: fcsel s2, s0, s4, mi
-; CHECK-IADISABLED-NEXT: fcmp s3, s1
-; CHECK-IADISABLED-NEXT: fcsel s4, s1, s3, gt
-; CHECK-IADISABLED-NEXT: fcmp s3, #0.0
-; CHECK-IADISABLED-NEXT: fcvtzs s2, s2
-; CHECK-IADISABLED-NEXT: fcsel s3, s0, s4, mi
-; CHECK-IADISABLED-NEXT: subs w10, w10, #1
-; CHECK-IADISABLED-NEXT: str b2, [x9]
-; CHECK-IADISABLED-NEXT: fcvtzs s3, s3
-; CHECK-IADISABLED-NEXT: stur b3, [x9, #1]
-; CHECK-IADISABLED-NEXT: add x9, x9, #2
-; CHECK-IADISABLED-NEXT: b.ne .LBB4_5
-; CHECK-IADISABLED-NEXT: .LBB4_6: // %for.cond.cleanup
-; CHECK-IADISABLED-NEXT: ret
-; CHECK-IADISABLED-NEXT: .LBB4_7: // %vector.ph
-; CHECK-IADISABLED-NEXT: add x11, x8, #1
-; CHECK-IADISABLED-NEXT: mov w8, #1132396544 // =0x437f0000
-; CHECK-IADISABLED-NEXT: and x10, x11, #0x1fffffffc
-; CHECK-IADISABLED-NEXT: dup v0.4s, w8
-; CHECK-IADISABLED-NEXT: and x12, x11, #0x1fffffffc
-; CHECK-IADISABLED-NEXT: add x8, x1, x10, lsl #3
-; CHECK-IADISABLED-NEXT: add x9, x0, x10, lsl #1
-; CHECK-IADISABLED-NEXT: .LBB4_8: // %vector.body
-; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ldp q2, q1, [x1], #32
-; CHECK-IADISABLED-NEXT: subs x12, x12, #4
-; CHECK-IADISABLED-NEXT: uzp1 v3.4s, v2.4s, v1.4s
-; CHECK-IADISABLED-NEXT: uzp2 v1.4s, v2.4s, v1.4s
-; CHECK-IADISABLED-NEXT: fcmgt v2.4s, v3.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fcmgt v4.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: bsl v2.16b, v0.16b, v3.16b
-; CHECK-IADISABLED-NEXT: fcmlt v3.4s, v3.4s, #0.0
-; CHECK-IADISABLED-NEXT: bsl v4.16b, v0.16b, v1.16b
-; CHECK-IADISABLED-NEXT: fcmlt v1.4s, v1.4s, #0.0
-; CHECK-IADISABLED-NEXT: bic v2.16b, v2.16b, v3.16b
-; CHECK-IADISABLED-NEXT: bic v1.16b, v4.16b, v1.16b
-; CHECK-IADISABLED-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-IADISABLED-NEXT: xtn v2.4h, v2.4s
-; CHECK-IADISABLED-NEXT: xtn v1.4h, v1.4s
-; CHECK-IADISABLED-NEXT: trn1 v1.8b, v2.8b, v1.8b
-; CHECK-IADISABLED-NEXT: str d1, [x0], #8
-; CHECK-IADISABLED-NEXT: b.ne .LBB4_8
-; CHECK-IADISABLED-NEXT: // %bb.9: // %middle.block
-; CHECK-IADISABLED-NEXT: cmp x11, x10
-; CHECK-IADISABLED-NEXT: b.ne .LBB4_4
-; CHECK-IADISABLED-NEXT: b .LBB4_6
+; CHECK-LABEL: loop2_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: subs w8, w2, #1
+; CHECK-NEXT: b.lt .LBB4_6
+; CHECK-NEXT: // %bb.1: // %for.body.preheader
+; CHECK-NEXT: cmp w8, #2
+; CHECK-NEXT: b.ls .LBB4_3
+; CHECK-NEXT: // %bb.2: // %vector.memcheck
+; CHECK-NEXT: ubfiz x9, x8, #1, #32
+; CHECK-NEXT: add x9, x9, #2
+; CHECK-NEXT: add x10, x0, x9
+; CHECK-NEXT: add x9, x1, x9, lsl #2
+; CHECK-NEXT: cmp x10, x1
+; CHECK-NEXT: ccmp x9, x0, #0, hi
+; CHECK-NEXT: b.ls .LBB4_7
+; CHECK-NEXT: .LBB4_3:
+; CHECK-NEXT: mov w10, wzr
+; CHECK-NEXT: mov x8, x1
+; CHECK-NEXT: mov x9, x0
+; CHECK-NEXT: .LBB4_4: // %for.body.preheader1
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: mov w11, #1132396544 // =0x437f0000
+; CHECK-NEXT: sub w10, w2, w10
+; CHECK-NEXT: fmov s1, w11
+; CHECK-NEXT: .LBB4_5: // %for.body
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ldp s2, s3, [x8], #8
+; CHECK-NEXT: fcmp s2, s1
+; CHECK-NEXT: fcsel s4, s1, s2, gt
+; CHECK-NEXT: fcmp s2, #0.0
+; CHECK-NEXT: fcsel s2, s0, s4, mi
+; CHECK-NEXT: fcmp s3, s1
+; CHECK-NEXT: fcsel s4, s1, s3, gt
+; CHECK-NEXT: fcmp s3, #0.0
+; CHECK-NEXT: fcvtzs s2, s2
+; CHECK-NEXT: fcsel s3, s0, s4, mi
+; CHECK-NEXT: subs w10, w10, #1
+; CHECK-NEXT: str b2, [x9]
+; CHECK-NEXT: fcvtzs s3, s3
+; CHECK-NEXT: stur b3, [x9, #1]
+; CHECK-NEXT: add x9, x9, #2
+; CHECK-NEXT: b.ne .LBB4_5
+; CHECK-NEXT: .LBB4_6: // %for.cond.cleanup
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB4_7: // %vector.ph
+; CHECK-NEXT: add x11, x8, #1
+; CHECK-NEXT: mov w8, #1132396544 // =0x437f0000
+; CHECK-NEXT: and x10, x11, #0x1fffffffc
+; CHECK-NEXT: dup v0.4s, w8
+; CHECK-NEXT: and x12, x11, #0x1fffffffc
+; CHECK-NEXT: add x8, x1, x10, lsl #3
+; CHECK-NEXT: add x9, x0, x10, lsl #1
+; CHECK-NEXT: .LBB4_8: // %vector.body
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ld2 { v1.4s, v2.4s }, [x1], #32
+; CHECK-NEXT: subs x12, x12, #4
+; CHECK-NEXT: fcmgt v3.4s, v1.4s, v0.4s
+; CHECK-NEXT: fcmgt v4.4s, v2.4s, v0.4s
+; CHECK-NEXT: fcmlt v5.4s, v1.4s, #0.0
+; CHECK-NEXT: bsl v3.16b, v0.16b, v1.16b
+; CHECK-NEXT: bsl v4.16b, v0.16b, v2.16b
+; CHECK-NEXT: fcmlt v1.4s, v2.4s, #0.0
+; CHECK-NEXT: bic v2.16b, v3.16b, v5.16b
+; CHECK-NEXT: bic v1.16b, v4.16b, v1.16b
+; CHECK-NEXT: fcvtzs v2.4s, v2.4s
+; CHECK-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-NEXT: xtn v2.4h, v2.4s
+; CHECK-NEXT: xtn v1.4h, v1.4s
+; CHECK-NEXT: zip1 v1.8h, v2.8h, v1.8h
+; CHECK-NEXT: xtn v1.8b, v1.8h
+; CHECK-NEXT: str d1, [x0], #8
+; CHECK-NEXT: b.ne .LBB4_8
+; CHECK-NEXT: // %bb.9: // %middle.block
+; CHECK-NEXT: cmp x11, x10
+; CHECK-NEXT: b.ne .LBB4_4
+; CHECK-NEXT: b .LBB4_6
entry:
%cmp19 = icmp sgt i32 %width, 0
br i1 %cmp19, label %for.body.preheader, label %for.cond.cleanup
diff --git a/llvm/test/CodeGen/AArch64/vector-deinterleave-load.ll b/llvm/test/CodeGen/AArch64/vector-deinterleave-load.ll
index b63448c643074..9d884c150f956 100644
--- a/llvm/test/CodeGen/AArch64/vector-deinterleave-load.ll
+++ b/llvm/test/CodeGen/AArch64/vector-deinterleave-load.ll
@@ -1,33 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IAENABLED
-; RUN: llc -mtriple=aarch64-linux-gnu -lower-interleaved-accesses=false < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IADISABLED
+; RUN: llc -mtriple=aarch64-linux-gnu -lower-interleaved-accesses=false < %s | FileCheck %s
define void @aarch64_vector_deinterleave_idx_ld2(ptr %ptr, i64 %idx) {
-; CHECK-IAENABLED-LABEL: aarch64_vector_deinterleave_idx_ld2:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: lsl x8, x1, #2
-; CHECK-IAENABLED-NEXT: and x9, x8, #0xfffffffffffffff0
-; CHECK-IAENABLED-NEXT: add x8, x8, #16
-; CHECK-IAENABLED-NEXT: add x10, x0, x9
-; CHECK-IAENABLED-NEXT: and x8, x8, #0xfffffffffffffff0
-; CHECK-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x10]
-; CHECK-IAENABLED-NEXT: str q0, [x0, x9]
-; CHECK-IAENABLED-NEXT: str q1, [x0, x8]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: aarch64_vector_deinterleave_idx_ld2:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: lsl x8, x1, #2
-; CHECK-IADISABLED-NEXT: and x9, x8, #0xfffffffffffffff0
-; CHECK-IADISABLED-NEXT: add x8, x8, #16
-; CHECK-IADISABLED-NEXT: add x9, x0, x9
-; CHECK-IADISABLED-NEXT: and x8, x8, #0xfffffffffffffff0
-; CHECK-IADISABLED-NEXT: ldp q1, q0, [x9]
-; CHECK-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: str q2, [x9]
-; CHECK-IADISABLED-NEXT: str q0, [x0, x8]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: aarch64_vector_deinterleave_idx_ld2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: lsl x8, x1, #2
+; CHECK-NEXT: and x9, x8, #0xfffffffffffffff0
+; CHECK-NEXT: add x8, x8, #16
+; CHECK-NEXT: add x10, x0, x9
+; CHECK-NEXT: and x8, x8, #0xfffffffffffffff0
+; CHECK-NEXT: ld2 { v0.4s, v1.4s }, [x10]
+; CHECK-NEXT: str q0, [x0, x9]
+; CHECK-NEXT: str q1, [x0, x8]
+; CHECK-NEXT: ret
entry:
%idx1 = lshr i64 %idx, 2
%a1 = add i64 %idx, 4
diff --git a/llvm/test/CodeGen/AArch64/vector-interleave-store.ll b/llvm/test/CodeGen/AArch64/vector-interleave-store.ll
index d3985991af531..10eee0fcf3ba7 100644
--- a/llvm/test/CodeGen/AArch64/vector-interleave-store.ll
+++ b/llvm/test/CodeGen/AArch64/vector-interleave-store.ll
@@ -1,24 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IAENABLED
-; RUN: llc -mtriple=aarch64-linux-gnu -lower-interleaved-accesses=false < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IADISABLED
+; RUN: llc -mtriple=aarch64-linux-gnu -lower-interleaved-accesses=false < %s | FileCheck %s
+
define void @aarch64_vector_interleave_idx_st2(ptr %ptr, i64 %idx, <4 x float> %v0, <4 x float> %v1) {
-; CHECK-IAENABLED-LABEL: aarch64_vector_interleave_idx_st2:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: lsr x8, x1, #2
-; CHECK-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-IAENABLED-NEXT: add x8, x0, x8, lsl #4
-; CHECK-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x8]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: aarch64_vector_interleave_idx_st2:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: lsr x8, x1, #2
-; CHECK-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: add x8, x0, x8, lsl #4
-; CHECK-IADISABLED-NEXT: stp q0, q2, [x8]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: aarch64_vector_interleave_idx_st2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: lsr x8, x1, #2
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: add x8, x0, x8, lsl #4
+; CHECK-NEXT: st2 { v0.4s, v1.4s }, [x8]
+; CHECK-NEXT: ret
entry:
%idx1 = lshr i64 %idx, 2
%gep1 = getelementptr inbounds <4 x float>, ptr %ptr, i64 %idx1
diff --git a/llvm/test/CodeGen/AArch64/vldn_shuffle.ll b/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
index 963c28aeba32b..fac725dd74999 100644
--- a/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
@@ -1075,12 +1075,10 @@ define void @vld2_intrinsic(ptr nocapture readonly %pSrc, ptr noalias nocapture
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: .LBB17_1: // %vector.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldp q1, q0, [x0], #32
-; CHECK-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; CHECK-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: fmul v1.4s, v2.4s, v2.4s
-; CHECK-NEXT: fmla v1.4s, v0.4s, v0.4s
-; CHECK-NEXT: str q1, [x1, x8]
+; CHECK-NEXT: ld2 { v0.4s, v1.4s }, [x0], #32
+; CHECK-NEXT: fmul v2.4s, v0.4s, v0.4s
+; CHECK-NEXT: fmla v2.4s, v1.4s, v1.4s
+; CHECK-NEXT: str q2, [x1, x8]
; CHECK-NEXT: add x8, x8, #16
; CHECK-NEXT: cmp x8, #1, lsl #12 // =4096
; CHECK-NEXT: b.ne .LBB17_1
@@ -1161,47 +1159,25 @@ while.end: ; preds = %vector.body
define void @vld4_intrinsic(ptr nocapture readonly %pSrc, ptr noalias nocapture %pDst, i32 %numSamples) {
-; CHECK-IAENABLED-LABEL: vld4_intrinsic:
-; CHECK-IAENABLED: .Lfunc_begin19:
-; CHECK-IAENABLED-NEXT: .cfi_startproc
-; CHECK-IAENABLED-NEXT: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: mov x8, xzr
-; CHECK-IAENABLED-NEXT: .LBB19_1: // %vector.body
-; CHECK-IAENABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IAENABLED-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
-; CHECK-IAENABLED-NEXT: add x9, x1, x8
-; CHECK-IAENABLED-NEXT: add x8, x8, #32
-; CHECK-IAENABLED-NEXT: cmp x8, #2, lsl #12 // =8192
-; CHECK-IAENABLED-NEXT: fmul v4.4s, v0.4s, v0.4s
-; CHECK-IAENABLED-NEXT: fmla v4.4s, v1.4s, v1.4s
-; CHECK-IAENABLED-NEXT: fmul v5.4s, v2.4s, v2.4s
-; CHECK-IAENABLED-NEXT: fmla v5.4s, v3.4s, v3.4s
-; CHECK-IAENABLED-NEXT: st2 { v4.4s, v5.4s }, [x9]
-; CHECK-IAENABLED-NEXT: b.ne .LBB19_1
-; CHECK-IAENABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: vld4_intrinsic:
-; CHECK-IADISABLED: .Lfunc_begin19:
-; CHECK-IADISABLED-NEXT: .cfi_startproc
-; CHECK-IADISABLED-NEXT: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: mov x8, xzr
-; CHECK-IADISABLED-NEXT: .LBB19_1: // %vector.body
-; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
-; CHECK-IADISABLED-NEXT: add x9, x1, x8
-; CHECK-IADISABLED-NEXT: add x8, x8, #32
-; CHECK-IADISABLED-NEXT: cmp x8, #2, lsl #12 // =8192
-; CHECK-IADISABLED-NEXT: fmul v4.4s, v0.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fmul v5.4s, v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmla v4.4s, v1.4s, v1.4s
-; CHECK-IADISABLED-NEXT: fmla v5.4s, v3.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip2 v0.4s, v4.4s, v5.4s
-; CHECK-IADISABLED-NEXT: zip1 v1.4s, v4.4s, v5.4s
-; CHECK-IADISABLED-NEXT: stp q1, q0, [x9]
-; CHECK-IADISABLED-NEXT: b.ne .LBB19_1
-; CHECK-IADISABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: vld4_intrinsic:
+; CHECK: .Lfunc_begin19:
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: mov x8, xzr
+; CHECK-NEXT: .LBB19_1: // %vector.body
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
+; CHECK-NEXT: add x9, x1, x8
+; CHECK-NEXT: add x8, x8, #32
+; CHECK-NEXT: cmp x8, #2, lsl #12 // =8192
+; CHECK-NEXT: fmul v4.4s, v0.4s, v0.4s
+; CHECK-NEXT: fmla v4.4s, v1.4s, v1.4s
+; CHECK-NEXT: fmul v5.4s, v2.4s, v2.4s
+; CHECK-NEXT: fmla v5.4s, v3.4s, v3.4s
+; CHECK-NEXT: st2 { v4.4s, v5.4s }, [x9]
+; CHECK-NEXT: b.ne .LBB19_1
+; CHECK-NEXT: // %bb.2: // %while.end
+; CHECK-NEXT: ret
entry:
br label %vector.body
@@ -1248,16 +1224,12 @@ define void @twosrc_intrinsic(ptr nocapture readonly %pSrc, ptr nocapture readon
; CHECK-NEXT: add x9, x0, x8
; CHECK-NEXT: add x10, x1, x8
; CHECK-NEXT: add x8, x8, #32
-; CHECK-NEXT: ldp q1, q0, [x9]
+; CHECK-NEXT: ld2 { v0.4s, v1.4s }, [x9]
; CHECK-NEXT: cmp x8, #2, lsl #12 // =8192
-; CHECK-NEXT: ldp q3, q2, [x10]
-; CHECK-NEXT: uzp1 v4.4s, v1.4s, v0.4s
-; CHECK-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: uzp1 v5.4s, v3.4s, v2.4s
-; CHECK-NEXT: uzp2 v1.4s, v3.4s, v2.4s
-; CHECK-NEXT: fmul v2.4s, v5.4s, v4.4s
-; CHECK-NEXT: fmla v2.4s, v0.4s, v1.4s
-; CHECK-NEXT: str q2, [x2], #16
+; CHECK-NEXT: ld2 { v2.4s, v3.4s }, [x10]
+; CHECK-NEXT: fmul v4.4s, v2.4s, v0.4s
+; CHECK-NEXT: fmla v4.4s, v1.4s, v3.4s
+; CHECK-NEXT: str q4, [x2], #16
; CHECK-NEXT: b.ne .LBB20_1
; CHECK-NEXT: // %bb.2: // %while.end
; CHECK-NEXT: ret
@@ -1295,41 +1267,22 @@ while.end: ; preds = %vector.body
define void @vld2_multiuse_intrinsic(ptr nocapture readonly %pSrc, ptr noalias nocapture %pDst, i32 %numSamples) {
-; CHECK-IAENABLED-LABEL: vld2_multiuse_intrinsic:
-; CHECK-IAENABLED: .Lfunc_begin21:
-; CHECK-IAENABLED-NEXT: .cfi_startproc
-; CHECK-IAENABLED-NEXT: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: mov x8, xzr
-; CHECK-IAENABLED-NEXT: .LBB21_1: // %vector.body
-; CHECK-IAENABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0], #32
-; CHECK-IAENABLED-NEXT: fmul v2.4s, v0.4s, v0.4s
-; CHECK-IAENABLED-NEXT: fmla v2.4s, v1.4s, v1.4s
-; CHECK-IAENABLED-NEXT: str q2, [x1, x8]
-; CHECK-IAENABLED-NEXT: add x8, x8, #16
-; CHECK-IAENABLED-NEXT: cmp x8, #1, lsl #12 // =4096
-; CHECK-IAENABLED-NEXT: b.ne .LBB21_1
-; CHECK-IAENABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: vld2_multiuse_intrinsic:
-; CHECK-IADISABLED: .Lfunc_begin21:
-; CHECK-IADISABLED-NEXT: .cfi_startproc
-; CHECK-IADISABLED-NEXT: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: mov x8, xzr
-; CHECK-IADISABLED-NEXT: .LBB21_1: // %vector.body
-; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ldp q1, q0, [x0], #32
-; CHECK-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fmul v1.4s, v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmla v1.4s, v0.4s, v0.4s
-; CHECK-IADISABLED-NEXT: str q1, [x1, x8]
-; CHECK-IADISABLED-NEXT: add x8, x8, #16
-; CHECK-IADISABLED-NEXT: cmp x8, #1, lsl #12 // =4096
-; CHECK-IADISABLED-NEXT: b.ne .LBB21_1
-; CHECK-IADISABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: vld2_multiuse_intrinsic:
+; CHECK: .Lfunc_begin21:
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: mov x8, xzr
+; CHECK-NEXT: .LBB21_1: // %vector.body
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ld2 { v0.4s, v1.4s }, [x0], #32
+; CHECK-NEXT: fmul v2.4s, v0.4s, v0.4s
+; CHECK-NEXT: fmla v2.4s, v1.4s, v1.4s
+; CHECK-NEXT: str q2, [x1, x8]
+; CHECK-NEXT: add x8, x8, #16
+; CHECK-NEXT: cmp x8, #1, lsl #12 // =4096
+; CHECK-NEXT: b.ne .LBB21_1
+; CHECK-NEXT: // %bb.2: // %while.end
+; CHECK-NEXT: ret
entry:
br label %vector.body
@@ -1402,47 +1355,25 @@ while.end: ; preds = %vector.body
define void @vld4_multiuse_intrinsic(ptr nocapture readonly %pSrc, ptr noalias nocapture %pDst, i32 %numSamples) {
-; CHECK-IAENABLED-LABEL: vld4_multiuse_intrinsic:
-; CHECK-IAENABLED: .Lfunc_begin23:
-; CHECK-IAENABLED-NEXT: .cfi_startproc
-; CHECK-IAENABLED-NEXT: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: mov x8, xzr
-; CHECK-IAENABLED-NEXT: .LBB23_1: // %vector.body
-; CHECK-IAENABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IAENABLED-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
-; CHECK-IAENABLED-NEXT: add x9, x1, x8
-; CHECK-IAENABLED-NEXT: add x8, x8, #32
-; CHECK-IAENABLED-NEXT: cmp x8, #2, lsl #12 // =8192
-; CHECK-IAENABLED-NEXT: fmul v4.4s, v0.4s, v0.4s
-; CHECK-IAENABLED-NEXT: fmla v4.4s, v1.4s, v1.4s
-; CHECK-IAENABLED-NEXT: fmul v5.4s, v2.4s, v2.4s
-; CHECK-IAENABLED-NEXT: fmla v5.4s, v3.4s, v3.4s
-; CHECK-IAENABLED-NEXT: st2 { v4.4s, v5.4s }, [x9]
-; CHECK-IAENABLED-NEXT: b.ne .LBB23_1
-; CHECK-IAENABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: vld4_multiuse_intrinsic:
-; CHECK-IADISABLED: .Lfunc_begin23:
-; CHECK-IADISABLED-NEXT: .cfi_startproc
-; CHECK-IADISABLED-NEXT: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: mov x8, xzr
-; CHECK-IADISABLED-NEXT: .LBB23_1: // %vector.body
-; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
-; CHECK-IADISABLED-NEXT: add x9, x1, x8
-; CHECK-IADISABLED-NEXT: add x8, x8, #32
-; CHECK-IADISABLED-NEXT: cmp x8, #2, lsl #12 // =8192
-; CHECK-IADISABLED-NEXT: fmul v4.4s, v0.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fmul v5.4s, v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmla v4.4s, v1.4s, v1.4s
-; CHECK-IADISABLED-NEXT: fmla v5.4s, v3.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip2 v0.4s, v4.4s, v5.4s
-; CHECK-IADISABLED-NEXT: zip1 v1.4s, v4.4s, v5.4s
-; CHECK-IADISABLED-NEXT: stp q1, q0, [x9]
-; CHECK-IADISABLED-NEXT: b.ne .LBB23_1
-; CHECK-IADISABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: vld4_multiuse_intrinsic:
+; CHECK: .Lfunc_begin23:
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: mov x8, xzr
+; CHECK-NEXT: .LBB23_1: // %vector.body
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
+; CHECK-NEXT: add x9, x1, x8
+; CHECK-NEXT: add x8, x8, #32
+; CHECK-NEXT: cmp x8, #2, lsl #12 // =8192
+; CHECK-NEXT: fmul v4.4s, v0.4s, v0.4s
+; CHECK-NEXT: fmla v4.4s, v1.4s, v1.4s
+; CHECK-NEXT: fmul v5.4s, v2.4s, v2.4s
+; CHECK-NEXT: fmla v5.4s, v3.4s, v3.4s
+; CHECK-NEXT: st2 { v4.4s, v5.4s }, [x9]
+; CHECK-NEXT: b.ne .LBB23_1
+; CHECK-NEXT: // %bb.2: // %while.end
+; CHECK-NEXT: ret
entry:
br label %vector.body
@@ -1534,18 +1465,18 @@ define void @transpose_s16_8x8_simpler2_intrinsic(ptr nocapture noundef %a) {
; CHECK-NEXT: .cfi_startproc
; CHECK-NEXT: // %bb.0: // %entry
; CHECK-NEXT: ldp q0, q1, [x0]
-; CHECK-NEXT: ldp q2, q3, [x0, #64]
-; CHECK-NEXT: ldp q4, q5, [x0, #96]
+; CHECK-NEXT: ldp q2, q3, [x0, #32]
+; CHECK-NEXT: ldp q4, q5, [x0, #64]
+; CHECK-NEXT: ldp q6, q7, [x0, #96]
; CHECK-NEXT: trn1 v0.8h, v0.8h, v1.8h
; CHECK-NEXT: zip1 v1.8h, v2.8h, v3.8h
-; CHECK-NEXT: trn1 v2.8h, v4.8h, v5.8h
-; CHECK-NEXT: ldp q3, q4, [x0, #32]
-; CHECK-NEXT: zip1 v3.8h, v3.8h, v4.8h
-; CHECK-NEXT: dup v1.4s, v1.s[0]
-; CHECK-NEXT: uzp1 v2.4s, v0.4s, v2.4s
-; CHECK-NEXT: zip1 v1.4s, v1.4s, v3.4s
-; CHECK-NEXT: zip2 v0.4s, v0.4s, v2.4s
-; CHECK-NEXT: str q1, [x0]
+; CHECK-NEXT: zip1 v2.8h, v4.8h, v5.8h
+; CHECK-NEXT: trn1 v3.8h, v6.8h, v7.8h
+; CHECK-NEXT: trn1 v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: uzp1 v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: zip1 v2.4s, v0.4s, v1.4s
+; CHECK-NEXT: zip2 v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: str q2, [x0]
; CHECK-NEXT: str q0, [x0, #64]
; CHECK-NEXT: ret
entry:
@@ -1684,26 +1615,14 @@ define void @transpose_s16_8x8_intrinsic(ptr nocapture noundef %0, ptr nocapture
}
define void @store_factor2_intrinsic(ptr %ptr, <4 x i32> %a0, <4 x i32> %a1) {
-; CHECK-IAENABLED-LABEL: store_factor2_intrinsic:
-; CHECK-IAENABLED: .Lfunc_begin27:
-; CHECK-IAENABLED-NEXT: .cfi_startproc
-; CHECK-IAENABLED-NEXT: // %bb.0:
-; CHECK-IAENABLED-NEXT: trn1 v2.4s, v0.4s, v1.4s
-; CHECK-IAENABLED-NEXT: trn1 v3.4s, v1.4s, v0.4s
-; CHECK-IAENABLED-NEXT: st2 { v2.4s, v3.4s }, [x0]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: store_factor2_intrinsic:
-; CHECK-IADISABLED: .Lfunc_begin27:
-; CHECK-IADISABLED-NEXT: .cfi_startproc
-; CHECK-IADISABLED-NEXT: // %bb.0:
-; CHECK-IADISABLED-NEXT: uzp1 v2.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: uzp1 v1.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: ext v0.16b, v2.16b, v0.16b, #8
-; CHECK-IADISABLED-NEXT: uzp2 v1.4s, v2.4s, v1.4s
-; CHECK-IADISABLED-NEXT: uzp1 v0.4s, v2.4s, v0.4s
-; CHECK-IADISABLED-NEXT: stp q0, q1, [x0]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: store_factor2_intrinsic:
+; CHECK: .Lfunc_begin27:
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: trn1 v2.4s, v0.4s, v1.4s
+; CHECK-NEXT: trn1 v3.4s, v1.4s, v0.4s
+; CHECK-NEXT: st2 { v2.4s, v3.4s }, [x0]
+; CHECK-NEXT: ret
%v0 = shufflevector <4 x i32> %a0, <4 x i32> %a1, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
%v1 = shufflevector <4 x i32> %a1, <4 x i32> %a0, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
%interleaved.vec = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %v0, <4 x i32> %v1)
diff --git a/llvm/test/CodeGen/X86/vector-interleave-intrinsics.ll b/llvm/test/CodeGen/X86/vector-interleave-intrinsics.ll
new file mode 100644
index 0000000000000..5046e822918cc
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vector-interleave-intrinsics.ll
@@ -0,0 +1,576 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+define void @interleave2(ptr %dst, <4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: interleave2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps %xmm0, %xmm2
+; CHECK-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT: movaps %xmm0, 16(%rdi)
+; CHECK-NEXT: movaps %xmm2, (%rdi)
+; CHECK-NEXT: retq
+ %result = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %v0, <4 x i32> %v1)
+ store <8 x i32> %result, ptr %dst
+ ret void
+}
+
+define void @deinterleave2(ptr %src, ptr %dst0, ptr %dst1) {
+; CHECK-LABEL: deinterleave2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps (%rdi), %xmm0
+; CHECK-NEXT: movaps 16(%rdi), %xmm1
+; CHECK-NEXT: movaps %xmm0, %xmm2
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,3],xmm1[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
+; CHECK-NEXT: movaps %xmm0, (%rsi)
+; CHECK-NEXT: movaps %xmm2, (%rdx)
+; CHECK-NEXT: retq
+ %wide = load <8 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2.v8i32(<8 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32> } %result, 1
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ ret void
+}
+
+define void @interleave3(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
+; CHECK-LABEL: interleave3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps %xmm2, %xmm3
+; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm0[1,3]
+; CHECK-NEXT: movaps %xmm0, %xmm4
+; CHECK-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm3[0,2]
+; CHECK-NEXT: movaps %xmm0, %xmm3
+; CHECK-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm1[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3],xmm1[3,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,2],xmm2[2,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1]
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm3[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0,1,3]
+; CHECK-NEXT: movaps %xmm2, 16(%rdi)
+; CHECK-NEXT: movaps %xmm4, (%rdi)
+; CHECK-NEXT: movaps %xmm0, 32(%rdi)
+; CHECK-NEXT: retq
+ %result = call <12 x i32> @llvm.vector.interleave3.v12i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2)
+ store <12 x i32> %result, ptr %dst
+ ret void
+}
+
+define void @deinterleave3(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2) {
+; CHECK-LABEL: deinterleave3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa (%rdi), %xmm0
+; CHECK-NEXT: movdqa 16(%rdi), %xmm1
+; CHECK-NEXT: movaps 32(%rdi), %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm2[0,3]
+; CHECK-NEXT: movdqa %xmm1, %xmm3
+; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1],xmm2[2,3]
+; CHECK-NEXT: movdqa %xmm0, %xmm5
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,0],xmm1[0,0]
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2],xmm3[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[1,0]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm1[0,2]
+; CHECK-NEXT: movaps %xmm0, (%rsi)
+; CHECK-NEXT: movaps %xmm5, (%rdx)
+; CHECK-NEXT: movaps %xmm4, (%rcx)
+; CHECK-NEXT: retq
+ %wide = load <12 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave3.v12i32(<12 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ ret void
+}
+
+define void @interleave4(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
+; CHECK-LABEL: interleave4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps %xmm2, %xmm4
+; CHECK-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
+; CHECK-NEXT: movaps %xmm0, %xmm5
+; CHECK-NEXT: unpcklps {{.*#+}} xmm5 = xmm5[0],xmm1[0],xmm5[1],xmm1[1]
+; CHECK-NEXT: movaps %xmm5, %xmm6
+; CHECK-NEXT: movlhps {{.*#+}} xmm6 = xmm6[0],xmm4[0]
+; CHECK-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm4[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm2 = xmm2[2],xmm3[2],xmm2[3],xmm3[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT: movaps %xmm0, %xmm1
+; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm2[1]
+; CHECK-NEXT: movaps %xmm0, 48(%rdi)
+; CHECK-NEXT: movaps %xmm1, 32(%rdi)
+; CHECK-NEXT: movaps %xmm5, 16(%rdi)
+; CHECK-NEXT: movaps %xmm6, (%rdi)
+; CHECK-NEXT: retq
+ %result = call <16 x i32> @llvm.vector.interleave4.v16i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3)
+ store <16 x i32> %result, ptr %dst
+ ret void
+}
+
+define void @deinterleave4(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2, ptr %dst3) {
+; CHECK-LABEL: deinterleave4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps (%rdi), %xmm0
+; CHECK-NEXT: movaps 16(%rdi), %xmm1
+; CHECK-NEXT: movaps 32(%rdi), %xmm2
+; CHECK-NEXT: movaps 48(%rdi), %xmm3
+; CHECK-NEXT: movaps %xmm2, %xmm4
+; CHECK-NEXT: unpckhps {{.*#+}} xmm4 = xmm4[2],xmm3[2],xmm4[3],xmm3[3]
+; CHECK-NEXT: movaps %xmm0, %xmm5
+; CHECK-NEXT: unpckhps {{.*#+}} xmm5 = xmm5[2],xmm1[2],xmm5[3],xmm1[3]
+; CHECK-NEXT: movaps %xmm5, %xmm6
+; CHECK-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm4[1]
+; CHECK-NEXT: movlhps {{.*#+}} xmm5 = xmm5[0],xmm4[0]
+; CHECK-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
+; CHECK-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; CHECK-NEXT: movaps %xmm0, %xmm1
+; CHECK-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1]
+; CHECK-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; CHECK-NEXT: movaps %xmm0, (%rsi)
+; CHECK-NEXT: movaps %xmm1, (%rdx)
+; CHECK-NEXT: movaps %xmm5, (%rcx)
+; CHECK-NEXT: movaps %xmm6, (%r8)
+; CHECK-NEXT: retq
+ %wide = load <16 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave4.v16i32(<16 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ %v3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ store <4 x i32> %v3, ptr %dst3
+ ret void
+}
+
+define void @interleave5(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4) {
+; CHECK-LABEL: interleave5:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps %xmm2, %xmm5
+; CHECK-NEXT: unpcklps {{.*#+}} xmm5 = xmm5[0],xmm3[0],xmm5[1],xmm3[1]
+; CHECK-NEXT: movaps %xmm0, %xmm6
+; CHECK-NEXT: unpcklps {{.*#+}} xmm6 = xmm6[0],xmm1[0],xmm6[1],xmm1[1]
+; CHECK-NEXT: movlhps {{.*#+}} xmm6 = xmm6[0],xmm5[0]
+; CHECK-NEXT: movaps %xmm0, %xmm5
+; CHECK-NEXT: unpckhps {{.*#+}} xmm5 = xmm5[2],xmm1[2],xmm5[3],xmm1[3]
+; CHECK-NEXT: movaps %xmm4, %xmm7
+; CHECK-NEXT: shufps {{.*#+}} xmm7 = xmm7[1,1],xmm3[1,1]
+; CHECK-NEXT: shufps {{.*#+}} xmm7 = xmm7[2,0],xmm5[0,1]
+; CHECK-NEXT: movaps %xmm4, %xmm5
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[2,1],xmm0[3,3]
+; CHECK-NEXT: movaps %xmm4, %xmm8
+; CHECK-NEXT: shufps {{.*#+}} xmm8 = xmm8[3,3],xmm3[3,3]
+; CHECK-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm2[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[2,0],xmm5[0,2]
+; CHECK-NEXT: movaps %xmm1, %xmm5
+; CHECK-NEXT: unpckhps {{.*#+}} xmm5 = xmm5[2],xmm2[2],xmm5[3],xmm2[3]
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[2,3],xmm8[2,0]
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
+; CHECK-NEXT: movss {{.*#+}} xmm0 = xmm4[0],xmm0[1,2,3]
+; CHECK-NEXT: movaps %xmm5, 64(%rdi)
+; CHECK-NEXT: movaps %xmm3, 48(%rdi)
+; CHECK-NEXT: movaps %xmm7, 32(%rdi)
+; CHECK-NEXT: movaps %xmm6, (%rdi)
+; CHECK-NEXT: movaps %xmm0, 16(%rdi)
+; CHECK-NEXT: retq
+ %result = call <20 x i32> @llvm.vector.interleave5.v20i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4)
+ store <20 x i32> %result, ptr %dst
+ ret void
+}
+
+define void @deinterleave5(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2, ptr %dst3, ptr %dst4) {
+; CHECK-LABEL: deinterleave5:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps 64(%rdi), %xmm1
+; CHECK-NEXT: movdqa (%rdi), %xmm0
+; CHECK-NEXT: movdqa 16(%rdi), %xmm4
+; CHECK-NEXT: movdqa 32(%rdi), %xmm2
+; CHECK-NEXT: movdqa 48(%rdi), %xmm3
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm2[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm4[2,2,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm4[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm4[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
+; CHECK-NEXT: movdqa %xmm3, %xmm5
+; CHECK-NEXT: movdqa %xmm3, %xmm9
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm2[2,2,2,2]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm10 = xmm10[2],xmm3[2],xmm10[3],xmm3[3]
+; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[2,0],xmm1[3,0]
+; CHECK-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm3[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,1],xmm1[2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm5[0,2]
+; CHECK-NEXT: movdqa %xmm0, %xmm5
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm5 = xmm5[2],xmm6[2],xmm5[3],xmm6[3]
+; CHECK-NEXT: shufps {{.*#+}} xmm9 = xmm9[0,1],xmm1[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,1],xmm9[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,1],xmm1[0,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm7[0],xmm1[1],xmm7[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm8[0],xmm0[1],xmm8[1]
+; CHECK-NEXT: movsd {{.*#+}} xmm10 = xmm0[0],xmm10[1]
+; CHECK-NEXT: movapd %xmm10, (%rsi)
+; CHECK-NEXT: movaps %xmm1, (%rdx)
+; CHECK-NEXT: movaps %xmm5, (%rcx)
+; CHECK-NEXT: movaps %xmm3, (%r8)
+; CHECK-NEXT: movaps %xmm4, (%r9)
+; CHECK-NEXT: retq
+ %wide = load <20 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave5.v20i32(<20 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ %v3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ %v4 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 4
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ store <4 x i32> %v3, ptr %dst3
+ store <4 x i32> %v4, ptr %dst4
+ ret void
+}
+
+define void @interleave6(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5) {
+; CHECK-LABEL: interleave6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps %xmm2, %xmm6
+; CHECK-NEXT: unpcklps {{.*#+}} xmm6 = xmm6[0],xmm3[0],xmm6[1],xmm3[1]
+; CHECK-NEXT: movaps %xmm0, %xmm7
+; CHECK-NEXT: unpcklps {{.*#+}} xmm7 = xmm7[0],xmm1[0],xmm7[1],xmm1[1]
+; CHECK-NEXT: movaps %xmm5, %xmm8
+; CHECK-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm4[0]
+; CHECK-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm7[2,3]
+; CHECK-NEXT: movlhps {{.*#+}} xmm7 = xmm7[0],xmm6[0]
+; CHECK-NEXT: movaps %xmm5, %xmm9
+; CHECK-NEXT: shufps {{.*#+}} xmm9 = xmm9[1,1],xmm4[1,1]
+; CHECK-NEXT: shufps {{.*#+}} xmm6 = xmm6[2,3],xmm9[2,0]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm2 = xmm2[2],xmm3[2],xmm2[3],xmm3[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT: movaps %xmm5, %xmm1
+; CHECK-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm4[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
+; CHECK-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3],xmm4[3,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,3],xmm5[2,0]
+; CHECK-NEXT: movaps %xmm2, 80(%rdi)
+; CHECK-NEXT: movaps %xmm1, 64(%rdi)
+; CHECK-NEXT: movaps %xmm0, 48(%rdi)
+; CHECK-NEXT: movaps %xmm6, 32(%rdi)
+; CHECK-NEXT: movaps %xmm8, 16(%rdi)
+; CHECK-NEXT: movaps %xmm7, (%rdi)
+; CHECK-NEXT: retq
+ %result = call <24 x i32> @llvm.vector.interleave6.v24i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5)
+ store <24 x i32> %result, ptr %dst
+ ret void
+}
+
+define void @deinterleave6(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2, ptr %dst3, ptr %dst4, ptr %dst5) {
+; CHECK-LABEL: deinterleave6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: movdqa (%rdi), %xmm0
+; CHECK-NEXT: movdqa 16(%rdi), %xmm6
+; CHECK-NEXT: movdqa 32(%rdi), %xmm4
+; CHECK-NEXT: movapd 48(%rdi), %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm4[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm6[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm7 = xmm7[0],xmm1[0],xmm7[1],xmm1[1]
+; CHECK-NEXT: movdqa 64(%rdi), %xmm3
+; CHECK-NEXT: movdqa 80(%rdi), %xmm5
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm5[2,3,2,3]
+; CHECK-NEXT: movdqa %xmm3, %xmm1
+; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm8[0],xmm1[1],xmm8[1]
+; CHECK-NEXT: movsd {{.*#+}} xmm1 = xmm7[0],xmm1[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm4[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm6[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm6[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm5[2,2,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm3[0,0,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm10 = xmm10[0],xmm7[0],xmm10[1],xmm7[1]
+; CHECK-NEXT: movsd {{.*#+}} xmm10 = xmm6[0],xmm10[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm4[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm0[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm7 = xmm7[0],xmm6[0],xmm7[1],xmm6[1]
+; CHECK-NEXT: movapd %xmm2, %xmm6
+; CHECK-NEXT: movsd {{.*#+}} xmm6 = xmm5[0],xmm6[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,1],xmm2[3,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,1],xmm5[2,0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm0[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,1],xmm6[2,0]
+; CHECK-NEXT: movdqa %xmm3, %xmm4
+; CHECK-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,1],xmm2[1,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm0[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm8[0],xmm6[1],xmm8[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,1],xmm4[2,0]
+; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[2,3],xmm2[0,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm9[0],xmm0[1],xmm9[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,0]
+; CHECK-NEXT: movaps %xmm0, (%rsi)
+; CHECK-NEXT: movaps %xmm6, (%rdx)
+; CHECK-NEXT: movaps %xmm5, (%rcx)
+; CHECK-NEXT: movaps %xmm7, (%r8)
+; CHECK-NEXT: movapd %xmm10, (%r9)
+; CHECK-NEXT: movapd %xmm1, (%rax)
+; CHECK-NEXT: retq
+ %wide = load <24 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave6.v24i32(<24 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ %v3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ %v4 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 4
+ %v5 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 5
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ store <4 x i32> %v3, ptr %dst3
+ store <4 x i32> %v4, ptr %dst4
+ store <4 x i32> %v5, ptr %dst5
+ ret void
+}
+
+define void @interleave7(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6) {
+; CHECK-LABEL: interleave7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps %xmm2, %xmm8
+; CHECK-NEXT: unpcklps {{.*#+}} xmm8 = xmm8[0],xmm3[0],xmm8[1],xmm3[1]
+; CHECK-NEXT: movaps %xmm0, %xmm7
+; CHECK-NEXT: unpcklps {{.*#+}} xmm7 = xmm7[0],xmm1[0],xmm7[1],xmm1[1]
+; CHECK-NEXT: movlhps {{.*#+}} xmm7 = xmm7[0],xmm8[0]
+; CHECK-NEXT: movaps %xmm6, %xmm9
+; CHECK-NEXT: shufps {{.*#+}} xmm9 = xmm9[0,1],xmm0[1,3]
+; CHECK-NEXT: movaps %xmm4, %xmm10
+; CHECK-NEXT: shufps {{.*#+}} xmm10 = xmm10[1,1],xmm3[1,1]
+; CHECK-NEXT: movaps %xmm4, %xmm11
+; CHECK-NEXT: movaps %xmm2, %xmm8
+; CHECK-NEXT: unpckhps {{.*#+}} xmm8 = xmm8[2],xmm3[2],xmm8[3],xmm3[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm3 = xmm3[2],xmm4[2],xmm3[3],xmm4[3]
+; CHECK-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm9[0,2]
+; CHECK-NEXT: movaps %xmm1, %xmm9
+; CHECK-NEXT: unpcklps {{.*#+}} xmm9 = xmm9[0],xmm2[0],xmm9[1],xmm2[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm9 = xmm9[2,3],xmm10[2,0]
+; CHECK-NEXT: movaps %xmm0, %xmm10
+; CHECK-NEXT: unpckhps {{.*#+}} xmm10 = xmm10[2],xmm1[2],xmm10[3],xmm1[3]
+; CHECK-NEXT: movaps %xmm5, %xmm12
+; CHECK-NEXT: unpcklps {{.*#+}} xmm12 = xmm12[0],xmm6[0],xmm12[1],xmm6[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm12 = xmm12[2,3],xmm10[0,1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm11 = xmm11[2],xmm5[2],xmm11[3],xmm5[3]
+; CHECK-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm11[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm6[2,3,2,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3],xmm5[3,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[2,3],xmm6[2,0]
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3],xmm1[3,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm2[2,0]
+; CHECK-NEXT: movss {{.*#+}} xmm0 = xmm10[0],xmm0[1,2,3]
+; CHECK-NEXT: movaps %xmm3, 96(%rdi)
+; CHECK-NEXT: movaps %xmm8, 64(%rdi)
+; CHECK-NEXT: movaps %xmm12, 48(%rdi)
+; CHECK-NEXT: movaps %xmm9, 32(%rdi)
+; CHECK-NEXT: movaps %xmm4, 16(%rdi)
+; CHECK-NEXT: movaps %xmm7, (%rdi)
+; CHECK-NEXT: movaps %xmm0, 80(%rdi)
+; CHECK-NEXT: retq
+ %result = call <28 x i32> @llvm.vector.interleave7.v28i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6)
+ store <28 x i32> %result, ptr %dst
+ ret void
+}
+
+define void @deinterleave7(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2, ptr %dst3, ptr %dst4, ptr %dst5, ptr %dst6) {
+; CHECK-LABEL: deinterleave7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; CHECK-NEXT: movaps 80(%rdi), %xmm0
+; CHECK-NEXT: movaps 96(%rdi), %xmm7
+; CHECK-NEXT: movaps %xmm7, %xmm3
+; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1],xmm0[0,3]
+; CHECK-NEXT: movdqa (%rdi), %xmm2
+; CHECK-NEXT: movdqa 16(%rdi), %xmm8
+; CHECK-NEXT: movdqa 32(%rdi), %xmm6
+; CHECK-NEXT: movdqa 48(%rdi), %xmm4
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm4[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm8[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm5[0],xmm1[1],xmm5[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,0]
+; CHECK-NEXT: movaps 64(%rdi), %xmm3
+; CHECK-NEXT: movaps %xmm7, %xmm9
+; CHECK-NEXT: shufps {{.*#+}} xmm9 = xmm9[2,1],xmm3[3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm8[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,1],xmm9[2,0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm7[0,0,1,1]
+; CHECK-NEXT: shufps {{.*#+}} xmm7 = xmm7[1,0],xmm3[2,0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm6[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm11 = xmm8[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm8 = xmm8[0],xmm10[0],xmm8[1],xmm10[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,1],xmm7[2,0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm2[2,2,3,3]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm7 = xmm7[2],xmm6[2],xmm7[3],xmm6[3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm3[0,0,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm9[0],xmm3[1],xmm9[1]
+; CHECK-NEXT: movsd {{.*#+}} xmm3 = xmm7[0],xmm3[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm6[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm2[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm7[0],xmm9[1],xmm7[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm0[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm10 = xmm10[0],xmm7[0],xmm10[1],xmm7[1]
+; CHECK-NEXT: movsd {{.*#+}} xmm10 = xmm9[0],xmm10[1]
+; CHECK-NEXT: movaps %xmm0, %xmm7
+; CHECK-NEXT: shufps {{.*#+}} xmm7 = xmm7[2,1],xmm4[3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm2[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm6[0],xmm9[1],xmm6[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm9 = xmm9[0,1],xmm7[2,0]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm4[2,0]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm11[0],xmm2[1],xmm11[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,0]
+; CHECK-NEXT: movaps %xmm2, (%rsi)
+; CHECK-NEXT: movaps %xmm9, (%rdx)
+; CHECK-NEXT: movapd %xmm10, (%rcx)
+; CHECK-NEXT: movapd %xmm3, (%r8)
+; CHECK-NEXT: movaps %xmm8, (%r9)
+; CHECK-NEXT: movaps %xmm5, (%r10)
+; CHECK-NEXT: movaps %xmm1, (%rax)
+; CHECK-NEXT: retq
+ %wide = load <28 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave7.v28i32(<28 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ %v3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ %v4 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 4
+ %v5 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 5
+ %v6 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 6
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ store <4 x i32> %v3, ptr %dst3
+ store <4 x i32> %v4, ptr %dst4
+ store <4 x i32> %v5, ptr %dst5
+ store <4 x i32> %v6, ptr %dst6
+ ret void
+}
+
+define void @interleave8(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6, <4 x i32> %v7) {
+; CHECK-LABEL: interleave8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps %xmm2, %xmm10
+; CHECK-NEXT: unpcklps {{.*#+}} xmm10 = xmm10[0],xmm3[0],xmm10[1],xmm3[1]
+; CHECK-NEXT: movaps %xmm0, %xmm9
+; CHECK-NEXT: unpcklps {{.*#+}} xmm9 = xmm9[0],xmm1[0],xmm9[1],xmm1[1]
+; CHECK-NEXT: movaps %xmm9, %xmm8
+; CHECK-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm10[0]
+; CHECK-NEXT: movaps %xmm6, %xmm11
+; CHECK-NEXT: unpcklps {{.*#+}} xmm11 = xmm11[0],xmm7[0],xmm11[1],xmm7[1]
+; CHECK-NEXT: movaps %xmm4, %xmm12
+; CHECK-NEXT: unpcklps {{.*#+}} xmm12 = xmm12[0],xmm5[0],xmm12[1],xmm5[1]
+; CHECK-NEXT: movaps %xmm12, %xmm13
+; CHECK-NEXT: movlhps {{.*#+}} xmm13 = xmm13[0],xmm11[0]
+; CHECK-NEXT: unpckhpd {{.*#+}} xmm9 = xmm9[1],xmm10[1]
+; CHECK-NEXT: unpckhpd {{.*#+}} xmm12 = xmm12[1],xmm11[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm2 = xmm2[2],xmm3[2],xmm2[3],xmm3[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT: movaps %xmm0, %xmm1
+; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm6 = xmm6[2],xmm7[2],xmm6[3],xmm7[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm4 = xmm4[2],xmm5[2],xmm4[3],xmm5[3]
+; CHECK-NEXT: movaps %xmm4, %xmm3
+; CHECK-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm6[0]
+; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm2[1]
+; CHECK-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm6[1]
+; CHECK-NEXT: movaps %xmm4, 112(%rdi)
+; CHECK-NEXT: movaps %xmm0, 96(%rdi)
+; CHECK-NEXT: movaps %xmm3, 80(%rdi)
+; CHECK-NEXT: movaps %xmm1, 64(%rdi)
+; CHECK-NEXT: movaps %xmm12, 48(%rdi)
+; CHECK-NEXT: movaps %xmm9, 32(%rdi)
+; CHECK-NEXT: movaps %xmm13, 16(%rdi)
+; CHECK-NEXT: movaps %xmm8, (%rdi)
+; CHECK-NEXT: retq
+ %result = call <32 x i32> @llvm.vector.interleave8.v32i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6, <4 x i32> %v7)
+ store <32 x i32> %result, ptr %dst
+ ret void
+}
+
+define void @deinterleave8(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2, ptr %dst3, ptr %dst4, ptr %dst5, ptr %dst6, ptr %dst7) {
+; CHECK-LABEL: deinterleave8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; CHECK-NEXT: movaps 112(%rdi), %xmm4
+; CHECK-NEXT: movaps 80(%rdi), %xmm5
+; CHECK-NEXT: movaps %xmm5, %xmm6
+; CHECK-NEXT: unpckhps {{.*#+}} xmm6 = xmm6[2],xmm4[2],xmm6[3],xmm4[3]
+; CHECK-NEXT: movaps (%rdi), %xmm3
+; CHECK-NEXT: movaps 16(%rdi), %xmm0
+; CHECK-NEXT: movaps 32(%rdi), %xmm7
+; CHECK-NEXT: movaps 48(%rdi), %xmm8
+; CHECK-NEXT: movaps %xmm0, %xmm1
+; CHECK-NEXT: unpckhps {{.*#+}} xmm1 = xmm1[2],xmm8[2],xmm1[3],xmm8[3]
+; CHECK-NEXT: movaps %xmm1, %xmm2
+; CHECK-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm6[1]
+; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm6[0]
+; CHECK-NEXT: unpcklps {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1]
+; CHECK-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm8[0],xmm0[1],xmm8[1]
+; CHECK-NEXT: movaps %xmm0, %xmm4
+; CHECK-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm5[1]
+; CHECK-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm5[0]
+; CHECK-NEXT: movaps 96(%rdi), %xmm5
+; CHECK-NEXT: movaps 64(%rdi), %xmm6
+; CHECK-NEXT: movaps %xmm6, %xmm8
+; CHECK-NEXT: unpckhps {{.*#+}} xmm8 = xmm8[2],xmm5[2],xmm8[3],xmm5[3]
+; CHECK-NEXT: movaps %xmm3, %xmm9
+; CHECK-NEXT: unpckhps {{.*#+}} xmm9 = xmm9[2],xmm7[2],xmm9[3],xmm7[3]
+; CHECK-NEXT: movaps %xmm9, %xmm10
+; CHECK-NEXT: unpckhpd {{.*#+}} xmm10 = xmm10[1],xmm8[1]
+; CHECK-NEXT: movlhps {{.*#+}} xmm9 = xmm9[0],xmm8[0]
+; CHECK-NEXT: unpcklps {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1]
+; CHECK-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm7[0],xmm3[1],xmm7[1]
+; CHECK-NEXT: movaps %xmm3, %xmm5
+; CHECK-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm6[1]
+; CHECK-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm6[0]
+; CHECK-NEXT: movaps %xmm3, (%rsi)
+; CHECK-NEXT: movaps %xmm5, (%rdx)
+; CHECK-NEXT: movaps %xmm9, (%rcx)
+; CHECK-NEXT: movaps %xmm10, (%r8)
+; CHECK-NEXT: movaps %xmm0, (%r9)
+; CHECK-NEXT: movaps %xmm4, (%r11)
+; CHECK-NEXT: movaps %xmm1, (%r10)
+; CHECK-NEXT: movaps %xmm2, (%rax)
+; CHECK-NEXT: retq
+ %wide = load <32 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave8.v32i32(<32 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ %v3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ %v4 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 4
+ %v5 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 5
+ %v6 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 6
+ %v7 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 7
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ store <4 x i32> %v3, ptr %dst3
+ store <4 x i32> %v4, ptr %dst4
+ store <4 x i32> %v5, ptr %dst5
+ store <4 x i32> %v6, ptr %dst6
+ store <4 x i32> %v7, ptr %dst7
+ ret void
+}
More information about the llvm-commits
mailing list