[llvm] [AMDGPU] Improved register pressure estimates for rescheduling (PR #213116)

[Shilei Tian via llvm-commits]

https://github.com/shiltian commented:

I like the idea of having register pressure that more closely reflects the actual RA for instruction scheduling. I actually have a couple of tickets that might be addressed by this: ROCM-9525 and ROCM-8818. I believe both were caused by the discrepancy in register pressure between instruction scheduling and RA.

However, I'm wondering how close the simulation is to the actual RA, and how expensive it is. I'm somewhat concerned about the compile-time impact. We've encountered some nasty test cases where the RA itself can take several minutes.

https://github.com/llvm/llvm-project/pull/213116