[llvm] [AArch64][GlobalISel] Change the remaining tests to concrete types. NFC (PR #215383)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 10 13:14:11 PDT 2026
https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/215383
None
>From 32b32e85e695647f69c7b815e555e1a9228094c0 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Mon, 10 Aug 2026 21:13:59 +0100
Subject: [PATCH] [AArch64][GlobalISel] Change the remaining tests to concrete
types. NFC
---
.../arm64-saddlp1d-uaddlp1d.mir | 24 +-
.../AArch64/GlobalISel/inline-memcpy.mir | 32 +-
.../AArch64/GlobalISel/inline-memmove.mir | 24 +-
.../GlobalISel/inline-memset-forced.mir | 5 +-
.../AArch64/GlobalISel/inline-memset.mir | 82 ++--
.../GlobalISel/inline-small-memcpy.mir | 12 +-
.../AArch64/GlobalISel/legalize-undef.mir | 2 +-
.../GlobalISel/load-addressing-modes.mir | 8 +-
.../localizer-propagate-debug-loc.mir | 84 ++--
.../CodeGen/AArch64/GlobalISel/localizer.mir | 404 +++++++++---------
10 files changed, 338 insertions(+), 339 deletions(-)
rename llvm/test/CodeGen/AArch64/{ => GlobalISel}/arm64-saddlp1d-uaddlp1d.mir (65%)
diff --git a/llvm/test/CodeGen/AArch64/arm64-saddlp1d-uaddlp1d.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-saddlp1d-uaddlp1d.mir
similarity index 65%
rename from llvm/test/CodeGen/AArch64/arm64-saddlp1d-uaddlp1d.mir
rename to llvm/test/CodeGen/AArch64/GlobalISel/arm64-saddlp1d-uaddlp1d.mir
index 074f75ab8a5f0..deb3945a75bcb 100644
--- a/llvm/test/CodeGen/AArch64/arm64-saddlp1d-uaddlp1d.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-saddlp1d-uaddlp1d.mir
@@ -14,14 +14,14 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fpr(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>))
- ; CHECK-NEXT: [[SADDLP:%[0-9]+]]:fpr(s64) = G_SADDLP [[LOAD]]
- ; CHECK-NEXT: $d0 = COPY [[SADDLP]](s64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fpr(<2 x i32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>))
+ ; CHECK-NEXT: [[SADDLP:%[0-9]+]]:fpr(i64) = G_SADDLP [[LOAD]]
+ ; CHECK-NEXT: $d0 = COPY [[SADDLP]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(p0) = COPY $x0
- %1:_(<2 x s32>) = G_LOAD %0(p0) :: (load (<2 x s32>))
- %2:_(s64) = G_SADDLP %1
- $d0 = COPY %2(s64)
+ %1:_(<2 x i32>) = G_LOAD %0(p0) :: (load (<2 x s32>))
+ %2:_(i64) = G_SADDLP %1
+ $d0 = COPY %2(i64)
RET_ReallyLR implicit $d0
...
---
@@ -38,13 +38,13 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fpr(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>))
- ; CHECK-NEXT: [[UADDLP:%[0-9]+]]:fpr(s64) = G_UADDLP [[LOAD]]
- ; CHECK-NEXT: $d0 = COPY [[UADDLP]](s64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fpr(<2 x i32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>))
+ ; CHECK-NEXT: [[UADDLP:%[0-9]+]]:fpr(i64) = G_UADDLP [[LOAD]]
+ ; CHECK-NEXT: $d0 = COPY [[UADDLP]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(p0) = COPY $x0
- %1:_(<2 x s32>) = G_LOAD %0(p0) :: (load (<2 x s32>))
- %2:_(s64) = G_UADDLP %1
- $d0 = COPY %2(s64)
+ %1:_(<2 x i32>) = G_LOAD %0(p0) :: (load (<2 x s32>))
+ %2:_(i64) = G_UADDLP %1
+ $d0 = COPY %2(i64)
RET_ReallyLR implicit $d0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
index dea5f4cb8c8ad..f9746df3b875f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
@@ -36,13 +36,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[COPY2]](s64), 1 :: (store (s8), align 4), (load (s8), align 4)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[COPY2]](i64), 1 :: (store (s8), align 4), (load (s8), align 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
- %2:_(s64) = COPY $x2
- G_MEMCPY %0(p0), %1(p0), %2(s64), 1 :: (store (s8), align 4), (load (s8), align 4)
+ %2:_(i64) = COPY $x2
+ G_MEMCPY %0(p0), %1(p0), %2(i64), 1 :: (store (s8), align 4), (load (s8), align 4)
RET_ReallyLR
...
@@ -89,8 +89,8 @@ body: |
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
- %2:_(s64) = G_CONSTANT i64 72
- G_MEMCPY %0(p0), %1(p0), %2(s64), 1 :: (store (s8), align 4), (load (s8), align 4)
+ %2:_(i64) = G_CONSTANT i64 72
+ G_MEMCPY %0(p0), %1(p0), %2(i64), 1 :: (store (s8), align 4), (load (s8), align 4)
RET_ReallyLR
...
@@ -137,8 +137,8 @@ body: |
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
- %2:_(s64) = G_CONSTANT i64 72
- G_MEMCPY %0(p0), %1(p0), %2(s64), 1 :: (store (s8), align 4), (load (s8), align 4)
+ %2:_(i64) = G_CONSTANT i64 72
+ G_MEMCPY %0(p0), %1(p0), %2(i64), 1 :: (store (s8), align 4), (load (s8), align 4)
RET_ReallyLR
...
@@ -160,13 +160,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 72
- ; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[C]](s64), 1 :: (store (s8), align 4), (load (s8), align 4)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 72
+ ; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[C]](i64), 1 :: (store (s8), align 4), (load (s8), align 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
- %2:_(s64) = G_CONSTANT i64 72
- G_MEMCPY %0(p0), %1(p0), %2(s64), 1 :: (store (s8), align 4), (load (s8), align 4)
+ %2:_(i64) = G_CONSTANT i64 72
+ G_MEMCPY %0(p0), %1(p0), %2(i64), 1 :: (store (s8), align 4), (load (s8), align 4)
RET_ReallyLR
...
@@ -233,8 +233,8 @@ body: |
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
- %2:_(s64) = G_CONSTANT i64 143
- G_MEMCPY %0(p0), %1(p0), %2(s64), 1 :: (store (s8), align 4), (load (s8), align 4)
+ %2:_(i64) = G_CONSTANT i64 143
+ G_MEMCPY %0(p0), %1(p0), %2(i64), 1 :: (store (s8), align 4), (load (s8), align 4)
RET_ReallyLR
...
@@ -281,8 +281,8 @@ body: |
; CHECK-NEXT: RET_ReallyLR
%0:_(p1) = COPY $x0
%1:_(p2) = COPY $x1
- %2:_(s64) = G_CONSTANT i64 72
- G_MEMCPY %0(p1), %1(p2), %2(s64), 1 :: (store (s8), align 4, addrspace 1), (load (s8), align 4, addrspace 2)
+ %2:_(i64) = G_CONSTANT i64 72
+ G_MEMCPY %0(p1), %1(p2), %2(i64), 1 :: (store (s8), align 4, addrspace 1), (load (s8), align 4, addrspace 2)
RET_ReallyLR
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
index 6441d0ea96989..c42e739f9e4d5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
@@ -27,13 +27,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: G_MEMMOVE [[COPY]](p0), [[COPY1]](p0), [[COPY2]](s64), 1 :: (store (s8), align 4), (load (s8), align 4)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: G_MEMMOVE [[COPY]](p0), [[COPY1]](p0), [[COPY2]](i64), 1 :: (store (s8), align 4), (load (s8), align 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
- %2:_(s64) = COPY $x2
- G_MEMMOVE %0(p0), %1(p0), %2(s64), 1 :: (store (s8), align 4), (load (s8), align 4)
+ %2:_(i64) = COPY $x2
+ G_MEMMOVE %0(p0), %1(p0), %2(i64), 1 :: (store (s8), align 4), (load (s8), align 4)
RET_ReallyLR
...
@@ -67,8 +67,8 @@ body: |
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
- %2:_(s64) = G_CONSTANT i64 48
- G_MEMMOVE %0(p0), %1(p0), %2(s64), 1 :: (store (s8), align 4), (load (s8), align 4)
+ %2:_(i64) = G_CONSTANT i64 48
+ G_MEMMOVE %0(p0), %1(p0), %2(i64), 1 :: (store (s8), align 4), (load (s8), align 4)
RET_ReallyLR
...
@@ -120,8 +120,8 @@ body: |
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
- %2:_(s64) = G_CONSTANT i64 96
- G_MEMMOVE %0(p0), %1(p0), %2(s64), 1 :: (store (s8), align 4), (load (s8), align 4)
+ %2:_(i64) = G_CONSTANT i64 96
+ G_MEMMOVE %0(p0), %1(p0), %2(i64), 1 :: (store (s8), align 4), (load (s8), align 4)
RET_ReallyLR
...
@@ -161,8 +161,8 @@ body: |
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
- %2:_(s64) = G_CONSTANT i64 52
- G_MEMMOVE %0(p0), %1(p0), %2(s64), 1 :: (store (s8), align 4), (load (s8), align 4)
+ %2:_(i64) = G_CONSTANT i64 52
+ G_MEMMOVE %0(p0), %1(p0), %2(i64), 1 :: (store (s8), align 4), (load (s8), align 4)
RET_ReallyLR
...
@@ -196,8 +196,8 @@ body: |
; CHECK-NEXT: RET_ReallyLR
%0:_(p1) = COPY $x0
%1:_(p2) = COPY $x1
- %2:_(s64) = G_CONSTANT i64 48
- G_MEMMOVE %0(p1), %1(p2), %2(s64), 1 :: (store (s8), align 4, addrspace 1), (load (s8), align 4, addrspace 2)
+ %2:_(i64) = G_CONSTANT i64 48
+ G_MEMMOVE %0(p1), %1(p2), %2(i64), 1 :: (store (s8), align 4, addrspace 1), (load (s8), align 4, addrspace 2)
RET_ReallyLR
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset-forced.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset-forced.mir
index 816ce08acfb93..a3a013dcf7fcb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset-forced.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset-forced.mir
@@ -66,12 +66,11 @@ body: |
; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C8]](s64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD7]](p0) :: (store (<2 x i64>) into %ir.dst + 127, align 1, basealign 4)
; CHECK-NEXT: RET_ReallyLR
- ;
%0:_(p0) = COPY $x0
%1:_(i32) = COPY $w1
%2:_(i8) = G_TRUNC %1(i32)
- %3:_(s64) = G_CONSTANT i64 143
- G_MEMSET_INLINE %0(p0), %2(i8), %3(s64) :: (store (s8) into %ir.dst, align 4)
+ %3:_(i64) = G_CONSTANT i64 143
+ G_MEMSET_INLINE %0(p0), %2(i8), %3(i64) :: (store (s8) into %ir.dst, align 4)
RET_ReallyLR
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
index 0fdb388200cee..741c94e2e8cee 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
@@ -66,18 +66,18 @@ body: |
; CHECK: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
- ; CHECK-NEXT: G_MEMSET [[COPY]](p0), [[TRUNC]](s8), [[ZEXT]](s64), 1 :: (store (s8) into %ir.dst)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY2]](i32)
+ ; CHECK-NEXT: G_MEMSET [[COPY]](p0), [[TRUNC]](i8), [[ZEXT]](i64), 1 :: (store (s8) into %ir.dst)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
- %1:_(s32) = COPY $w1
- %2:_(s32) = COPY $w2
- %3:_(s8) = G_TRUNC %1(s32)
- %4:_(s64) = G_ZEXT %2(s32)
- G_MEMSET %0(p0), %3(s8), %4(s64), 1 :: (store (s8) into %ir.dst)
+ %1:_(i32) = COPY $w1
+ %2:_(i32) = COPY $w2
+ %3:_(i8) = G_TRUNC %1(i32)
+ %4:_(i64) = G_ZEXT %2(i32)
+ G_MEMSET %0(p0), %3(i8), %4(i64), 1 :: (store (s8) into %ir.dst)
RET_ReallyLR
...
@@ -93,19 +93,19 @@ body: |
; CHECK: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[TRUNC]](s8)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[TRUNC]](i8)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 72340172838076673
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MUL]](i64), [[MUL]](i64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
- %1:_(s32) = COPY $w1
- %3:_(s64) = G_CONSTANT i64 16
- %2:_(s8) = G_TRUNC %1(s32)
- G_MEMSET %0(p0), %2(s8), %3(s64), 1 :: (store (s8) into %ir.dst)
+ %1:_(i32) = COPY $w1
+ %3:_(i64) = G_CONSTANT i64 16
+ %2:_(i8) = G_TRUNC %1(i32)
+ G_MEMSET %0(p0), %2(i8), %3(i64), 1 :: (store (s8) into %ir.dst)
RET_ReallyLR
...
@@ -135,10 +135,10 @@ body: |
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD2]](p0) :: (store (<2 x i64>) into %ir.dst + 48, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
- %1:_(s32) = G_CONSTANT i32 0
- %3:_(s64) = G_CONSTANT i64 64
- %2:_(s8) = G_TRUNC %1(s32)
- G_MEMSET %0(p0), %2(s8), %3(s64), 1 :: (store (s8) into %ir.dst)
+ %1:_(i32) = G_CONSTANT i32 0
+ %3:_(i64) = G_CONSTANT i64 64
+ %2:_(i8) = G_TRUNC %1(i32)
+ G_MEMSET %0(p0), %2(i8), %3(i64), 1 :: (store (s8) into %ir.dst)
RET_ReallyLR
...
@@ -160,9 +160,9 @@ body: |
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
- %1:_(s8) = G_CONSTANT i8 64
- %2:_(s64) = G_CONSTANT i64 16
- G_MEMSET %0(p0), %1(s8), %2(s64), 1 :: (store (s8) into %ir.dst)
+ %1:_(i8) = G_CONSTANT i8 64
+ %2:_(i64) = G_CONSTANT i64 16
+ G_MEMSET %0(p0), %1(i8), %2(i64), 1 :: (store (s8) into %ir.dst)
RET_ReallyLR
...
@@ -178,9 +178,9 @@ body: |
; CHECK: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[TRUNC]](s8)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[TRUNC]](i8)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 72340172838076673
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MUL]](i64), [[MUL]](i64)
@@ -196,10 +196,10 @@ body: |
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD2]](p0) :: (store (<2 x i64>) into %ir.dst + 44, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
- %1:_(s32) = COPY $w1
- %3:_(s64) = G_CONSTANT i64 60
- %2:_(s8) = G_TRUNC %1(s32)
- G_MEMSET %0(p0), %2(s8), %3(s64), 1 :: (store (s8) into %ir.dst)
+ %1:_(i32) = COPY $w1
+ %3:_(i64) = G_CONSTANT i64 60
+ %2:_(i8) = G_TRUNC %1(i32)
+ G_MEMSET %0(p0), %2(i8), %3(i64), 1 :: (store (s8) into %ir.dst)
RET_ReallyLR
...
@@ -224,9 +224,9 @@ body: |
; CHECK-NEXT: G_STORE [[C1]](i16), [[PTR_ADD]](p0) :: (store (i16) into %ir.dst + 16, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
- %1:_(s8) = G_CONSTANT i8 64
- %2:_(s64) = G_CONSTANT i64 18
- G_MEMSET %0(p0), %1(s8), %2(s64), 1 :: (store (s8) into %ir.dst)
+ %1:_(i8) = G_CONSTANT i8 64
+ %2:_(i64) = G_CONSTANT i64 18
+ G_MEMSET %0(p0), %1(i8), %2(i64), 1 :: (store (s8) into %ir.dst)
RET_ReallyLR
...
@@ -241,17 +241,17 @@ body: |
; CHECK: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[TRUNC]](s8)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[TRUNC]](i8)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 72340172838076673
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MUL]](i64), [[MUL]](i64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
- %1:_(s32) = COPY $w1
- %3:_(s64) = G_CONSTANT i64 16
- %2:_(s8) = G_TRUNC %1(s32)
- G_MEMSET %0(p0), %2(s8), %3(s64), 1 :: (store (s8) into %ir.dst)
+ %1:_(i32) = COPY $w1
+ %3:_(i64) = G_CONSTANT i64 16
+ %2:_(i8) = G_TRUNC %1(i32)
+ G_MEMSET %0(p0), %2(i8), %3(i64), 1 :: (store (s8) into %ir.dst)
RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
index b10e273eb265b..de8beb9a01edf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
@@ -53,8 +53,8 @@ body: |
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
- %2:_(s64) = G_CONSTANT i64 32
- G_MEMCPY %0(p0), %1(p0), %2(s64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
+ %2:_(i64) = G_CONSTANT i64 32
+ G_MEMCPY %0(p0), %1(p0), %2(i64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
RET_ReallyLR
...
@@ -76,13 +76,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[C]](s64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[C]](i64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
- %2:_(s64) = G_CONSTANT i64 36
- G_MEMCPY %0(p0), %1(p0), %2(s64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
+ %2:_(i64) = G_CONSTANT i64 36
+ G_MEMCPY %0(p0), %1(p0), %2(i64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
RET_ReallyLR
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
index 1d99befe302af..f5271f2d259ce 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
@@ -56,7 +56,7 @@ body: |
; CHECK-NEXT: $q0 = COPY [[DEF]](<2 x i64>)
; CHECK-NEXT: $q1 = COPY [[DEF]](<2 x i64>)
%0:_(<4 x i64>) = G_IMPLICIT_DEF
- %1:_(<2 x s64> ), %2:_(<2 x i64>) = G_UNMERGE_VALUES %0
+ %1:_(<2 x i64> ), %2:_(<2 x i64>) = G_UNMERGE_VALUES %0
$q0 = COPY %1
$q1 = COPY %2
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
index 31e259ca940f0..fc954bdc129c2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
@@ -259,7 +259,7 @@ body: |
%2:gpr(i64) = G_SHL %0, %1(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
- %5:fpr(s128) = G_LOAD %4(p0) :: (load (s128) from %ir.addr)
+ %5:fpr(i128) = G_LOAD %4(p0) :: (load (s128) from %ir.addr)
RET_ReallyLR implicit %5
...
@@ -762,7 +762,7 @@ body: |
%2:gpr(i64) = G_SHL %0, %1(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
- %20:fpr(s128) = G_LOAD %4(p0) :: (load (s128) from %ir.addr)
+ %20:fpr(i128) = G_LOAD %4(p0) :: (load (s128) from %ir.addr)
%6:gpr(i64) = G_ADD %2, %1
%200:fpr(i64) = G_TRUNC %20
%2000:gpr(i64) = COPY %200
@@ -917,8 +917,8 @@ body: |
%0:gpr(p0) = COPY $x0
%1:gpr(i64) = COPY $x1
%2:gpr(p0) = G_PTR_ADD %0, %1
- %4:fpr(s16) = G_LOAD %2(p0) :: (load (s16) from %ir.addr)
- $h2 = COPY %4(s16)
+ %4:fpr(f16) = G_LOAD %2(p0) :: (load (s16) from %ir.addr)
+ $h2 = COPY %4(f16)
RET_ReallyLR implicit $h2
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-propagate-debug-loc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-propagate-debug-loc.mir
index 903bf27cef105..6ced34daed680 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-propagate-debug-loc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-propagate-debug-loc.mir
@@ -75,7 +75,7 @@ body: |
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 3
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @C, debug-location !DILocation(line: 0, scope: !18)
; CHECK-NEXT: [[ADD_LOW:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP]](p0), target-flags(aarch64-pageoff, aarch64-nc) @C, debug-location !DILocation(line: 0, scope: !18)
; CHECK-NEXT: [[ADRP1:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @B, debug-location !DILocation(line: 0, scope: !14)
@@ -83,12 +83,12 @@ body: |
; CHECK-NEXT: [[ADRP2:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @A, debug-location !DILocation(line: 0, scope: !11)
; CHECK-NEXT: [[ADD_LOW2:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP2]](p0), target-flags(aarch64-pageoff, aarch64-nc) @A, debug-location !DILocation(line: 0, scope: !11)
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:gpr(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY [[C1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:gpr(s32) = G_XOR [[COPY]], [[C2]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[XOR]](s32)
- ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.2
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(i32) = COPY [[C1]](i32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:gpr(i32) = G_XOR [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(i1) = G_TRUNC [[XOR]](i32)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC]](i1), %bb.2
; CHECK-NEXT: G_BR %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -96,19 +96,19 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ADRP3:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @A, debug-location !10
; CHECK-NEXT: [[ADD_LOW3:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP3]](p0), target-flags(aarch64-pageoff, aarch64-nc) @A, debug-location !10
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[ADD_LOW3]](p0), debug-location !10 :: (dereferenceable load (s32))
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(i32) = G_LOAD [[ADD_LOW3]](p0), debug-location !10 :: (dereferenceable load (i32))
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:gpr(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: G_STORE [[LOAD]](s32), [[FRAME_INDEX1]](p0) :: (volatile store (s32) into %ir.1)
+ ; CHECK-NEXT: G_STORE [[LOAD]](i32), [[FRAME_INDEX1]](p0) :: (volatile store (i32) into %ir.1)
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:gpr(s32) = G_XOR [[C3]], [[C4]]
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:gpr(s1) = G_TRUNC [[XOR1]](s32)
- ; CHECK-NEXT: G_BRCOND [[TRUNC1]](s1), %bb.4
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:gpr(i32) = G_XOR [[C3]], [[C4]]
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:gpr(i1) = G_TRUNC [[XOR1]](i32)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC1]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
@@ -116,11 +116,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ADRP4:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @B, debug-location !DILocation(line: 0, scope: !14)
; CHECK-NEXT: [[ADD_LOW4:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP4]](p0), target-flags(aarch64-pageoff, aarch64-nc) @B, debug-location !DILocation(line: 0, scope: !14)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:gpr(s32) = G_LOAD [[ADD_LOW4]](p0), debug-location !13 :: (dereferenceable load (s32))
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:gpr(i32) = G_LOAD [[ADD_LOW4]](p0), debug-location !13 :: (dereferenceable load (i32))
; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:gpr(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: G_STORE [[LOAD1]](s32), [[FRAME_INDEX2]](p0) :: (volatile store (s32) into %ir.1)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:gpr(s32) = G_LOAD [[ADD_LOW4]](p0), debug-location !16 :: (dereferenceable load (s32))
- ; CHECK-NEXT: G_STORE [[LOAD2]](s32), [[FRAME_INDEX2]](p0) :: (volatile store (s32) into %ir.1)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](i32), [[FRAME_INDEX2]](p0) :: (volatile store (i32) into %ir.1)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:gpr(i32) = G_LOAD [[ADD_LOW4]](p0), debug-location !16 :: (dereferenceable load (i32))
+ ; CHECK-NEXT: G_STORE [[LOAD2]](i32), [[FRAME_INDEX2]](p0) :: (volatile store (i32) into %ir.1)
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4:
@@ -128,69 +128,69 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ADRP5:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @C, debug-location !17
; CHECK-NEXT: [[ADD_LOW5:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP5]](p0), target-flags(aarch64-pageoff, aarch64-nc) @C, debug-location !17
- ; CHECK-NEXT: [[C5:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3, debug-location !17
- ; CHECK-NEXT: G_STORE [[C5]](s32), [[ADD_LOW5]](p0), debug-location !17 :: (store (s32) into @C)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 3, debug-location !17
+ ; CHECK-NEXT: G_STORE [[C5]](i32), [[ADD_LOW5]](p0), debug-location !17 :: (store (i32) into @C)
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5:
- ; CHECK-NEXT: [[C6:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: $w0 = COPY [[C6]](s32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $w0 = COPY [[C6]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
bb.1:
successors: %bb.2(0x40000000), %bb.3(0x40000000)
- %2:gpr(s32) = G_CONSTANT i32 3
+ %2:gpr(i32) = G_CONSTANT i32 3
%24:gpr64(p0) = ADRP target-flags(aarch64-page) @C, debug-location !DILocation(line: 0, scope: !18)
%3:gpr(p0) = G_ADD_LOW %24(p0), target-flags(aarch64-pageoff, aarch64-nc) @C, debug-location !DILocation(line: 0, scope: !18)
%23:gpr64(p0) = ADRP target-flags(aarch64-page) @B, debug-location !DILocation(line: 0, scope: !14)
%5:gpr(p0) = G_ADD_LOW %23(p0), target-flags(aarch64-pageoff, aarch64-nc) @B, debug-location !DILocation(line: 0, scope: !14)
%22:gpr64(p0) = ADRP target-flags(aarch64-page) @A, debug-location !DILocation(line: 0, scope: !11)
%8:gpr(p0) = G_ADD_LOW %22(p0), target-flags(aarch64-pageoff, aarch64-nc) @A, debug-location !DILocation(line: 0, scope: !11)
- %9:gpr(s32) = G_CONSTANT i32 0
+ %9:gpr(i32) = G_CONSTANT i32 0
%0:gpr(p0) = G_FRAME_INDEX %stack.0
- %18:gpr(s32) = COPY %9(s32)
- %19:gpr(s32) = G_CONSTANT i32 1
- %20:gpr(s32) = G_XOR %18, %19
- %11:gpr(s1) = G_TRUNC %20(s32)
- G_BRCOND %11(s1), %bb.3
+ %18:gpr(i32) = COPY %9(i32)
+ %19:gpr(i32) = G_CONSTANT i32 1
+ %20:gpr(i32) = G_XOR %18, %19
+ %11:gpr(i1) = G_TRUNC %20(i32)
+ G_BRCOND %11(i1), %bb.3
G_BR %bb.2
bb.2:
successors: %bb.6(0x80000000)
- %7:gpr(s32) = G_LOAD %8(p0), debug-location !10 :: (dereferenceable load (s32))
- G_STORE %7(s32), %0(p0) :: (volatile store (s32) into %ir.1)
+ %7:gpr(i32) = G_LOAD %8(p0), debug-location !10 :: (dereferenceable load (i32))
+ G_STORE %7(i32), %0(p0) :: (volatile store (i32) into %ir.1)
G_BR %bb.6
bb.3:
successors: %bb.4(0x40000000), %bb.5(0x40000000)
- %14:gpr(s32) = G_CONSTANT i32 0
- %15:gpr(s32) = G_CONSTANT i32 1
- %16:gpr(s32) = G_XOR %14, %15
- %13:gpr(s1) = G_TRUNC %16(s32)
- G_BRCOND %13(s1), %bb.5
+ %14:gpr(i32) = G_CONSTANT i32 0
+ %15:gpr(i32) = G_CONSTANT i32 1
+ %16:gpr(i32) = G_XOR %14, %15
+ %13:gpr(i1) = G_TRUNC %16(i32)
+ G_BRCOND %13(i1), %bb.5
G_BR %bb.4
bb.4:
successors: %bb.6(0x80000000)
- %4:gpr(s32) = G_LOAD %5(p0), debug-location !13 :: (dereferenceable load (s32))
- G_STORE %4(s32), %0(p0) :: (volatile store (s32) into %ir.1)
- %6:gpr(s32) = G_LOAD %5(p0), debug-location !16 :: (dereferenceable load (s32))
- G_STORE %6(s32), %0(p0) :: (volatile store (s32) into %ir.1)
+ %4:gpr(i32) = G_LOAD %5(p0), debug-location !13 :: (dereferenceable load (i32))
+ G_STORE %4(i32), %0(p0) :: (volatile store (i32) into %ir.1)
+ %6:gpr(i32) = G_LOAD %5(p0), debug-location !16 :: (dereferenceable load (i32))
+ G_STORE %6(i32), %0(p0) :: (volatile store (i32) into %ir.1)
G_BR %bb.6
bb.5:
successors: %bb.6(0x80000000)
- G_STORE %2(s32), %3(p0), debug-location !17 :: (store (s32) into @C)
+ G_STORE %2(i32), %3(p0), debug-location !17 :: (store (i32) into @C)
G_BR %bb.6
bb.6:
- $w0 = COPY %9(s32)
+ $w0 = COPY %9(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir b/llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir
index a110956ade319..9fb9b8423ec37 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir
@@ -68,10 +68,10 @@ regBankSelected: true
body: |
bb.0:
; CHECK-LABEL: name: local_use
- ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
- %0:gpr(s32) = G_CONSTANT i32 1
- %1:gpr(s32) = G_ADD %0, %0
+ ; CHECK: [[C:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(i32) = G_ADD [[C]], [[C]]
+ %0:gpr(i32) = G_CONSTANT i32 1
+ %1:gpr(i32) = G_ADD %0, %0
...
---
@@ -83,12 +83,12 @@ body: |
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(i32) = G_ADD [[C]], [[C]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[C1]], [[ADD]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(i32) = G_ADD [[C1]], [[ADD]]
; Existing registers should be left untouched
; The newly created reg should be on the same regbank/regclass as its origin.
@@ -96,11 +96,11 @@ body: |
bb.0:
successors: %bb.1
- %0:gpr(s32) = G_CONSTANT i32 1
- %1:gpr(s32) = G_ADD %0, %0
+ %0:gpr(i32) = G_CONSTANT i32 1
+ %1:gpr(i32) = G_ADD %0, %0
bb.1:
- %2:gpr(s32) = G_ADD %0, %1
+ %2:gpr(i32) = G_ADD %0, %1
...
---
@@ -112,12 +112,12 @@ body: |
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(i32) = G_ADD [[C]], [[C]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[C1]], [[C1]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(i32) = G_ADD [[C1]], [[C1]]
; Existing registers should be left untouched
; The newly created reg should be on the same regbank/regclass as its origin.
@@ -125,11 +125,11 @@ body: |
bb.0:
successors: %bb.1
- %0:gpr(s32) = G_CONSTANT i32 1
- %1:gpr(s32) = G_ADD %0, %0
+ %0:gpr(i32) = G_CONSTANT i32 1
+ %1:gpr(i32) = G_ADD %0, %0
bb.1:
- %2:gpr(s32) = G_ADD %0, %0
+ %2:gpr(i32) = G_ADD %0, %0
...
---
@@ -142,17 +142,17 @@ body: |
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(i32) = G_ADD [[C]], [[C]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr(s32) = PHI [[C1]](s32), %bb.1
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[PHI]]
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr(i32) = PHI [[C1]](i32), %bb.1
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(i32) = G_ADD [[PHI]], [[PHI]]
; Existing registers should be left untouched
; The newly created reg should be on the same regbank/regclass as its origin.
@@ -160,15 +160,15 @@ body: |
bb.0:
successors: %bb.1
- %0:gpr(s32) = G_CONSTANT i32 1
- %1:gpr(s32) = G_ADD %0, %0
+ %0:gpr(i32) = G_CONSTANT i32 1
+ %1:gpr(i32) = G_ADD %0, %0
bb.1:
successors: %bb.2
bb.2:
- %3:gpr(s32) = PHI %0(s32), %bb.1
- %2:gpr(s32) = G_ADD %3, %3
+ %3:gpr(i32) = PHI %0(i32), %bb.1
+ %2:gpr(i32) = G_ADD %3, %3
...
---
@@ -181,18 +181,18 @@ body: |
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(i32) = G_ADD [[C]], [[C]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr(s32) = PHI [[C1]](s32), %bb.1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[C2]]
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr(i32) = PHI [[C1]](i32), %bb.1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(i32) = G_ADD [[PHI]], [[C2]]
; Existing registers should be left untouched
; The newly created reg should be on the same regbank/regclass as its origin.
@@ -200,15 +200,15 @@ body: |
bb.0:
successors: %bb.1
- %0:gpr(s32) = G_CONSTANT i32 1
- %1:gpr(s32) = G_ADD %0, %0
+ %0:gpr(i32) = G_CONSTANT i32 1
+ %1:gpr(i32) = G_ADD %0, %0
bb.1:
successors: %bb.2
bb.2:
- %3:gpr(s32) = PHI %0(s32), %bb.1
- %2:gpr(s32) = G_ADD %3, %0
+ %3:gpr(i32) = PHI %0(i32), %bb.1
+ %2:gpr(i32) = G_ADD %3, %0
...
---
@@ -221,18 +221,18 @@ body: |
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:gpr(s32) = G_FRAME_INDEX 1
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[FRAME_INDEX]], [[FRAME_INDEX]]
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:gpr(i32) = G_FRAME_INDEX 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(i32) = G_ADD [[FRAME_INDEX]], [[FRAME_INDEX]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:gpr(s32) = G_FRAME_INDEX 1
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:gpr(i32) = G_FRAME_INDEX 1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr(s32) = PHI [[FRAME_INDEX1]](s32), %bb.1
- ; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:gpr(s32) = G_FRAME_INDEX 1
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[FRAME_INDEX2]]
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr(i32) = PHI [[FRAME_INDEX1]](i32), %bb.1
+ ; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:gpr(i32) = G_FRAME_INDEX 1
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(i32) = G_ADD [[PHI]], [[FRAME_INDEX2]]
; Existing registers should be left untouched
; The newly created reg should be on the same regbank/regclass as its origin.
@@ -240,15 +240,15 @@ body: |
bb.0:
successors: %bb.1
- %0:gpr(s32) = G_FRAME_INDEX 1
- %1:gpr(s32) = G_ADD %0, %0
+ %0:gpr(i32) = G_FRAME_INDEX 1
+ %1:gpr(i32) = G_ADD %0, %0
bb.1:
successors: %bb.2
bb.2:
- %3:gpr(s32) = PHI %0(s32), %bb.1
- %2:gpr(s32) = G_ADD %3, %0
+ %3:gpr(i32) = PHI %0(i32), %bb.1
+ %2:gpr(i32) = G_ADD %3, %0
...
---
@@ -261,18 +261,18 @@ body: |
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:fpr(s32) = G_FADD [[C]], [[C]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:fpr(f32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:fpr(f32) = G_FADD [[C]], [[C]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C1:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:fpr(f32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:fpr(s32) = PHI [[C1]](s32), %bb.1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
- ; CHECK-NEXT: [[FADD1:%[0-9]+]]:fpr(s32) = G_FADD [[PHI]], [[C2]]
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:fpr(f32) = PHI [[C1]](f32), %bb.1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:fpr(f32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK-NEXT: [[FADD1:%[0-9]+]]:fpr(f32) = G_FADD [[PHI]], [[C2]]
; Existing registers should be left untouched
; The newly created reg should be on the same regbank/regclass as its origin.
@@ -280,15 +280,15 @@ body: |
bb.0:
successors: %bb.1
- %0:fpr(s32) = G_FCONSTANT float 1.0
- %1:fpr(s32) = G_FADD %0, %0
+ %0:fpr(f32) = G_FCONSTANT float 1.0
+ %1:fpr(f32) = G_FADD %0, %0
bb.1:
successors: %bb.2
bb.2:
- %3:fpr(s32) = PHI %0(s32), %bb.1
- %2:fpr(s32) = G_FADD %3, %0
+ %3:fpr(f32) = PHI %0(f32), %bb.1
+ %2:fpr(f32) = G_FADD %3, %0
...
---
@@ -303,15 +303,15 @@ body: |
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:fpr(s32) = G_FADD [[C]], [[C]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:fpr(f32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:fpr(f32) = G_FADD [[C]], [[C]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:fpr(s32) = PHI [[FADD]](s32), %bb.0, %4(s32), %bb.1
- ; CHECK-NEXT: [[FADD1:%[0-9]+]]:fpr(s32) = G_FADD [[PHI]], [[FADD]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:fpr(f32) = PHI [[FADD]](f32), %bb.0, %4(f32), %bb.1
+ ; CHECK-NEXT: [[FADD1:%[0-9]+]]:fpr(f32) = G_FADD [[PHI]], [[FADD]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:fpr(f32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: G_BR %bb.1
; Existing registers should be left untouched
@@ -320,14 +320,14 @@ body: |
bb.0:
successors: %bb.1
- %0:fpr(s32) = G_FCONSTANT float 1.0
- %1:fpr(s32) = G_FADD %0, %0
+ %0:fpr(f32) = G_FCONSTANT float 1.0
+ %1:fpr(f32) = G_FADD %0, %0
bb.1:
successors: %bb.1
- %3:fpr(s32) = PHI %1(s32), %bb.0, %0(s32), %bb.1
- %2:fpr(s32) = G_FADD %3, %1
+ %3:fpr(f32) = PHI %1(f32), %bb.0, %0(f32), %bb.1
+ %2:fpr(f32) = G_FADD %3, %1
G_BR %bb.1
...
@@ -343,15 +343,15 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $s0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
- ; CHECK-NEXT: [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(f32) = COPY $s0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:fpr(f32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: EH_LABEL 1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:fpr(s32) = G_FADD [[COPY]], [[C1]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:fpr(f32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:fpr(f32) = G_FADD [[COPY]], [[C1]]
; CHECK-NEXT: G_BR %bb.1
; Existing registers should be left untouched
@@ -361,14 +361,14 @@ body: |
liveins: $s0
successors: %bb.1
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FCONSTANT float 1.0
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FCONSTANT float 1.0
bb.1:
successors: %bb.1
EH_LABEL 1
- %2:fpr(s32) = G_FADD %0, %1
+ %2:fpr(f32) = G_FADD %0, %1
G_BR %bb.1
...
---
@@ -381,61 +381,61 @@ body: |
; CHECK: bb.0.entry:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 2
; CHECK-NEXT: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 3
; CHECK-NEXT: [[GV1:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3
- ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[GV2]](p0) :: (load (s32) from @var1)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(eq), [[LOAD]](s32), [[C3]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(i32) = G_LOAD [[GV2]](p0) :: (load (i32) from @var1)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(i32) = G_ICMP intpred(eq), [[LOAD]](i32), [[C3]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(i1) = G_TRUNC [[ICMP]](i32)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC]](i1), %bb.1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.if.then:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV3:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
- ; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2
- ; CHECK-NEXT: G_STORE [[C4]](s32), [[GV3]](p0) :: (store (s32) into @var2)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: G_STORE [[C4]](i32), [[GV3]](p0) :: (store (i32) into @var2)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 3
; CHECK-NEXT: [[GV4:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: G_STORE [[C5]](s32), [[GV4]](p0) :: (store (s32) into @var1)
+ ; CHECK-NEXT: G_STORE [[C5]](i32), [[GV4]](p0) :: (store (i32) into @var1)
; CHECK-NEXT: [[GV5:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3
- ; CHECK-NEXT: G_STORE [[C4]](s32), [[GV5]](p0) :: (store (s32) into @var3)
- ; CHECK-NEXT: G_STORE [[C5]](s32), [[GV4]](p0) :: (store (s32) into @var1)
+ ; CHECK-NEXT: G_STORE [[C4]](i32), [[GV5]](p0) :: (store (i32) into @var3)
+ ; CHECK-NEXT: G_STORE [[C5]](i32), [[GV4]](p0) :: (store (i32) into @var1)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.end:
- ; CHECK-NEXT: [[C6:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: $w0 = COPY [[C6]](s32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $w0 = COPY [[C6]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
; Some of these instructions are dead. We're checking that the other instructions are
; sunk immediately before their first user in the if.then block or as close as possible.
bb.1.entry:
%1:gpr(p0) = G_GLOBAL_VALUE @var1
- %2:gpr(s32) = G_CONSTANT i32 1
- %4:gpr(s32) = G_CONSTANT i32 2
+ %2:gpr(i32) = G_CONSTANT i32 1
+ %4:gpr(i32) = G_CONSTANT i32 2
%5:gpr(p0) = G_GLOBAL_VALUE @var2
- %6:gpr(s32) = G_CONSTANT i32 3
+ %6:gpr(i32) = G_CONSTANT i32 3
%7:gpr(p0) = G_GLOBAL_VALUE @var3
- %8:gpr(s32) = G_CONSTANT i32 0
- %0:gpr(s32) = G_LOAD %1(p0) :: (load (s32) from @var1)
- %9:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
- %3:gpr(s1) = G_TRUNC %9(s32)
- G_BRCOND %3(s1), %bb.2
+ %8:gpr(i32) = G_CONSTANT i32 0
+ %0:gpr(i32) = G_LOAD %1(p0) :: (load (i32) from @var1)
+ %9:gpr(i32) = G_ICMP intpred(eq), %0(i32), %2
+ %3:gpr(i1) = G_TRUNC %9(i32)
+ G_BRCOND %3(i1), %bb.2
G_BR %bb.3
bb.2.if.then:
- G_STORE %4(s32), %5(p0) :: (store (s32) into @var2)
- G_STORE %6(s32), %1(p0) :: (store (s32) into @var1)
- G_STORE %4(s32), %7(p0) :: (store (s32) into @var3)
- G_STORE %6(s32), %1(p0) :: (store (s32) into @var1)
+ G_STORE %4(i32), %5(p0) :: (store (i32) into @var2)
+ G_STORE %6(i32), %1(p0) :: (store (i32) into @var1)
+ G_STORE %4(i32), %7(p0) :: (store (i32) into @var3)
+ G_STORE %6(i32), %1(p0) :: (store (i32) into @var1)
bb.3.if.end:
- $w0 = COPY %8(s32)
+ $w0 = COPY %8(i32)
RET_ReallyLR implicit $w0
...
@@ -451,18 +451,18 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var1
; CHECK-NEXT: %addlow1:gpr(p0) = G_ADD_LOW [[ADRP]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var1
- ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 2
; CHECK-NEXT: [[ADRP1:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var2
; CHECK-NEXT: %addlow2:gpr(p0) = G_ADD_LOW [[ADRP1]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var2
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 3
; CHECK-NEXT: [[ADRP2:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var3
; CHECK-NEXT: %addlow3:gpr(p0) = G_ADD_LOW [[ADRP2]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var3
- ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[ADRP]](p0) :: (load (s32) from @var1)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(eq), [[LOAD]](s32), [[C3]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(i32) = G_LOAD [[ADRP]](p0) :: (load (i32) from @var1)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(i32) = G_ICMP intpred(eq), [[LOAD]](i32), [[C3]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(i1) = G_TRUNC [[ICMP]](i32)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC]](i1), %bb.1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.if.then:
@@ -470,48 +470,48 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ADRP3:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var2
; CHECK-NEXT: [[ADD_LOW:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP3]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var2
- ; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2
- ; CHECK-NEXT: G_STORE [[C4]](s32), [[ADD_LOW]](p0) :: (store (s32) into @var2)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: G_STORE [[C4]](i32), [[ADD_LOW]](p0) :: (store (i32) into @var2)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 3
; CHECK-NEXT: [[ADRP4:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var1
; CHECK-NEXT: [[ADD_LOW1:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP4]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var1
- ; CHECK-NEXT: G_STORE [[C5]](s32), [[ADD_LOW1]](p0) :: (store (s32) into @var1)
+ ; CHECK-NEXT: G_STORE [[C5]](i32), [[ADD_LOW1]](p0) :: (store (i32) into @var1)
; CHECK-NEXT: [[ADRP5:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var3
; CHECK-NEXT: [[ADD_LOW2:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP5]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var3
- ; CHECK-NEXT: G_STORE [[C4]](s32), [[ADD_LOW2]](p0) :: (store (s32) into @var3)
- ; CHECK-NEXT: G_STORE [[C5]](s32), [[ADD_LOW1]](p0) :: (store (s32) into @var1)
+ ; CHECK-NEXT: G_STORE [[C4]](i32), [[ADD_LOW2]](p0) :: (store (i32) into @var3)
+ ; CHECK-NEXT: G_STORE [[C5]](i32), [[ADD_LOW1]](p0) :: (store (i32) into @var1)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.end:
- ; CHECK-NEXT: [[C6:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: $w0 = COPY [[C6]](s32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $w0 = COPY [[C6]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
; Some of these instructions are dead.
bb.1.entry:
%1:gpr64(p0) = ADRP target-flags(aarch64-page) @var1
%addlow1:gpr(p0) = G_ADD_LOW %1(p0), target-flags(aarch64-pageoff, aarch64-nc) @var1
- %2:gpr(s32) = G_CONSTANT i32 1
- %4:gpr(s32) = G_CONSTANT i32 2
+ %2:gpr(i32) = G_CONSTANT i32 1
+ %4:gpr(i32) = G_CONSTANT i32 2
%5:gpr64(p0) = ADRP target-flags(aarch64-page) @var2
%addlow2:gpr(p0) = G_ADD_LOW %5(p0), target-flags(aarch64-pageoff, aarch64-nc) @var2
- %6:gpr(s32) = G_CONSTANT i32 3
+ %6:gpr(i32) = G_CONSTANT i32 3
%7:gpr64(p0) = ADRP target-flags(aarch64-page) @var3
%addlow3:gpr(p0) = G_ADD_LOW %7(p0), target-flags(aarch64-pageoff, aarch64-nc) @var3
- %8:gpr(s32) = G_CONSTANT i32 0
- %0:gpr(s32) = G_LOAD %1(p0) :: (load (s32) from @var1)
- %9:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
- %3:gpr(s1) = G_TRUNC %9(s32)
- G_BRCOND %3(s1), %bb.2
+ %8:gpr(i32) = G_CONSTANT i32 0
+ %0:gpr(i32) = G_LOAD %1(p0) :: (load (i32) from @var1)
+ %9:gpr(i32) = G_ICMP intpred(eq), %0(i32), %2
+ %3:gpr(i1) = G_TRUNC %9(i32)
+ G_BRCOND %3(i1), %bb.2
G_BR %bb.3
bb.2.if.then:
- G_STORE %4(s32), %addlow2(p0) :: (store (s32) into @var2)
- G_STORE %6(s32), %addlow1(p0) :: (store (s32) into @var1)
- G_STORE %4(s32), %addlow3(p0) :: (store (s32) into @var3)
- G_STORE %6(s32), %addlow1(p0) :: (store (s32) into @var1)
+ G_STORE %4(i32), %addlow2(p0) :: (store (i32) into @var2)
+ G_STORE %6(i32), %addlow1(p0) :: (store (i32) into @var1)
+ G_STORE %4(i32), %addlow3(p0) :: (store (i32) into @var3)
+ G_STORE %6(i32), %addlow1(p0) :: (store (i32) into @var1)
bb.3.if.end:
- $w0 = COPY %8(s32)
+ $w0 = COPY %8(i32)
RET_ReallyLR implicit $w0
...
@@ -527,49 +527,49 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: liveins: $w0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(i32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:gpr(p0) = G_INTTOPTR [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 128
- ; CHECK-NEXT: [[INTTOPTR1:%[0-9]+]]:gpr(p0) = G_INTTOPTR [[C1]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C2]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:gpr(p0) = G_INTTOPTR [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(i64) = G_CONSTANT i64 128
+ ; CHECK-NEXT: [[INTTOPTR1:%[0-9]+]]:gpr(p0) = G_INTTOPTR [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(i32) = G_ICMP intpred(eq), [[COPY]](i32), [[C2]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(i1) = G_TRUNC [[ICMP]](i32)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC]](i1), %bb.1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[COPY]], [[COPY]]
- ; CHECK-NEXT: G_STORE [[ADD]](s32), [[COPY1]](p0) :: (store (s32))
- ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 128
- ; CHECK-NEXT: [[INTTOPTR2:%[0-9]+]]:gpr(p0) = G_INTTOPTR [[C3]](s64)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(i32) = G_ADD [[COPY]], [[COPY]]
+ ; CHECK-NEXT: G_STORE [[ADD]](i32), [[COPY1]](p0) :: (store (i32))
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(i64) = G_CONSTANT i64 128
+ ; CHECK-NEXT: [[INTTOPTR2:%[0-9]+]]:gpr(p0) = G_INTTOPTR [[C3]](i64)
; CHECK-NEXT: $x0 = COPY [[INTTOPTR2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
- ; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[INTTOPTR3:%[0-9]+]]:gpr(p0) = G_INTTOPTR [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[INTTOPTR3:%[0-9]+]]:gpr(p0) = G_INTTOPTR [[C4]](i64)
; CHECK-NEXT: $x0 = COPY [[INTTOPTR3]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
bb.1:
liveins: $w0, $x1
- %0:gpr(s32) = COPY $w0
+ %0:gpr(i32) = COPY $w0
%1:gpr(p0) = COPY $x1
- %2:gpr(s64) = G_CONSTANT i64 128
- %4:gpr(s32) = G_CONSTANT i32 0
- %7:gpr(s64) = G_CONSTANT i64 0
- %6:gpr(p0) = G_INTTOPTR %7(s64)
- %3:gpr(p0) = G_INTTOPTR %2(s64)
- %9:gpr(s32) = G_ICMP intpred(eq), %0(s32), %4
- %5:gpr(s1) = G_TRUNC %9(s32)
- G_BRCOND %5(s1), %bb.2
+ %2:gpr(i64) = G_CONSTANT i64 128
+ %4:gpr(i32) = G_CONSTANT i32 0
+ %7:gpr(i64) = G_CONSTANT i64 0
+ %6:gpr(p0) = G_INTTOPTR %7(i64)
+ %3:gpr(p0) = G_INTTOPTR %2(i64)
+ %9:gpr(i32) = G_ICMP intpred(eq), %0(i32), %4
+ %5:gpr(i1) = G_TRUNC %9(i32)
+ G_BRCOND %5(i1), %bb.2
G_BR %bb.3
bb.2:
- %8:gpr(s32) = G_ADD %0, %0
- G_STORE %8(s32), %1(p0) :: (store (s32))
+ %8:gpr(i32) = G_ADD %0, %0
+ G_STORE %8(i32), %1(p0) :: (store (i32))
$x0 = COPY %3(p0)
RET_ReallyLR implicit $x0
@@ -586,22 +586,22 @@ regBankSelected: true
body: |
bb.0:
; CHECK-LABEL: name: many_local_use_intra_block
- ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
- ; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
- ; CHECK-NEXT: [[ADD3:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
- ; CHECK-NEXT: [[ADD4:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2
- ; CHECK-NEXT: [[ADD5:%[0-9]+]]:gpr(s32) = G_ADD [[C1]], [[C1]]
- %0:gpr(s32) = G_CONSTANT i32 1
- %1:gpr(s32) = G_CONSTANT i32 2
- %2:gpr(s32) = G_ADD %0, %0
- %3:gpr(s32) = G_ADD %0, %0
- %4:gpr(s32) = G_ADD %0, %0
- %5:gpr(s32) = G_ADD %0, %0
- %6:gpr(s32) = G_ADD %0, %0
- %7:gpr(s32) = G_ADD %1, %1
+ ; CHECK: [[C:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(i32) = G_ADD [[C]], [[C]]
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(i32) = G_ADD [[C]], [[C]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr(i32) = G_ADD [[C]], [[C]]
+ ; CHECK-NEXT: [[ADD3:%[0-9]+]]:gpr(i32) = G_ADD [[C]], [[C]]
+ ; CHECK-NEXT: [[ADD4:%[0-9]+]]:gpr(i32) = G_ADD [[C]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[ADD5:%[0-9]+]]:gpr(i32) = G_ADD [[C1]], [[C1]]
+ %0:gpr(i32) = G_CONSTANT i32 1
+ %1:gpr(i32) = G_CONSTANT i32 2
+ %2:gpr(i32) = G_ADD %0, %0
+ %3:gpr(i32) = G_ADD %0, %0
+ %4:gpr(i32) = G_ADD %0, %0
+ %5:gpr(i32) = G_ADD %0, %0
+ %6:gpr(i32) = G_ADD %0, %0
+ %7:gpr(i32) = G_ADD %1, %1
...
---
@@ -614,40 +614,40 @@ body: |
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
- ; CHECK-NEXT: %cmp:gpr(s32) = G_ICMP intpred(eq), [[ADD]](s32), [[C]]
- ; CHECK-NEXT: %cond:gpr(s1) = G_TRUNC %cmp(s32)
- ; CHECK-NEXT: G_BRCOND %cond(s1), %bb.1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(i32) = G_ADD [[C]], [[C]]
+ ; CHECK-NEXT: %cmp:gpr(i32) = G_ICMP intpred(eq), [[ADD]](i32), [[C]]
+ ; CHECK-NEXT: %cond:gpr(i1) = G_TRUNC %cmp(i32)
+ ; CHECK-NEXT: G_BRCOND %cond(i1), %bb.1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr(s32) = G_PHI [[C1]](s32), %bb.1, [[C]](s32), %bb.0
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[PHI]]
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr(i32) = G_PHI [[C1]](i32), %bb.1, [[C]](i32), %bb.0
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(i32) = G_ADD [[PHI]], [[PHI]]
; Localize the 1 into bb.1, since the number of uses is under the threshold.
bb.0:
successors: %bb.1, %bb.2
- %0:gpr(s32) = G_CONSTANT i32 1
- %1:gpr(s32) = G_ADD %0, %0
- %cmp:gpr(s32) = G_ICMP intpred(eq), %1(s32), %0
- %cond:gpr(s1) = G_TRUNC %cmp(s32)
- G_BRCOND %cond(s1), %bb.1
+ %0:gpr(i32) = G_CONSTANT i32 1
+ %1:gpr(i32) = G_ADD %0, %0
+ %cmp:gpr(i32) = G_ICMP intpred(eq), %1(i32), %0
+ %cond:gpr(i1) = G_TRUNC %cmp(i32)
+ G_BRCOND %cond(i1), %bb.1
G_BR %bb.2
bb.1:
successors: %bb.2
bb.2:
- %3:gpr(s32) = G_PHI %0(s32), %bb.1, %0(s32), %bb.0
- %2:gpr(s32) = G_ADD %3, %3
+ %3:gpr(i32) = G_PHI %0(i32), %bb.1, %0(i32), %bb.0
+ %2:gpr(i32) = G_ADD %3, %3
...
---
name: non_local_phi_three_uses
@@ -659,36 +659,36 @@ body: |
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
- ; CHECK-NEXT: %cmp:gpr(s32) = G_ICMP intpred(eq), [[ADD]](s32), [[C]]
- ; CHECK-NEXT: %cond:gpr(s1) = G_TRUNC %cmp(s32)
- ; CHECK-NEXT: G_BRCOND %cond(s1), %bb.1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(i32) = G_ADD [[C]], [[C]]
+ ; CHECK-NEXT: %cmp:gpr(i32) = G_ICMP intpred(eq), [[ADD]](i32), [[C]]
+ ; CHECK-NEXT: %cond:gpr(i1) = G_TRUNC %cmp(i32)
+ ; CHECK-NEXT: G_BRCOND %cond(i1), %bb.1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr(s32) = G_PHI [[C]](s32), %bb.1, [[C]](s32), %bb.0, [[C]](s32), %bb.0, [[C]](s32), %bb.0
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[PHI]]
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr(i32) = G_PHI [[C]](i32), %bb.1, [[C]](i32), %bb.0, [[C]](i32), %bb.0, [[C]](i32), %bb.0
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(i32) = G_ADD [[PHI]], [[PHI]]
; Don't localize the 1 into bb.1, above the thresold of uses in the phi.
bb.0:
successors: %bb.1, %bb.2
- %0:gpr(s32) = G_CONSTANT i32 1
- %1:gpr(s32) = G_ADD %0, %0
- %cmp:gpr(s32) = G_ICMP intpred(eq), %1(s32), %0
- %cond:gpr(s1) = G_TRUNC %cmp(s32)
- G_BRCOND %cond(s1), %bb.1
+ %0:gpr(i32) = G_CONSTANT i32 1
+ %1:gpr(i32) = G_ADD %0, %0
+ %cmp:gpr(i32) = G_ICMP intpred(eq), %1(i32), %0
+ %cond:gpr(i1) = G_TRUNC %cmp(i32)
+ G_BRCOND %cond(i1), %bb.1
G_BR %bb.2
bb.1:
successors: %bb.2
bb.2:
- %3:gpr(s32) = G_PHI %0(s32), %bb.1, %0(s32), %bb.0, %0(s32), %bb.0, %0(s32), %bb.0
- %2:gpr(s32) = G_ADD %3, %3
+ %3:gpr(i32) = G_PHI %0(i32), %bb.1, %0(i32), %bb.0, %0(i32), %bb.0, %0(i32), %bb.0
+ %2:gpr(i32) = G_ADD %3, %3
...
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