[llvm] fold sgpr32 via vgpr16 (PR #215375)
Guo Chen via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 10 12:47:49 PDT 2026
https://github.com/broxigarchen created https://github.com/llvm/llvm-project/pull/215375
None
>From 6ec38274cac8455a590da4094a785d7889d9a9b3 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Mon, 10 Aug 2026 13:47:41 -0400
Subject: [PATCH] fold sgpr32 via vgpr16
---
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 36 ++
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll | 84 ++--
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll | 15 +-
.../inst-select-amdgcn.class.s16.mir | 3 +-
.../AMDGPU/GlobalISel/store-local.96.ll | 6 -
llvm/test/CodeGen/AMDGPU/add-debug.ll | 1 +
.../CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll | 24 +
.../CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll | 4 +-
.../CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll | 424 +++++++++---------
.../CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll | 130 ------
.../CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll | 260 +++++------
llvm/test/CodeGen/AMDGPU/true16-fold.mir | 62 +++
12 files changed, 497 insertions(+), 552 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 04a9ed487d655..f5ae6c676ea41 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -1508,6 +1508,42 @@ bool SIFoldOperandsImpl::foldOperand(
return true;
}
+ // Look through Lo16 Copy
+ // OpToFold: %0
+ // %1:vgpr32 = copy %0:sreg32/sregxx:sub_x
+ // %2:vgpr16 = copy %1.lo16:vgpr32 (UseMI)
+ // VALU %2:vgpr16 ...
+ // =>
+ // VALU %0:sreg32/sregxx:sub_x...
+ if (UseMI->isCopy() && OpToFold.isReg() &&
+ UseMI->getOperand(0).getReg().isVirtual() &&
+ TRI->isSGPRReg(*MRI, OpToFold.getReg()) &&
+ TII->getOpSize(*UseMI, 0) == 2 &&
+ UseMI->getOperand(1).getSubReg() == AMDGPU::lo16 &&
+ OpToFold.DefMI->implicit_operands().empty()) {
+
+ // Push Users of vgpr16 instead
+ SmallVector<MachineOperand *, 4> UsesToProcess(llvm::make_pointer_range(
+ MRI->use_nodbg_operands(UseMI->getOperand(0).getReg())));
+ for (auto *U : UsesToProcess) {
+ MachineInstr *NextMI = U->getParent();
+
+ const MCInstrDesc &UseDesc = NextMI->getDesc();
+ if (UseDesc.isVariadic() || U->isImplicit() ||
+ UseDesc.operands()[NextMI->getOperandNo(U)].RegClass == -1)
+ continue;
+
+ FoldableDef NextOpToFold(*OpToFold.OpToFold, OpToFold.DefRC,
+ U->getSubReg());
+ LLVM_DEBUG(dbgs() << "Folding " << *NextOpToFold.OpToFold << "\n across "
+ << *UseMI << "\n into " << *NextMI);
+
+ Changed |= tryAddToFoldList(FoldList, NextMI, NextMI->getOperandNo(U),
+ NextOpToFold);
+ }
+ return Changed;
+ }
+
unsigned UseOpc = UseMI->getOpcode();
if (UseOpc == AMDGPU::V_READFIRSTLANE_B32 ||
(UseOpc == AMDGPU::V_READLANE_B32 &&
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index 6844b698473c7..14294565c0f63 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -3028,28 +3028,16 @@ define amdgpu_ps i32 @s_fshl_i32(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt)
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-TRUE16-LABEL: s_fshl_i32:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_not_b32 s2, s2
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, s1, 1
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s2
-; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, v0, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX11-FAKE16-LABEL: s_fshl_i32:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s0, s1, 1
-; GFX11-FAKE16-NEXT: s_lshr_b32 s0, s0, 1
-; GFX11-FAKE16-NEXT: s_not_b32 s1, s2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s0, v0, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-FAKE16-NEXT: ; return to shader part epilog
+; GFX11-LABEL: s_fshl_i32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, 1
+; GFX11-NEXT: s_lshr_b32 s0, s0, 1
+; GFX11-NEXT: s_not_b32 s1, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_alignbit_b32 v0, s0, v0, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: ; return to shader part epilog
%result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 %amt)
ret i32 %result
}
@@ -3289,24 +3277,14 @@ define amdgpu_ps float @v_fshl_i32_svs(i32 inreg %lhs, i32 %rhs, i32 inreg %amt)
; GFX10-NEXT: v_alignbit_b32 v0, s0, v0, s1
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-TRUE16-LABEL: v_fshl_i32_svs:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_not_b32 s1, s1
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, v0, 1
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s1
-; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, v0, v1.l
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX11-FAKE16-LABEL: v_fshl_i32_svs:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s0, v0, 1
-; GFX11-FAKE16-NEXT: s_lshr_b32 s0, s0, 1
-; GFX11-FAKE16-NEXT: s_not_b32 s1, s1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s0, v0, s1
-; GFX11-FAKE16-NEXT: ; return to shader part epilog
+; GFX11-LABEL: v_fshl_i32_svs:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_alignbit_b32 v0, s0, v0, 1
+; GFX11-NEXT: s_lshr_b32 s0, s0, 1
+; GFX11-NEXT: s_not_b32 s1, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_alignbit_b32 v0, s0, v0, s1
+; GFX11-NEXT: ; return to shader part epilog
%result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 %amt)
%cast.result = bitcast i32 %result to float
ret float %cast.result
@@ -3351,24 +3329,14 @@ define amdgpu_ps float @v_fshl_i32_vss(i32 inreg %lhs, i32 inreg %rhs, i32 inreg
; GFX10-NEXT: v_alignbit_b32 v0, s0, v0, s1
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-TRUE16-LABEL: v_fshl_i32_vss:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_not_b32 s2, s2
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, s1, 1
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s2
-; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, v0, v1.l
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX11-FAKE16-LABEL: v_fshl_i32_vss:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s0, s1, 1
-; GFX11-FAKE16-NEXT: s_lshr_b32 s0, s0, 1
-; GFX11-FAKE16-NEXT: s_not_b32 s1, s2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s0, v0, s1
-; GFX11-FAKE16-NEXT: ; return to shader part epilog
+; GFX11-LABEL: v_fshl_i32_vss:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, 1
+; GFX11-NEXT: s_lshr_b32 s0, s0, 1
+; GFX11-NEXT: s_not_b32 s1, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_alignbit_b32 v0, s0, v0, s1
+; GFX11-NEXT: ; return to shader part epilog
%result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 %amt)
%cast.result = bitcast i32 %result to float
ret float %cast.result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index 11b62d825c965..ee863cc06eb6d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -3257,17 +3257,10 @@ define amdgpu_ps float @v_fshr_i32_svs(i32 inreg %lhs, i32 %rhs, i32 inreg %amt)
; GFX10-NEXT: v_alignbit_b32 v0, s0, v0, s1
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-TRUE16-LABEL: v_fshr_i32_svs:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_alignbit_b32 v0, s0, v0, v1.l
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
-;
-; GFX11-FAKE16-LABEL: v_fshr_i32_svs:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, s0, v0, s1
-; GFX11-FAKE16-NEXT: ; return to shader part epilog
+; GFX11-LABEL: v_fshr_i32_svs:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_alignbit_b32 v0, s0, v0, s1
+; GFX11-NEXT: ; return to shader part epilog
%result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)
%cast.result = bitcast i32 %result to float
ret float %cast.result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
index b0587821eb116..df9d756bdd0bc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
@@ -136,8 +136,7 @@ body: |
; GFX11-FOLD-TRUE16-NEXT: {{ $}}
; GFX11-FOLD-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX11-FOLD-TRUE16-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX11-FOLD-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
- ; GFX11-FOLD-TRUE16-NEXT: [[V_CMP_CLASS_F16_t16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_t16_e64 0, [[COPY]].lo16, 0, [[COPY2]].lo16, 0, implicit $exec
+ ; GFX11-FOLD-TRUE16-NEXT: [[V_CMP_CLASS_F16_t16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_t16_e64 0, [[COPY]].lo16, 0, [[COPY1]], 0, implicit $exec
; GFX11-FOLD-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_t16_e64_]]
;
; GFX11-FOLD-FAKE16-LABEL: name: class_f16_vcc_vs
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
index 3b6106b915e03..0ac3afd11133b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
@@ -60,7 +60,6 @@ define amdgpu_kernel void @store_lds_v3i32(ptr addrspace(3) %out, <3 x i32> %x)
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: ds_store_b96 v3, v[0:2]
; GFX11-NEXT: s_endpgm
-;
; GFX6-LABEL: store_lds_v3i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x4
@@ -261,7 +260,6 @@ define amdgpu_kernel void @store_lds_v3i32_align1(ptr addrspace(3) %out, <3 x i3
; GFX11-NEXT: ds_store_b8_d16_hi v6, v3 offset:10
; GFX11-NEXT: ds_store_b8_d16_hi v6, v4 offset:11
; GFX11-NEXT: s_endpgm
-;
; GFX6-LABEL: store_lds_v3i32_align1:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x4
@@ -426,7 +424,6 @@ define amdgpu_kernel void @store_lds_v3i32_align2(ptr addrspace(3) %out, <3 x i3
; GFX11-NEXT: ds_store_b16 v1, v4 offset:8
; GFX11-NEXT: ds_store_b16 v1, v6 offset:10
; GFX11-NEXT: s_endpgm
-;
; GFX6-LABEL: store_lds_v3i32_align2:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x4
@@ -522,7 +519,6 @@ define amdgpu_kernel void @store_lds_v3i32_align4(ptr addrspace(3) %out, <3 x i3
; GFX11-NEXT: ds_store_2addr_b32 v1, v0, v2 offset1:1
; GFX11-NEXT: ds_store_b32 v1, v3 offset:8
; GFX11-NEXT: s_endpgm
-;
; GFX6-LABEL: store_lds_v3i32_align4:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dword s6, s[4:5], 0x0
@@ -597,7 +593,6 @@ define amdgpu_kernel void @store_lds_v3i32_align8(ptr addrspace(3) %out, <3 x i3
; GFX11-NEXT: ds_store_2addr_b32 v1, v0, v2 offset1:1
; GFX11-NEXT: ds_store_b32 v1, v3 offset:8
; GFX11-NEXT: s_endpgm
-;
; GFX6-LABEL: store_lds_v3i32_align8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x4
@@ -671,7 +666,6 @@ define amdgpu_kernel void @store_lds_v3i32_align16(ptr addrspace(3) %out, <3 x i
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: ds_store_b96 v3, v[0:2]
; GFX11-NEXT: s_endpgm
-;
; GFX6-LABEL: store_lds_v3i32_align16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x4
diff --git a/llvm/test/CodeGen/AMDGPU/add-debug.ll b/llvm/test/CodeGen/AMDGPU/add-debug.ll
index 714082791fe63..8a89ec3f3e043 100644
--- a/llvm/test/CodeGen/AMDGPU/add-debug.ll
+++ b/llvm/test/CodeGen/AMDGPU/add-debug.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=amdgpu6.00 -debug
; RUN: llc < %s -mtriple=amdgpu8.02 -debug
; REQUIRES: asserts
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll b/llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll
index aea9a6564096a..a22925cd0d358 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll
@@ -5,6 +5,8 @@
define amdgpu_ps float @v_sin_f32(float %src) #1 {
; GCN-LABEL: v_sin_f32:
; GCN: ; %bb.0:
+; GCN: global_prefetch_b8 v0, null scope:SCOPE_SE
+; GCN: v_nop
; GCN: v_sin_f32_e32 v0, v0
%sin = call float @llvm.amdgcn.sin.f32(float %src) #0
ret float %sin
@@ -13,6 +15,8 @@ define amdgpu_ps float @v_sin_f32(float %src) #1 {
define amdgpu_ps float @s_sin_f32(float inreg %src) #1 {
; GCN-LABEL: s_sin_f32:
; GCN: ; %bb.0:
+; GCN: global_prefetch_b8 v0, null scope:SCOPE_SE
+; GCN: v_nop
; GCN: v_sin_f32_e32 v0, s0
%sin = call float @llvm.amdgcn.sin.f32(float %src) #0
ret float %sin
@@ -21,10 +25,14 @@ define amdgpu_ps float @s_sin_f32(float inreg %src) #1 {
define amdgpu_ps half @v_sin_f16(half %src) #1 {
; FAKE16-LABEL: v_sin_f16:
; FAKE16: ; %bb.0:
+; FAKE16: global_prefetch_b8 v0, null scope:SCOPE_SE
+; FAKE16: v_nop
; FAKE16: v_sin_f16_e32 v0, v0
;
; REAL16-LABEL: v_sin_f16:
; REAL16: ; %bb.0:
+; REAL16: global_prefetch_b8 v0, null scope:SCOPE_SE
+; REAL16: v_nop
; REAL16: v_sin_f16_e32 v0.l, v0.l
%sin = call half @llvm.amdgcn.sin.f16(half %src) #0
ret half %sin
@@ -33,10 +41,14 @@ define amdgpu_ps half @v_sin_f16(half %src) #1 {
define amdgpu_ps half @s_sin_f16(half inreg %src) #1 {
; FAKE16-LABEL: s_sin_f16:
; FAKE16: ; %bb.0:
+; FAKE16: global_prefetch_b8 v0, null scope:SCOPE_SE
+; FAKE16: v_nop
; FAKE16: v_sin_f16_e32 v0, s0
;
; REAL16-LABEL: s_sin_f16:
; REAL16: ; %bb.0:
+; REAL16: global_prefetch_b8 v0, null scope:SCOPE_SE
+; REAL16: v_nop
; REAL16: v_sin_f16_e32 v0.l, s0
%sin = call half @llvm.amdgcn.sin.f16(half %src) #0
ret half %sin
@@ -45,6 +57,8 @@ define amdgpu_ps half @s_sin_f16(half inreg %src) #1 {
define amdgpu_ps float @v_cos_f32(float %src) #1 {
; GCN-LABEL: v_cos_f32:
; GCN: ; %bb.0:
+; GCN: global_prefetch_b8 v0, null scope:SCOPE_SE
+; GCN: v_nop
; GCN: v_cos_f32_e32 v0, v0
%cos = call float @llvm.amdgcn.cos.f32(float %src) #0
ret float %cos
@@ -53,6 +67,8 @@ define amdgpu_ps float @v_cos_f32(float %src) #1 {
define amdgpu_ps float @s_cos_f32(float inreg %src) #1 {
; GCN-LABEL: s_cos_f32:
; GCN: ; %bb.0:
+; GCN: global_prefetch_b8 v0, null scope:SCOPE_SE
+; GCN: v_nop
; GCN: v_cos_f32_e32 v0, s0
%cos = call float @llvm.amdgcn.cos.f32(float %src) #0
ret float %cos
@@ -61,10 +77,14 @@ define amdgpu_ps float @s_cos_f32(float inreg %src) #1 {
define amdgpu_ps half @v_cos_f16(half %src) #1 {
; FAKE16-LABEL: v_cos_f16:
; FAKE16: ; %bb.0:
+; FAKE16: global_prefetch_b8 v0, null scope:SCOPE_SE
+; FAKE16: v_nop
; FAKE16: v_cos_f16_e32 v0, v0
;
; REAL16-LABEL: v_cos_f16:
; REAL16: ; %bb.0:
+; REAL16: global_prefetch_b8 v0, null scope:SCOPE_SE
+; REAL16: v_nop
; REAL16: v_cos_f16_e32 v0.l, v0.l
%cos = call half @llvm.amdgcn.cos.f16(half %src) #0
ret half %cos
@@ -73,10 +93,14 @@ define amdgpu_ps half @v_cos_f16(half %src) #1 {
define amdgpu_ps half @s_cos_f16(half inreg %src) #1 {
; FAKE16-LABEL: s_cos_f16:
; FAKE16: ; %bb.0:
+; FAKE16: global_prefetch_b8 v0, null scope:SCOPE_SE
+; FAKE16: v_nop
; FAKE16: v_cos_f16_e32 v0, s0
;
; REAL16-LABEL: s_cos_f16:
; REAL16: ; %bb.0:
+; REAL16: global_prefetch_b8 v0, null scope:SCOPE_SE
+; REAL16: v_nop
; REAL16: v_cos_f16_e32 v0.l, s0
%cos = call half @llvm.amdgcn.cos.f16(half %src) #0
ret half %cos
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
index de05fe56b8428..db8687edb2642 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
@@ -294,9 +294,7 @@ define amdgpu_kernel void @v_alignbyte_b32_2(ptr addrspace(1) %out, ptr addrspac
; GFX11-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x3c
; GFX11-TRUE16-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-GISEL-NEXT: v_mov_b32_e32 v2, s2
-; GFX11-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-GISEL-NEXT: v_alignbyte_b32 v0, v1, v0, v2.l
+; GFX11-TRUE16-GISEL-NEXT: v_alignbyte_b32 v0, v1, v0, s2
; GFX11-TRUE16-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-TRUE16-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
index 6f58dbbce3e77..63280bfb3715d 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
@@ -1848,21 +1848,21 @@ define amdgpu_kernel void @v_fcmp_f64_ule(ptr addrspace(1) %out, double %src) {
define amdgpu_kernel void @v_fcmp_f16_oeq_with_fabs(ptr addrspace(1) %out, half %src, half %a) {
-; GFX11-LABEL: v_fcmp_f16_oeq_with_fabs:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_lshr_b32 s3, s2, 16
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, |s3|
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: v_fcmp_f16_oeq_with_fabs:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_clause 0x1
+; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: s_lshr_b32 s3, s2, 16
+; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, |s3|
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
;
; GFX9-SDAG-LABEL: v_fcmp_f16_oeq_with_fabs:
; GFX9-SDAG: ; %bb.0:
@@ -1929,21 +1929,21 @@ define amdgpu_kernel void @v_fcmp_f16_oeq_with_fabs(ptr addrspace(1) %out, half
define amdgpu_kernel void @v_fcmp_f16_oeq_both_operands_with_fabs(ptr addrspace(1) %out, half %src, half %a) {
-; GFX11-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_lshr_b32 s3, s2, 16
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_eq_f16_e64 s[2:3], |s2|, |s3|
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_clause 0x1
+; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: s_lshr_b32 s3, s2, 16
+; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cmp_eq_f16_e64 s[2:3], |s2|, |s3|
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
;
; GFX9-SDAG-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
; GFX9-SDAG: ; %bb.0:
@@ -2053,19 +2053,19 @@ define amdgpu_kernel void @v_fcmp_f16(ptr addrspace(1) %out, half %src) {
define amdgpu_kernel void @v_fcmp_f16_oeq(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_oeq:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_eq_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: v_fcmp_f16_oeq:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_clause 0x1
+; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_eq_f16_e64 s[2:3], 0x5640, s2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
;
; GFX9-LABEL: v_fcmp_f16_oeq:
; GFX9: ; %bb.0:
@@ -2114,19 +2114,19 @@ define amdgpu_kernel void @v_fcmp_f16_oeq(ptr addrspace(1) %out, half %src) {
define amdgpu_kernel void @v_fcmp_f16_one(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_one:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_neq_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: v_fcmp_f16_one:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_clause 0x1
+; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_neq_f16_e64 s[2:3], 0x5640, s2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
;
; GFX9-LABEL: v_fcmp_f16_one:
; GFX9: ; %bb.0:
@@ -2175,19 +2175,19 @@ define amdgpu_kernel void @v_fcmp_f16_one(ptr addrspace(1) %out, half %src) {
define amdgpu_kernel void @v_fcmp_f16_ogt(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_ogt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_lt_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: v_fcmp_f16_ogt:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_clause 0x1
+; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_lt_f16_e64 s[2:3], 0x5640, s2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
;
; GFX9-LABEL: v_fcmp_f16_ogt:
; GFX9: ; %bb.0:
@@ -2236,19 +2236,19 @@ define amdgpu_kernel void @v_fcmp_f16_ogt(ptr addrspace(1) %out, half %src) {
define amdgpu_kernel void @v_fcmp_f16_oge(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_oge:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_le_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: v_fcmp_f16_oge:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_clause 0x1
+; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_le_f16_e64 s[2:3], 0x5640, s2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
;
; GFX9-LABEL: v_fcmp_f16_oge:
; GFX9: ; %bb.0:
@@ -2297,19 +2297,19 @@ define amdgpu_kernel void @v_fcmp_f16_oge(ptr addrspace(1) %out, half %src) {
define amdgpu_kernel void @v_fcmp_f16_olt(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_olt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: v_fcmp_f16_olt:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_clause 0x1
+; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_gt_f16_e64 s[2:3], 0x5640, s2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
;
; GFX9-LABEL: v_fcmp_f16_olt:
; GFX9: ; %bb.0:
@@ -2358,19 +2358,19 @@ define amdgpu_kernel void @v_fcmp_f16_olt(ptr addrspace(1) %out, half %src) {
define amdgpu_kernel void @v_fcmp_f16_ole(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_ole:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ge_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: v_fcmp_f16_ole:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_clause 0x1
+; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_ge_f16_e64 s[2:3], 0x5640, s2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
;
; GFX9-LABEL: v_fcmp_f16_ole:
; GFX9: ; %bb.0:
@@ -2419,19 +2419,19 @@ define amdgpu_kernel void @v_fcmp_f16_ole(ptr addrspace(1) %out, half %src) {
define amdgpu_kernel void @v_fcmp_f16_ueq(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_ueq:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nlg_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: v_fcmp_f16_ueq:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_clause 0x1
+; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_nlg_f16_e64 s[2:3], 0x5640, s2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
;
; GFX9-LABEL: v_fcmp_f16_ueq:
; GFX9: ; %bb.0:
@@ -2480,19 +2480,19 @@ define amdgpu_kernel void @v_fcmp_f16_ueq(ptr addrspace(1) %out, half %src) {
define amdgpu_kernel void @v_fcmp_f16_une(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_une:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_neq_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: v_fcmp_f16_une:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_clause 0x1
+; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_neq_f16_e64 s[2:3], 0x5640, s2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
;
; GFX9-LABEL: v_fcmp_f16_une:
; GFX9: ; %bb.0:
@@ -2541,19 +2541,19 @@ define amdgpu_kernel void @v_fcmp_f16_une(ptr addrspace(1) %out, half %src) {
define amdgpu_kernel void @v_fcmp_f16_ugt(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_ugt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nge_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: v_fcmp_f16_ugt:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_clause 0x1
+; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_nge_f16_e64 s[2:3], 0x5640, s2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
;
; GFX9-LABEL: v_fcmp_f16_ugt:
; GFX9: ; %bb.0:
@@ -2602,19 +2602,19 @@ define amdgpu_kernel void @v_fcmp_f16_ugt(ptr addrspace(1) %out, half %src) {
define amdgpu_kernel void @v_fcmp_f16_uge(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_uge:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ngt_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: v_fcmp_f16_uge:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_clause 0x1
+; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_ngt_f16_e64 s[2:3], 0x5640, s2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
;
; GFX9-LABEL: v_fcmp_f16_uge:
; GFX9: ; %bb.0:
@@ -2663,19 +2663,19 @@ define amdgpu_kernel void @v_fcmp_f16_uge(ptr addrspace(1) %out, half %src) {
define amdgpu_kernel void @v_fcmp_f16_ult(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_ult:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nle_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: v_fcmp_f16_ult:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_clause 0x1
+; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_nle_f16_e64 s[2:3], 0x5640, s2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
;
; GFX9-LABEL: v_fcmp_f16_ult:
; GFX9: ; %bb.0:
@@ -2723,19 +2723,19 @@ define amdgpu_kernel void @v_fcmp_f16_ult(ptr addrspace(1) %out, half %src) {
}
define amdgpu_kernel void @v_fcmp_f16_o(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_o:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_o_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: v_fcmp_f16_o:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_clause 0x1
+; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_o_f16_e64 s[2:3], 0x5640, s2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
;
; GFX9-LABEL: v_fcmp_f16_o:
; GFX9: ; %bb.0:
@@ -2783,19 +2783,19 @@ define amdgpu_kernel void @v_fcmp_f16_o(ptr addrspace(1) %out, half %src) {
}
define amdgpu_kernel void @v_fcmp_f16_uo(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_uo:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_u_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: v_fcmp_f16_uo:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_clause 0x1
+; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_u_f16_e64 s[2:3], 0x5640, s2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
;
; GFX9-LABEL: v_fcmp_f16_uo:
; GFX9: ; %bb.0:
@@ -2843,19 +2843,19 @@ define amdgpu_kernel void @v_fcmp_f16_uo(ptr addrspace(1) %out, half %src) {
}
define amdgpu_kernel void @v_fcmp_f16_ule(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_ule:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nlt_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: v_fcmp_f16_ule:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_clause 0x1
+; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_cmp_nlt_f16_e64 s[2:3], 0x5640, s2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
;
; GFX9-LABEL: v_fcmp_f16_ule:
; GFX9: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
index 4876cd4c5f0a9..2f308f435ef97 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
@@ -1066,19 +1066,6 @@ define amdgpu_kernel void @v_icmp_i16_eq(ptr addrspace(1) %out, i16 %src) {
; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; SDAG-GFX10-NEXT: s_endpgm
;
-; GISEL-GFX11-LABEL: v_icmp_i16_eq:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_eq_u16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
; GISEL-GFX10-LABEL: v_icmp_i16_eq:
; GISEL-GFX10: ; %bb.0:
; GISEL-GFX10-NEXT: s_clause 0x1
@@ -1149,19 +1136,6 @@ define amdgpu_kernel void @v_icmp_i16_ne(ptr addrspace(1) %out, i16 %src) {
; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; SDAG-GFX10-NEXT: s_endpgm
;
-; GISEL-GFX11-LABEL: v_icmp_i16_ne:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ne_u16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
; GISEL-GFX10-LABEL: v_icmp_i16_ne:
; GISEL-GFX10: ; %bb.0:
; GISEL-GFX10-NEXT: s_clause 0x1
@@ -1203,19 +1177,6 @@ define amdgpu_kernel void @v_icmp_i16_ugt(ptr addrspace(1) %out, i16 %src) {
; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; SDAG-GFX10-NEXT: s_endpgm
;
-; GISEL-GFX11-LABEL: v_icmp_i16_ugt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_lt_u16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
; GISEL-GFX10-LABEL: v_icmp_i16_ugt:
; GISEL-GFX10: ; %bb.0:
; GISEL-GFX10-NEXT: s_clause 0x1
@@ -1257,19 +1218,6 @@ define amdgpu_kernel void @v_icmp_i16_uge(ptr addrspace(1) %out, i16 %src) {
; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; SDAG-GFX10-NEXT: s_endpgm
;
-; GISEL-GFX11-LABEL: v_icmp_i16_uge:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_le_u16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
; GISEL-GFX10-LABEL: v_icmp_i16_uge:
; GISEL-GFX10: ; %bb.0:
; GISEL-GFX10-NEXT: s_clause 0x1
@@ -1311,19 +1259,6 @@ define amdgpu_kernel void @v_icmp_i16_ult(ptr addrspace(1) %out, i16 %src) {
; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; SDAG-GFX10-NEXT: s_endpgm
;
-; GISEL-GFX11-LABEL: v_icmp_i16_ult:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_gt_u16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
; GISEL-GFX10-LABEL: v_icmp_i16_ult:
; GISEL-GFX10: ; %bb.0:
; GISEL-GFX10-NEXT: s_clause 0x1
@@ -1365,19 +1300,6 @@ define amdgpu_kernel void @v_icmp_i16_ule(ptr addrspace(1) %out, i16 %src) {
; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; SDAG-GFX10-NEXT: s_endpgm
;
-; GISEL-GFX11-LABEL: v_icmp_i16_ule:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ge_u16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
; GISEL-GFX10-LABEL: v_icmp_i16_ule:
; GISEL-GFX10: ; %bb.0:
; GISEL-GFX10-NEXT: s_clause 0x1
@@ -1419,19 +1341,6 @@ define amdgpu_kernel void @v_icmp_i16_sgt(ptr addrspace(1) %out, i16 %src) #1 {
; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; SDAG-GFX10-NEXT: s_endpgm
;
-; GISEL-GFX11-LABEL: v_icmp_i16_sgt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_lt_i16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
; GISEL-GFX10-LABEL: v_icmp_i16_sgt:
; GISEL-GFX10: ; %bb.0:
; GISEL-GFX10-NEXT: s_clause 0x1
@@ -1473,19 +1382,6 @@ define amdgpu_kernel void @v_icmp_i16_sge(ptr addrspace(1) %out, i16 %src) {
; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; SDAG-GFX10-NEXT: s_endpgm
;
-; GISEL-GFX11-LABEL: v_icmp_i16_sge:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_le_i16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
; GISEL-GFX10-LABEL: v_icmp_i16_sge:
; GISEL-GFX10: ; %bb.0:
; GISEL-GFX10-NEXT: s_clause 0x1
@@ -1527,19 +1423,6 @@ define amdgpu_kernel void @v_icmp_i16_slt(ptr addrspace(1) %out, i16 %src) {
; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; SDAG-GFX10-NEXT: s_endpgm
;
-; GISEL-GFX11-LABEL: v_icmp_i16_slt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_gt_i16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
; GISEL-GFX10-LABEL: v_icmp_i16_slt:
; GISEL-GFX10: ; %bb.0:
; GISEL-GFX10-NEXT: s_clause 0x1
@@ -1581,19 +1464,6 @@ define amdgpu_kernel void @v_icmp_i16_sle(ptr addrspace(1) %out, i16 %src) {
; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; SDAG-GFX10-NEXT: s_endpgm
;
-; GISEL-GFX11-LABEL: v_icmp_i16_sle:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ge_i16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
; GISEL-GFX10-LABEL: v_icmp_i16_sle:
; GISEL-GFX10: ; %bb.0:
; GISEL-GFX10-NEXT: s_clause 0x1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
index 541a7c73e8c07..b93af1e0ad4a5 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
@@ -1237,19 +1237,19 @@ define amdgpu_kernel void @v_icmp_i64_sle(ptr addrspace(1) %out, i64 %src) {
}
define amdgpu_kernel void @v_icmp_i16_eq(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_eq:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_eq_u16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; SDAG-GFX11-LABEL: v_icmp_i16_eq:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_clause 0x1
+; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v2, 0
+; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_cmp_eq_u16_e64 s[2:3], 0x64, s2
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v0, s2
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v1, s3
+; SDAG-GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; SDAG-GFX11-NEXT: s_endpgm
;
; SDAG-VI-LABEL: v_icmp_i16_eq:
; SDAG-VI: ; %bb.0:
@@ -1339,19 +1339,19 @@ define amdgpu_kernel void @v_icmp_i16(ptr addrspace(1) %out, i16 %src) {
}
define amdgpu_kernel void @v_icmp_i16_ne(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_ne:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ne_u16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; SDAG-GFX11-LABEL: v_icmp_i16_ne:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_clause 0x1
+; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v2, 0
+; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_cmp_ne_u16_e64 s[2:3], 0x64, s2
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v0, s2
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v1, s3
+; SDAG-GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; SDAG-GFX11-NEXT: s_endpgm
;
; SDAG-VI-LABEL: v_icmp_i16_ne:
; SDAG-VI: ; %bb.0:
@@ -1399,19 +1399,19 @@ define amdgpu_kernel void @v_icmp_i16_ne(ptr addrspace(1) %out, i16 %src) {
}
define amdgpu_kernel void @v_icmp_i16_ugt(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_ugt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_lt_u16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; SDAG-GFX11-LABEL: v_icmp_i16_ugt:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_clause 0x1
+; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v2, 0
+; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_cmp_lt_u16_e64 s[2:3], 0x64, s2
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v0, s2
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v1, s3
+; SDAG-GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; SDAG-GFX11-NEXT: s_endpgm
;
; SDAG-VI-LABEL: v_icmp_i16_ugt:
; SDAG-VI: ; %bb.0:
@@ -1459,19 +1459,19 @@ define amdgpu_kernel void @v_icmp_i16_ugt(ptr addrspace(1) %out, i16 %src) {
}
define amdgpu_kernel void @v_icmp_i16_uge(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_uge:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_le_u16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; SDAG-GFX11-LABEL: v_icmp_i16_uge:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_clause 0x1
+; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v2, 0
+; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_cmp_le_u16_e64 s[2:3], 0x64, s2
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v0, s2
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v1, s3
+; SDAG-GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; SDAG-GFX11-NEXT: s_endpgm
;
; SDAG-VI-LABEL: v_icmp_i16_uge:
; SDAG-VI: ; %bb.0:
@@ -1519,19 +1519,19 @@ define amdgpu_kernel void @v_icmp_i16_uge(ptr addrspace(1) %out, i16 %src) {
}
define amdgpu_kernel void @v_icmp_i16_ult(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_ult:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_u16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; SDAG-GFX11-LABEL: v_icmp_i16_ult:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_clause 0x1
+; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v2, 0
+; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_cmp_gt_u16_e64 s[2:3], 0x64, s2
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v0, s2
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v1, s3
+; SDAG-GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; SDAG-GFX11-NEXT: s_endpgm
;
; SDAG-VI-LABEL: v_icmp_i16_ult:
; SDAG-VI: ; %bb.0:
@@ -1579,19 +1579,19 @@ define amdgpu_kernel void @v_icmp_i16_ult(ptr addrspace(1) %out, i16 %src) {
}
define amdgpu_kernel void @v_icmp_i16_ule(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_ule:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ge_u16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; SDAG-GFX11-LABEL: v_icmp_i16_ule:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_clause 0x1
+; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v2, 0
+; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_cmp_ge_u16_e64 s[2:3], 0x64, s2
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v0, s2
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v1, s3
+; SDAG-GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; SDAG-GFX11-NEXT: s_endpgm
;
; SDAG-VI-LABEL: v_icmp_i16_ule:
; SDAG-VI: ; %bb.0:
@@ -1639,19 +1639,19 @@ define amdgpu_kernel void @v_icmp_i16_ule(ptr addrspace(1) %out, i16 %src) {
}
define amdgpu_kernel void @v_icmp_i16_sgt(ptr addrspace(1) %out, i16 %src) #1 {
-; GFX11-LABEL: v_icmp_i16_sgt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_lt_i16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; SDAG-GFX11-LABEL: v_icmp_i16_sgt:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_clause 0x1
+; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v2, 0
+; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_cmp_lt_i16_e64 s[2:3], 0x64, s2
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v0, s2
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v1, s3
+; SDAG-GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; SDAG-GFX11-NEXT: s_endpgm
;
; SDAG-VI-LABEL: v_icmp_i16_sgt:
; SDAG-VI: ; %bb.0:
@@ -1699,19 +1699,19 @@ define amdgpu_kernel void @v_icmp_i16_sgt(ptr addrspace(1) %out, i16 %src) #1 {
}
define amdgpu_kernel void @v_icmp_i16_sge(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_sge:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_le_i16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; SDAG-GFX11-LABEL: v_icmp_i16_sge:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_clause 0x1
+; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v2, 0
+; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_cmp_le_i16_e64 s[2:3], 0x64, s2
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v0, s2
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v1, s3
+; SDAG-GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; SDAG-GFX11-NEXT: s_endpgm
;
; SDAG-VI-LABEL: v_icmp_i16_sge:
; SDAG-VI: ; %bb.0:
@@ -1759,19 +1759,19 @@ define amdgpu_kernel void @v_icmp_i16_sge(ptr addrspace(1) %out, i16 %src) {
}
define amdgpu_kernel void @v_icmp_i16_slt(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_slt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_i16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; SDAG-GFX11-LABEL: v_icmp_i16_slt:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_clause 0x1
+; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v2, 0
+; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_cmp_gt_i16_e64 s[2:3], 0x64, s2
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v0, s2
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v1, s3
+; SDAG-GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; SDAG-GFX11-NEXT: s_endpgm
;
; SDAG-VI-LABEL: v_icmp_i16_slt:
; SDAG-VI: ; %bb.0:
@@ -1819,19 +1819,19 @@ define amdgpu_kernel void @v_icmp_i16_slt(ptr addrspace(1) %out, i16 %src) {
}
define amdgpu_kernel void @v_icmp_i16_sle(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_sle:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ge_i16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; SDAG-GFX11-LABEL: v_icmp_i16_sle:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_clause 0x1
+; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v2, 0
+; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_cmp_ge_i16_e64 s[2:3], 0x64, s2
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v0, s2
+; SDAG-GFX11-NEXT: v_mov_b32_e32 v1, s3
+; SDAG-GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; SDAG-GFX11-NEXT: s_endpgm
;
; SDAG-VI-LABEL: v_icmp_i16_sle:
; SDAG-VI: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/true16-fold.mir b/llvm/test/CodeGen/AMDGPU/true16-fold.mir
index 29be6c55e6f30..5a12046abc61c 100644
--- a/llvm/test/CodeGen/AMDGPU/true16-fold.mir
+++ b/llvm/test/CodeGen/AMDGPU/true16-fold.mir
@@ -265,3 +265,65 @@ body: |
$vgpr0 = COPY %5
SI_RETURN implicit $vgpr0
...
+
+---
+name: fold_sreg32_cross_lo16_copy_1
+tracksRegLiveness: true
+registers:
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: fold_sreg32_cross_lo16_copy_1
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK-NEXT: [[V_MAX_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_MAX_F16_t16_e64 0, [[COPY]], 0, [[COPY]], -1, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0
+ %0:sreg_32 = COPY $sgpr0
+ %1:vgpr_32 = COPY %0:sreg_32
+ %2:vgpr_16 = COPY %1.lo16:vgpr_32
+ %3:vgpr_16 = nofpexcept V_MAX_F16_t16_e64 0, %2, 0, %2, -1, 0, 0, implicit $mode, implicit $exec
+ S_ENDPGM 0
+...
+
+---
+name: fold_sreg32_cross_lo16_copy_2
+tracksRegLiveness: true
+registers:
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: fold_sreg32_cross_lo16_copy_2
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[V_MAX_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_MAX_F16_t16_e64 0, [[DEF]].sub1, 0, [[DEF]].sub1, -1, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0
+ %0:sreg_64 = IMPLICIT_DEF
+ %1:vgpr_32 = COPY %0.sub1:sreg_64
+ %2:vgpr_16 = COPY %1.lo16:vgpr_32
+ %3:vgpr_16 = nofpexcept V_MAX_F16_t16_e64 0, %2, 0, %2, -1, 0, 0, implicit $mode, implicit $exec
+ S_ENDPGM 0
+...
+
+# Should not fold
+---
+name: fold_sreg32_cross_hi16
+tracksRegLiveness: true
+registers:
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: fold_sreg32_cross_hi16
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
+ ; CHECK-NEXT: [[V_MAX_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_MAX_F16_t16_e64 0, [[COPY1]].hi16, 0, [[COPY1]].hi16, -1, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0
+ %0:sreg_32 = COPY $sgpr0
+ %1:vgpr_32 = COPY %0:sreg_32
+ %2:vgpr_16 = COPY %1.hi16:vgpr_32
+ %3:vgpr_16 = nofpexcept V_MAX_F16_t16_e64 0, %2, 0, %2, -1, 0, 0, implicit $mode, implicit $exec
+ S_ENDPGM 0
+...
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