[llvm] [DAGCombiner] Don't create illegal types in visitSRL (PR #215374)

[Adam Nemet via llvm-commits]

https://github.com/anemet created https://github.com/llvm/llvm-project/pull/215374

Besides what's fixed in #205074, the srl(bitcast(build_vector)) fold added in #181412 has another way to create an illegal type: the bitcast to LastElt.getValueType().changeTypeToInteger() is itself illegal when, for example, LastElt is f16 and i16 is not a legal type.

Unfortunately, this happens in a downstream target so no testcase.

>From ba10a62f0e1409a109cf00e448f59e4f16c35018 Mon Sep 17 00:00:00 2001
From: Adam Nemet <anemet at apple.com>
Date: Mon, 10 Aug 2026 12:16:47 -0700
Subject: [PATCH] [DAGCombiner] Don't create illegal types in visitSRL

Besides what's fixed in #205074, the srl(bitcast(build_vector)) fold
added in #181412 has another way to create an illegal type: the
bitcast to LastElt.getValueType().changeTypeToInteger() is itself
illegal when, for example, LastElt is f16 and i16 is not a legal
type.

Unfortunately, this happens in a downstream target so no testcase.
---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d7db5fb1b9e40..8b8ced73f38bc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -11880,12 +11880,14 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
         SDValue LastElt = BV.getOperand(NumElts - 1);
         assert(LastElt.getScalarValueSizeInBits() >= EltSizeInBits &&
                "Expected BUILD_VECTOR operand as wide as element type");
-        LastElt = DAG.getBitcast(LastElt.getValueType().changeTypeToInteger(),
-                                 LastElt);
-        SDValue Ext = DAG.getZExtOrTrunc(LastElt, DL, VT);
-        APInt Mask = APInt::getLowBitsSet(VT.getSizeInBits(), EltSizeInBits);
-        return DAG.getNode(ISD::AND, DL, VT, Ext,
-                           DAG.getConstant(Mask, DL, VT));
+        EVT IntEltVT = LastElt.getValueType().changeTypeToInteger();
+        if (!LegalTypes || TLI.isTypeLegal(IntEltVT)) {
+          LastElt = DAG.getBitcast(IntEltVT, LastElt);
+          SDValue Ext = DAG.getZExtOrTrunc(LastElt, DL, VT);
+          APInt Mask = APInt::getLowBitsSet(VT.getSizeInBits(), EltSizeInBits);
+          return DAG.getNode(ISD::AND, DL, VT, Ext,
+                             DAG.getConstant(Mask, DL, VT));
+        }
       }
     }
   }