[llvm] [TableGen] Add isReg check for CheckRegOperand predicate (PR #215230)

[Nemanja Ivanovic via llvm-commits]

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@@ -123,8 +128,8 @@ class CheckOperandBase<int Index, string Fn = ""> : MCOperandPredicate<Index> {
 }
 
 // Check that the machine register operand at position `Index` references
-// register R. This predicate assumes that we already checked that the machine
-// operand at position `Index` is a register operand.
+// register R. This predicate checks whether the operand at position `Index`
+// is a register first and return false when not satisfied.
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nemanjai wrote:

It seems reasonable to simply rewrite this comment:
```
// Check that the machine register operand at position `Index` is a register
// operand and that it matches register `R`.
```

https://github.com/llvm/llvm-project/pull/215230