[llvm] [VPlan] Expand negated add operands as a subtract in VPSCEVExpander. (PR #215253)
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 10 04:56:25 PDT 2026
https://github.com/fhahn created https://github.com/llvm/llvm-project/pull/215253
Update VPSCEVExpander to try to expand adds of negative values as
subtract, instead of adding the negated operand. This matches IR
SCEVExpander behavior and improves expansions slightly.
It also avoids regressions when expanding more expressions.
Alive2 Proof: https://alive2.llvm.org/ce/z/Emgeqv
Depends on https://github.com/llvm/llvm-project/pull/215252 (included in PR)
>From bc4233c06cc9366ecd4b3b654e629153d44631f4 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Mon, 10 Aug 2026 09:24:23 +0100
Subject: [PATCH 1/2] [VPlan] Sort non-constant-negative add operands last in
VPSCEVExpander.
Update the order in which operands for SCEVAddExpr are expanded.
Negative non-constant operands are moved to the end, matching the equivalent
ordering in SCEVExpander's LoopCompare.
Negated operands require multiplying with a negative constant, so it is better
accumulated into the result than used to start it: a following operand can then
be folded into the running sum, which removes a few adds.
The impact in this patch is small (just a few improvements), but it is also a
prerequisite for expanding those operands as a subtraction, matching
IR SCEVExpander in more cases.
---
llvm/lib/Transforms/Vectorize/VPlanUtils.cpp | 11 ++++-
.../AArch64/aggressive-interleaving.ll | 4 +-
.../LoopVectorize/AArch64/induction-costs.ll | 4 +-
.../AArch64/partial-reduce-constant-ops.ll | 28 +++++------
.../partial-reduce-incomplete-chains.ll | 4 +-
.../replicating-load-store-costs-apple.ll | 7 ++-
.../AArch64/replicating-load-store-costs.ll | 7 ++-
.../AArch64/sve-live-out-pointer-induction.ll | 4 +-
...-interleave-to-widen-memory-derived-ivs.ll | 12 ++---
.../ARM/tail-folding-counting-down.ll | 8 ++--
.../LoopVectorize/PowerPC/pr41179.ll | 14 +++---
.../RISCV/dbg-tail-folding-by-evl.ll | 12 ++---
.../LoopVectorize/RISCV/iv-select-cmp.ll | 4 +-
.../LoopVectorize/RISCV/pointer-induction.ll | 8 ++--
.../LoopVectorize/VPlan/expand-scev.ll | 2 +-
.../X86/fold-tail-low-trip-count.ll | 8 ++--
.../X86/interleave-opaque-pointers.ll | 4 +-
.../Transforms/LoopVectorize/X86/optsize.ll | 8 ++--
.../Transforms/LoopVectorize/X86/pr35432.ll | 4 +-
.../Transforms/LoopVectorize/X86/pr48340.ll | 8 ++--
.../Transforms/LoopVectorize/X86/pr72969.ll | 4 +-
.../LoopVectorize/X86/predicate-switch.ll | 48 +++++++++----------
.../X86/replicating-load-store-costs.ll | 4 +-
.../LoopVectorize/cast-induction.ll | 8 ++--
.../LoopVectorize/expand-ptrtoaddr.ll | 4 +-
...find-last-iv-sinkable-expr-tail-folding.ll | 4 +-
.../find-last-iv-sinkable-expr.ll | 4 +-
.../Transforms/LoopVectorize/find-last.ll | 4 +-
.../LoopVectorize/first-order-recurrence.ll | 24 +++++-----
...nd-sink-mem-ops-with-invariant-pointers.ll | 4 +-
.../Transforms/LoopVectorize/if-conversion.ll | 8 ++--
.../LoopVectorize/induction-ptrcasts.ll | 6 +--
.../interleaved-accesses-metadata.ll | 8 ++--
...idate-scev-at-scope-after-vectorization.ll | 4 +-
.../invariant-store-vectorization.ll | 4 +-
.../LoopVectorize/iv-select-cmp-decreasing.ll | 12 ++---
.../LoopVectorize/iv-select-cmp-fold-tail.ll | 4 +-
.../LoopVectorize/iv_outside_user.ll | 8 ++--
.../nested-loops-scev-expansion.ll | 23 ++++-----
.../Transforms/LoopVectorize/opaque-ptr.ll | 12 ++---
llvm/test/Transforms/LoopVectorize/pr37248.ll | 8 ++--
llvm/test/Transforms/LoopVectorize/pr45259.ll | 2 +-
.../LoopVectorize/pr58811-scev-expansion.ll | 8 ++--
.../preserve-dbg-loc-and-loop-metadata.ll | 8 ++--
.../reduction-minmax-users-and-predicated.ll | 4 +-
.../LoopVectorize/reduction-small-size.ll | 4 +-
.../LoopVectorize/runtime-check-known-true.ll | 4 +-
.../runtime-checks-difference.ll | 8 ++--
.../LoopVectorize/scev-predicate-reasoning.ll | 8 ++--
.../single-early-exit-deref-assumptions.ll | 20 ++++----
.../PhaseOrdering/AArch64/std-find.ll | 4 +-
51 files changed, 218 insertions(+), 218 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
index 93b18b31e9e7d..7cae96192453c 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
@@ -894,9 +894,16 @@ VPValue *VPSCEVExpander::tryToExpand(const SCEV *S) {
unsigned Opcode =
S->getSCEVType() == scAddExpr ? Instruction::Add : Instruction::Mul;
- // Iterate in reverse so that constants are emitted last.
+ // Iterate in reverse so that constants are emitted last. For adds, sort
+ // non-constant-negative operands last, matching SCEVExpander's LoopCompare,
+ // so that they are accumulated into the result rather than starting it.
+ SmallVector<const SCEV *, 2> SCEVOps(reverse(NAry->operands()));
+ if (Opcode == Instruction::Add)
+ stable_sort(SCEVOps, [](const SCEV *L, const SCEV *R) {
+ return !L->isNonConstantNegative() && R->isNonConstantNegative();
+ });
SmallVector<VPValue *, 2> Ops;
- for (const SCEVUse &Op : reverse(NAry->operands())) {
+ for (const SCEV *Op : SCEVOps) {
VPValue *OpV = tryToExpand(Op);
if (!OpV)
return nullptr;
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll b/llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll
index 9789e291dc1a9..8a6de3f6a7ba6 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll
@@ -24,8 +24,8 @@ define void @test_interleave_reduction(ptr %arg, ptr %arg1) {
; A320-NEXT: [[TPM32:%.*]] = getelementptr inbounds double, ptr [[TPM17]], i64 [[TPM26]]
; A320-NEXT: [[TMP0:%.*]] = ptrtoaddr ptr [[TPM29]] to i64
; A320-NEXT: [[TPM102:%.*]] = ptrtoaddr ptr [[TPM10]] to i64
-; A320-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[TPM102]]
-; A320-NEXT: [[TMP6:%.*]] = add i64 [[TMP1]], -8
+; A320-NEXT: [[TMP8:%.*]] = add i64 [[TMP0]], -8
+; A320-NEXT: [[TMP6:%.*]] = sub i64 [[TMP8]], [[TPM102]]
; A320-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP6]], 2
; A320-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; A320-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
index cc4370f653274..b9ba8e81ef5f0 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
@@ -438,8 +438,8 @@ define i32 @load_from_pointer_induction(ptr %start, ptr %end) {
; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; CHECK-NEXT: [[START2:%.*]] = ptrtoaddr ptr [[START]] to i64
; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.umax.i64(i64 [[END1]], i64 [[START2]])
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
-; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[TMP1]], 1
+; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[TMP0]], 1
+; CHECK-NEXT: [[TMP20:%.*]] = sub i64 [[TMP21]], [[START2]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP20]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll
index 0f7e374733528..437f6aadc5a55 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll
@@ -9,8 +9,8 @@ define i32 @red_zext_mul_by_63(ptr %start, ptr %end) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoaddr ptr [[START]] to i64
-; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[END1]], [[TMP7]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP8]], 1
+; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[END1]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP8]], [[TMP7]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -75,8 +75,8 @@ define i32 @red_zext_mul_by_255(ptr %start, ptr %end) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = ptrtoaddr ptr [[START]] to i64
-; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[END1]], [[TMP5]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP8]], 1
+; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[END1]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP8]], [[TMP5]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -141,8 +141,8 @@ define i32 @red_zext_mul_by_256(ptr %start, ptr %end) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = ptrtoaddr ptr [[START]] to i64
-; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[END1]], [[TMP8]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], 1
+; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[END1]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP9]], [[TMP8]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -207,8 +207,8 @@ define i32 @red_sext_mul_by_63(ptr %start, ptr %end) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoaddr ptr [[START]] to i64
-; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[END1]], [[TMP7]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP8]], 1
+; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[END1]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP8]], [[TMP7]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -275,8 +275,8 @@ define i32 @red_sext_mul_by_128(ptr %start, ptr %end) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = ptrtoaddr ptr [[START]] to i64
-; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[END1]], [[TMP8]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], 1
+; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[END1]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP9]], [[TMP8]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -342,8 +342,8 @@ define i32 @red_sext_mul_by_255(ptr %start, ptr %end) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = ptrtoaddr ptr [[START]] to i64
-; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[END1]], [[TMP8]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], 1
+; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[END1]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP9]], [[TMP8]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -408,8 +408,8 @@ define i32 @red_sext_mul_by_256(ptr %start, ptr %end) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = ptrtoaddr ptr [[START]] to i64
-; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[END1]], [[TMP8]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], 1
+; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[END1]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP9]], [[TMP8]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll
index bf0681edcc9a4..48d709840082c 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll
@@ -9,8 +9,8 @@ define i32 @red_extended_add_incomplete_chain(ptr %start, ptr %end, i32 %offset)
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = ptrtoaddr ptr [[START]] to i64
-; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[END1]], [[TMP8]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], 1
+; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[END1]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP9]], [[TMP8]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll b/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
index c62f6ef0acc4d..c16f93c902239 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
@@ -456,11 +456,10 @@ define void @test_prefer_vector_addressing(ptr %start, ptr %ms, ptr noalias %src
; CHECK-NEXT: [[START2:%.*]] = ptrtoaddr ptr [[START]] to i64
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[START2]], 3
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP10]], i64 [[TMP0]])
-; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], [[START2]]
-; CHECK-NEXT: [[TMP23:%.*]] = add i64 [[TMP2]], -3
+; CHECK-NEXT: [[TMP25:%.*]] = add i64 [[TMP1]], -3
+; CHECK-NEXT: [[TMP23:%.*]] = sub i64 [[TMP25]], [[START2]]
; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP23]], i64 1)
-; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[TMP2]], [[UMIN]]
-; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[TMP3]], -3
+; CHECK-NEXT: [[TMP24:%.*]] = sub i64 [[TMP23]], [[UMIN]]
; CHECK-NEXT: [[TMP4:%.*]] = udiv i64 [[TMP24]], 3
; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[UMIN]], [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP5]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
index 325c3ffe4eac7..ee038890245ae 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
@@ -452,11 +452,10 @@ define void @test_prefer_vector_addressing(ptr %start, ptr %ms, ptr noalias %src
; CHECK-NEXT: [[START2:%.*]] = ptrtoaddr ptr [[START]] to i64
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[START2]], 3
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP10]], i64 [[TMP0]])
-; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], [[START2]]
-; CHECK-NEXT: [[TMP23:%.*]] = add i64 [[TMP2]], -3
+; CHECK-NEXT: [[TMP25:%.*]] = add i64 [[TMP1]], -3
+; CHECK-NEXT: [[TMP23:%.*]] = sub i64 [[TMP25]], [[START2]]
; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP23]], i64 1)
-; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[TMP2]], [[UMIN]]
-; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[TMP3]], -3
+; CHECK-NEXT: [[TMP24:%.*]] = sub i64 [[TMP23]], [[UMIN]]
; CHECK-NEXT: [[TMP4:%.*]] = udiv i64 [[TMP24]], 3
; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[UMIN]], [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP5]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
index 31c089d65abf2..70df5bd33e61a 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
@@ -6,8 +6,8 @@ define ptr @test(ptr %start.1, ptr %start.2, ptr %end) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[START_22:%.*]] = ptrtoaddr ptr [[START_2:%.*]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END:%.*]] to i64
-; CHECK-NEXT: [[TMP6:%.*]] = sub i64 [[START_22]], [[END1]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP6]], -8
+; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[START_22]], -8
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP6]], [[END1]]
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll
index a39f080dc7241..7d8a89089c2fc 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll
@@ -132,8 +132,8 @@ define void @derived_pointer_ivs(ptr noalias %a, ptr noalias %b, ptr %end) {
; VF2-NEXT: [[ENTRY:.*:]]
; VF2-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; VF2-NEXT: [[TMP4:%.*]] = ptrtoaddr ptr [[A]] to i64
-; VF2-NEXT: [[TMP5:%.*]] = sub i64 [[END1]], [[TMP4]]
-; VF2-NEXT: [[TMP1:%.*]] = add i64 [[TMP5]], -16
+; VF2-NEXT: [[TMP5:%.*]] = add i64 [[END1]], -16
+; VF2-NEXT: [[TMP1:%.*]] = sub i64 [[TMP5]], [[TMP4]]
; VF2-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 4
; VF2-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; VF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
@@ -164,8 +164,8 @@ define void @derived_pointer_ivs(ptr noalias %a, ptr noalias %b, ptr %end) {
; VF2IC2-NEXT: [[ENTRY:.*:]]
; VF2IC2-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; VF2IC2-NEXT: [[TMP4:%.*]] = ptrtoaddr ptr [[A]] to i64
-; VF2IC2-NEXT: [[TMP5:%.*]] = sub i64 [[END1]], [[TMP4]]
-; VF2IC2-NEXT: [[TMP1:%.*]] = add i64 [[TMP5]], -16
+; VF2IC2-NEXT: [[TMP5:%.*]] = add i64 [[END1]], -16
+; VF2IC2-NEXT: [[TMP1:%.*]] = sub i64 [[TMP5]], [[TMP4]]
; VF2IC2-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 4
; VF2IC2-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; VF2IC2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
@@ -202,8 +202,8 @@ define void @derived_pointer_ivs(ptr noalias %a, ptr noalias %b, ptr %end) {
; VF4-NEXT: [[ENTRY:.*:]]
; VF4-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; VF4-NEXT: [[TMP4:%.*]] = ptrtoaddr ptr [[A]] to i64
-; VF4-NEXT: [[TMP5:%.*]] = sub i64 [[END1]], [[TMP4]]
-; VF4-NEXT: [[TMP1:%.*]] = add i64 [[TMP5]], -16
+; VF4-NEXT: [[TMP5:%.*]] = add i64 [[END1]], -16
+; VF4-NEXT: [[TMP1:%.*]] = sub i64 [[TMP5]], [[TMP4]]
; VF4-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 4
; VF4-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; VF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll
index 5884accd83d16..4621ddfd330eb 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll
@@ -84,8 +84,8 @@ define void @sgt_no_loopguard(ptr noalias nocapture readonly %a, ptr noalias noc
; COMMON-SAME: ptr noalias readonly captures(none) [[A:%.*]], ptr noalias readonly captures(none) [[B:%.*]], ptr noalias captures(none) [[C:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {
; COMMON-NEXT: [[ENTRY:.*:]]
; COMMON-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[N]], i32 1)
-; COMMON-NEXT: [[TMP4:%.*]] = sub i32 [[N]], [[SMIN]]
-; COMMON-NEXT: [[TMP1:%.*]] = add i32 [[TMP4]], 1
+; COMMON-NEXT: [[TMP4:%.*]] = add i32 [[N]], 1
+; COMMON-NEXT: [[TMP1:%.*]] = sub i32 [[TMP4]], [[SMIN]]
; COMMON-NEXT: br label %[[VECTOR_PH:.*]]
; COMMON: [[VECTOR_PH]]:
; COMMON-NEXT: [[N_RND_UP:%.*]] = add i32 [[TMP1]], 15
@@ -143,8 +143,8 @@ define void @sgt_extra_use_cmp(ptr noalias nocapture readonly %a, ptr noalias no
; COMMON-SAME: ptr noalias readonly captures(none) [[A:%.*]], ptr noalias readonly captures(none) [[B:%.*]], ptr noalias captures(none) [[C:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {
; COMMON-NEXT: [[ENTRY:.*:]]
; COMMON-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[N]], i32 1)
-; COMMON-NEXT: [[TMP8:%.*]] = sub i32 [[N]], [[SMIN]]
-; COMMON-NEXT: [[TMP1:%.*]] = add i32 [[TMP8]], 1
+; COMMON-NEXT: [[TMP8:%.*]] = add i32 [[N]], 1
+; COMMON-NEXT: [[TMP1:%.*]] = sub i32 [[TMP8]], [[SMIN]]
; COMMON-NEXT: br label %[[VECTOR_PH:.*]]
; COMMON: [[VECTOR_PH]]:
; COMMON-NEXT: [[N_RND_UP:%.*]] = add i32 [[TMP1]], 3
diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/pr41179.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/pr41179.ll
index 45547e33ff8cc..eb110b4c0a4c1 100644
--- a/llvm/test/Transforms/LoopVectorize/PowerPC/pr41179.ll
+++ b/llvm/test/Transforms/LoopVectorize/PowerPC/pr41179.ll
@@ -5,11 +5,11 @@ define void @foo(ptr %start, ptr %end) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[START2:%.*]] = ptrtoaddr ptr [[START:%.*]] to i64
+; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[START2]] to i32
; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END:%.*]] to i64
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[END1]], -1
-; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[START2]], i64 [[TMP1]])
+; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[START2]], -1
+; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[END1]], i64 [[TMP9]])
; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[UMIN]] to i32
-; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[END1]] to i32
; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP0]], [[TMP2]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP3]], 2
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
@@ -24,8 +24,8 @@ define void @foo(ptr %start, ptr %end) {
; CHECK-NEXT: [[INDUCTION3:%.*]] = add i32 [[OFFSET_IDX]], -1
; CHECK-NEXT: [[TMP4:%.*]] = sub i32 -1, [[INDEX]]
; CHECK-NEXT: [[TMP5:%.*]] = add nsw i32 -1, [[INDUCTION3]]
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[END]], i32 [[TMP4]]
-; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[END]], i32 [[TMP5]]
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[START]], i32 [[TMP4]]
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[START]], i32 [[TMP5]]
; CHECK-NEXT: store i8 0, ptr [[TMP6]], align 1
; CHECK-NEXT: store i8 0, ptr [[TMP7]], align 1
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
@@ -40,9 +40,9 @@ define void @foo(ptr %start, ptr %end) {
; CHECK: while.body:
; CHECK-NEXT: [[COUNT_09:%.*]] = phi i32 [ [[ADD:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
; CHECK-NEXT: [[ADD]] = add nsw i32 -1, [[COUNT_09]]
-; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr [[END]], i32 [[ADD]]
+; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr [[START]], i32 [[ADD]]
; CHECK-NEXT: store i8 0, ptr [[G]], align 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult ptr [[START]], [[G]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult ptr [[END]], [[G]]
; CHECK-NEXT: br i1 [[CMP]], label [[WHILE_BODY]], label [[WHILE_END_LOOPEXIT]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: while.end.loopexit:
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll b/llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
index 2cccae4de2fa5..e7405906b1668 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
@@ -8,8 +8,8 @@ define void @reverse_store(ptr %a, i64 %n) !dbg !3 {
; CHECK-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG3:![0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[N]], i64 1)
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[N]], [[UMIN]]
-; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP1]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[N]], 1
+; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[TMP1]], [[UMIN]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()
@@ -27,12 +27,12 @@ define void @reverse_store(ptr %a, i64 %n) !dbg !3 {
; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT1]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = add nsw <vscale x 2 x i64> [[VEC_IND]], splat (i64 -1), !dbg [[DBG6:![0-9]+]]
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 2 x i64> [[TMP7]], i64 0
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw i64, ptr [[A]], i64 [[TMP8]], !dbg [[DBG7:![0-9]+]]
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw i64, ptr [[A]], i64 [[TMP8]], !dbg [[DBG7:![0-9]+]]
; CHECK-NEXT: [[TMP11:%.*]] = sub nuw nsw i64 [[TMP5]], 1
; CHECK-NEXT: [[TMP12:%.*]] = sub i64 0, [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i64, ptr [[TMP9]], i64 [[TMP12]], !dbg [[DBG8:![0-9]+]]
-; CHECK-NEXT: [[TMP13:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vp.reverse.nxv2i64(<vscale x 2 x i64> [[TMP7]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP4]]), !dbg [[DBG8]]
-; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP13]], ptr align 8 [[TMP14]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP4]]), !dbg [[DBG8]]
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i64, ptr [[TMP10]], i64 [[TMP12]], !dbg [[DBG8:![0-9]+]]
+; CHECK-NEXT: [[TMP14:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vp.reverse.nxv2i64(<vscale x 2 x i64> [[TMP7]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP4]]), !dbg [[DBG8]]
+; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP14]], ptr align 8 [[TMP13]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP4]]), !dbg [[DBG8]]
; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP5]]
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <vscale x 2 x i64> [[VEC_IND]], [[BROADCAST_SPLAT2]]
; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/iv-select-cmp.ll b/llvm/test/Transforms/LoopVectorize/RISCV/iv-select-cmp.ll
index e2dbe7a0e41a4..afad205790594 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/iv-select-cmp.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/iv-select-cmp.ll
@@ -63,8 +63,8 @@ define i64 @select_decreasing_induction_icmp_non_const_start(ptr %a, ptr %b, i64
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[N]], i64 1)
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[N]], [[UMIN]]
-; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP1]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[N]], 1
+; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[TMP1]], [[UMIN]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64()
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll b/llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
index a55985caa28ab..667612a193dd5 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
@@ -9,8 +9,8 @@ define void @ptr_induction(ptr %p, ptr noalias %q, ptr noalias %p.end) #0 {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[P_END1:%.*]] = ptrtoaddr ptr [[P_END]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = ptrtoaddr ptr [[P]] to i64
-; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[P_END1]], [[TMP1]]
-; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP8]], 1
+; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[P_END1]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[TMP8]], [[TMP1]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x ptr> poison, ptr [[Q]], i64 0
@@ -65,8 +65,8 @@ define i1 @scalarize_ptr_induction(ptr %start, ptr %end, ptr noalias %dst, i1 %c
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoaddr ptr [[START]] to i64
-; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[END1]], [[TMP4]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP5]], -12
+; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[END1]], -12
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP5]], [[TMP4]]
; CHECK-NEXT: [[TMP2:%.*]] = udiv i64 [[TMP1]], 12
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
index 573dc9056f8bc..94ccb5b33273e 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
@@ -294,7 +294,7 @@ define i32 @mul_by_signed_min_expanded_to_shl(i1 %a) {
; CHECK-NEXT: IR %sub = sub i32 %rem.neg, 1
; CHECK-NEXT: IR %shl = shl i32 %sub, 31
; CHECK-NEXT: EMIT vp<[[VP2:%[0-9]+]]> = shl nuw ir<%rem.neg>, ir<31>
-; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = add vp<[[VP2]]>, ir<-2147483547>
+; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = add ir<-2147483547>, vp<[[VP2]]>
; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult vp<[[VP3]]>, ir<4>
; CHECK-NEXT: EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, vector.ph
diff --git a/llvm/test/Transforms/LoopVectorize/X86/fold-tail-low-trip-count.ll b/llvm/test/Transforms/LoopVectorize/X86/fold-tail-low-trip-count.ll
index c8472141668a4..b92a591ae5147 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/fold-tail-low-trip-count.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/fold-tail-low-trip-count.ll
@@ -46,8 +46,8 @@ define ptr @low_trip_count_via_profile_info_with_iv_live_out(ptr align 16 %start
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoaddr ptr [[START]] to i64
-; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[END1]], [[TMP7]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP8]], 1
+; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[END1]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP8]], [[TMP7]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP1]], 63
@@ -100,8 +100,8 @@ define void @low_trip_count_via_profile_info(ptr align 16 %start, ptr align 16 %
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; CHECK-NEXT: [[TMP6:%.*]] = ptrtoaddr ptr [[START]] to i64
-; CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[END1]], [[TMP6]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP7]], 1
+; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[END1]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP7]], [[TMP6]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP1]], 63
diff --git a/llvm/test/Transforms/LoopVectorize/X86/interleave-opaque-pointers.ll b/llvm/test/Transforms/LoopVectorize/X86/interleave-opaque-pointers.ll
index 30c46504f2495..fe4dce024a7a8 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/interleave-opaque-pointers.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/interleave-opaque-pointers.ll
@@ -11,8 +11,8 @@ define void @test_pr55375_interleave_opaque_ptr(ptr %start, ptr %end) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[START2:%.*]] = ptrtoaddr ptr [[START:%.*]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END:%.*]] to i64
-; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[START2]], [[END1]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP5]], -16
+; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[START2]], -16
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP5]], [[END1]]
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 4
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
diff --git a/llvm/test/Transforms/LoopVectorize/X86/optsize.ll b/llvm/test/Transforms/LoopVectorize/X86/optsize.ll
index 0b81eb6fa1c72..c78688c348b84 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/optsize.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/optsize.ll
@@ -327,8 +327,8 @@ define void @tail_folded_store_avx512(ptr %start, ptr %end) #3 {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[START1:%.*]] = ptrtoaddr ptr [[START]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoaddr ptr [[END]] to i32
-; CHECK-NEXT: [[TMP8:%.*]] = sub i32 [[START1]], [[TMP4]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP8]], -72
+; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[START1]], -72
+; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP8]], [[TMP4]]
; CHECK-NEXT: [[TMP2:%.*]] = udiv i32 [[TMP1]], 72
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP2]], 1
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
@@ -362,8 +362,8 @@ define void @tail_folded_store_avx512(ptr %start, ptr %end) #3 {
; AUTOVF-NEXT: [[ENTRY:.*:]]
; AUTOVF-NEXT: [[START1:%.*]] = ptrtoaddr ptr [[START]] to i32
; AUTOVF-NEXT: [[TMP4:%.*]] = ptrtoaddr ptr [[END]] to i32
-; AUTOVF-NEXT: [[TMP8:%.*]] = sub i32 [[START1]], [[TMP4]]
-; AUTOVF-NEXT: [[TMP1:%.*]] = add i32 [[TMP8]], -72
+; AUTOVF-NEXT: [[TMP8:%.*]] = add i32 [[START1]], -72
+; AUTOVF-NEXT: [[TMP1:%.*]] = sub i32 [[TMP8]], [[TMP4]]
; AUTOVF-NEXT: [[TMP2:%.*]] = udiv i32 [[TMP1]], 72
; AUTOVF-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP2]], 1
; AUTOVF-NEXT: br label %[[VECTOR_PH:.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/X86/pr35432.ll b/llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
index 767bb38d7926f..e9a758f7b21df 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
@@ -36,8 +36,8 @@ define i32 @main(ptr %ptr) {
; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[CONV3]], -1
; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32
; CHECK-NEXT: [[UMIN1:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP0]], i32 [[TMP2]])
-; CHECK-NEXT: [[TMP11:%.*]] = sub i32 [[TMP2]], [[UMIN1]]
-; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP11]], 1
+; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP2]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP11]], [[UMIN1]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP4]], 24
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
; CHECK: vector.scevcheck:
diff --git a/llvm/test/Transforms/LoopVectorize/X86/pr48340.ll b/llvm/test/Transforms/LoopVectorize/X86/pr48340.ll
index 71d14c19aa179..64658564abfe0 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/pr48340.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/pr48340.ll
@@ -12,8 +12,8 @@ define ptr @foo(ptr %p, ptr %p.last) #0 {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[P3:%.*]] = ptrtoaddr ptr [[P:%.*]] to i64
; CHECK-NEXT: [[P_LAST1:%.*]] = ptrtoaddr ptr [[P_LAST:%.*]] to i64
-; CHECK-NEXT: [[TMP6:%.*]] = sub i64 [[P3]], [[P_LAST1]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP6]], -1024
+; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[P3]], -1024
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP6]], [[P_LAST1]]
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 10
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 16
@@ -72,8 +72,8 @@ define ptr @bar(ptr %p, ptr %p.last) #0 {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[P3:%.*]] = ptrtoaddr ptr [[P:%.*]] to i64
; CHECK-NEXT: [[P_LAST1:%.*]] = ptrtoaddr ptr [[P_LAST:%.*]] to i64
-; CHECK-NEXT: [[TMP6:%.*]] = sub i64 [[P3]], [[P_LAST1]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP6]], -1024
+; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[P3]], -1024
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP6]], [[P_LAST1]]
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 10
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 16
diff --git a/llvm/test/Transforms/LoopVectorize/X86/pr72969.ll b/llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
index de5d0887dabaf..b0545d4db7102 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
@@ -30,8 +30,8 @@ define void @test(ptr %p) {
; VEC-NEXT: [[TMP0:%.*]] = ptrtoaddr ptr [[P]] to i64
; VEC-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 16
; VEC-NEXT: [[TMP9:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP1]], i64 add (i64 ptrtoaddr (ptr @h to i64), i64 1))
-; VEC-NEXT: [[TMP15:%.*]] = sub i64 [[TMP9]], [[TMP0]]
-; VEC-NEXT: [[TMP2:%.*]] = add i64 [[TMP15]], -9
+; VEC-NEXT: [[TMP15:%.*]] = add i64 [[TMP9]], -9
+; VEC-NEXT: [[TMP2:%.*]] = sub i64 [[TMP15]], [[TMP0]]
; VEC-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; VEC-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
; VEC-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP4]], 8
diff --git a/llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll b/llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
index 1e87f60bfab20..8f9039b9db32f 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
@@ -8,8 +8,8 @@ define void @switch_default_to_latch_common_dest(ptr %start, ptr %end) {
; COST-NEXT: [[ENTRY:.*]]:
; COST-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; COST-NEXT: [[TMP11:%.*]] = ptrtoaddr ptr [[START]] to i64
-; COST-NEXT: [[TMP12:%.*]] = sub i64 [[END1]], [[TMP11]]
-; COST-NEXT: [[TMP1:%.*]] = add i64 [[TMP12]], -8
+; COST-NEXT: [[TMP12:%.*]] = add i64 [[END1]], -8
+; COST-NEXT: [[TMP1:%.*]] = sub i64 [[TMP12]], [[TMP11]]
; COST-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; COST-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; COST-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
@@ -60,8 +60,8 @@ define void @switch_default_to_latch_common_dest(ptr %start, ptr %end) {
; FORCED-NEXT: [[ENTRY:.*]]:
; FORCED-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; FORCED-NEXT: [[TMP15:%.*]] = ptrtoaddr ptr [[START]] to i64
-; FORCED-NEXT: [[TMP16:%.*]] = sub i64 [[END1]], [[TMP15]]
-; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP16]], -8
+; FORCED-NEXT: [[TMP16:%.*]] = add i64 [[END1]], -8
+; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP16]], [[TMP15]]
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
@@ -143,8 +143,8 @@ define void @switch_default_to_latch_common_dest_using_branches(ptr %start, ptr
; COST-NEXT: [[ENTRY:.*]]:
; COST-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; COST-NEXT: [[TMP13:%.*]] = ptrtoaddr ptr [[START]] to i64
-; COST-NEXT: [[TMP14:%.*]] = sub i64 [[END1]], [[TMP13]]
-; COST-NEXT: [[TMP1:%.*]] = add i64 [[TMP14]], -8
+; COST-NEXT: [[TMP14:%.*]] = add i64 [[END1]], -8
+; COST-NEXT: [[TMP1:%.*]] = sub i64 [[TMP14]], [[TMP13]]
; COST-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; COST-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; COST-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
@@ -198,8 +198,8 @@ define void @switch_default_to_latch_common_dest_using_branches(ptr %start, ptr
; FORCED-NEXT: [[ENTRY:.*]]:
; FORCED-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; FORCED-NEXT: [[TMP19:%.*]] = ptrtoaddr ptr [[START]] to i64
-; FORCED-NEXT: [[TMP20:%.*]] = sub i64 [[END1]], [[TMP19]]
-; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP20]], -8
+; FORCED-NEXT: [[TMP20:%.*]] = add i64 [[END1]], -8
+; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP20]], [[TMP19]]
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
@@ -321,8 +321,8 @@ define void @switch_all_dests_distinct(ptr %start, ptr %end) {
; FORCED-NEXT: [[ENTRY:.*]]:
; FORCED-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; FORCED-NEXT: [[TMP21:%.*]] = ptrtoaddr ptr [[START]] to i64
-; FORCED-NEXT: [[TMP22:%.*]] = sub i64 [[END1]], [[TMP21]]
-; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP22]], -8
+; FORCED-NEXT: [[TMP22:%.*]] = add i64 [[END1]], -8
+; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP22]], [[TMP21]]
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
@@ -439,8 +439,8 @@ define void @switch_all_dests_distinct_variant_using_branches(ptr %start, ptr %e
; COST-NEXT: [[ENTRY:.*]]:
; COST-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; COST-NEXT: [[TMP16:%.*]] = ptrtoaddr ptr [[START]] to i64
-; COST-NEXT: [[TMP17:%.*]] = sub i64 [[END1]], [[TMP16]]
-; COST-NEXT: [[TMP1:%.*]] = add i64 [[TMP17]], -8
+; COST-NEXT: [[TMP17:%.*]] = add i64 [[END1]], -8
+; COST-NEXT: [[TMP1:%.*]] = sub i64 [[TMP17]], [[TMP16]]
; COST-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; COST-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; COST-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
@@ -511,8 +511,8 @@ define void @switch_all_dests_distinct_variant_using_branches(ptr %start, ptr %e
; FORCED-NEXT: [[ENTRY:.*]]:
; FORCED-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; FORCED-NEXT: [[TMP25:%.*]] = ptrtoaddr ptr [[START]] to i64
-; FORCED-NEXT: [[TMP26:%.*]] = sub i64 [[END1]], [[TMP25]]
-; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP26]], -8
+; FORCED-NEXT: [[TMP26:%.*]] = add i64 [[END1]], -8
+; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP26]], [[TMP25]]
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
@@ -671,8 +671,8 @@ define void @switch_multiple_common_dests(ptr %start, ptr %end) {
; FORCED-NEXT: [[ENTRY:.*]]:
; FORCED-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; FORCED-NEXT: [[TMP29:%.*]] = ptrtoaddr ptr [[START]] to i64
-; FORCED-NEXT: [[TMP30:%.*]] = sub i64 [[END1]], [[TMP29]]
-; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP30]], -8
+; FORCED-NEXT: [[TMP30:%.*]] = add i64 [[END1]], -8
+; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP30]], [[TMP29]]
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
@@ -820,8 +820,8 @@ define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
; FORCED-NEXT: [[ENTRY:.*]]:
; FORCED-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; FORCED-NEXT: [[TMP17:%.*]] = ptrtoaddr ptr [[START]] to i64
-; FORCED-NEXT: [[TMP18:%.*]] = sub i64 [[END1]], [[TMP17]]
-; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP18]], -8
+; FORCED-NEXT: [[TMP18:%.*]] = add i64 [[END1]], -8
+; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP18]], [[TMP17]]
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
@@ -956,8 +956,8 @@ define void @switch_under_br_default_common_dest_with_case(ptr %start, ptr %end,
; FORCED-NEXT: [[ENTRY:.*]]:
; FORCED-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; FORCED-NEXT: [[TMP25:%.*]] = ptrtoaddr ptr [[START]] to i64
-; FORCED-NEXT: [[TMP26:%.*]] = sub i64 [[END1]], [[TMP25]]
-; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP26]], -8
+; FORCED-NEXT: [[TMP26:%.*]] = add i64 [[END1]], -8
+; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP26]], [[TMP25]]
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
@@ -1109,8 +1109,8 @@ define void @br_under_switch_default_common_dest_with_case(ptr %start, ptr %end,
; FORCED-NEXT: [[ENTRY:.*]]:
; FORCED-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; FORCED-NEXT: [[TMP29:%.*]] = ptrtoaddr ptr [[START]] to i64
-; FORCED-NEXT: [[TMP30:%.*]] = sub i64 [[END1]], [[TMP29]]
-; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP30]], -8
+; FORCED-NEXT: [[TMP30:%.*]] = add i64 [[END1]], -8
+; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP30]], [[TMP29]]
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
@@ -1263,8 +1263,8 @@ define void @large_number_of_cases(ptr %start, ptr %end) {
; FORCED-NEXT: [[ENTRY:.*]]:
; FORCED-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; FORCED-NEXT: [[TMP43:%.*]] = ptrtoaddr ptr [[START]] to i64
-; FORCED-NEXT: [[TMP44:%.*]] = sub i64 [[END1]], [[TMP43]]
-; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP44]], -8
+; FORCED-NEXT: [[TMP44:%.*]] = add i64 [[END1]], -8
+; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP44]], [[TMP43]]
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
diff --git a/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll b/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
index 1e649aac1329c..8d983fcb5221b 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
@@ -705,8 +705,8 @@ define void @loaded_address_used_by_load_through_blend(i64 %start, ptr noalias %
; I32-SAME: i64 [[START:%.*]], ptr noalias [[SRC:%.*]], ptr noalias [[SRC_2:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR0]] {
; I32-NEXT: [[ENTRY:.*:]]
; I32-NEXT: [[SMIN:%.*]] = call i64 @llvm.smin.i64(i64 [[START]], i64 100)
-; I32-NEXT: [[TMP92:%.*]] = sub i64 [[START]], [[SMIN]]
-; I32-NEXT: [[TMP1:%.*]] = add i64 [[TMP92]], 1
+; I32-NEXT: [[TMP92:%.*]] = add i64 [[START]], 1
+; I32-NEXT: [[TMP1:%.*]] = sub i64 [[TMP92]], [[SMIN]]
; I32-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 8
; I32-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; I32: [[VECTOR_PH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/cast-induction.ll b/llvm/test/Transforms/LoopVectorize/cast-induction.ll
index 612206e910479..edf7aaca124bc 100644
--- a/llvm/test/Transforms/LoopVectorize/cast-induction.ll
+++ b/llvm/test/Transforms/LoopVectorize/cast-induction.ll
@@ -425,8 +425,8 @@ define i64 @induction_cast_chain_cleared_by_dce(i64 %n, i64 %mask.init) {
; VF4-NEXT: [[TMP2:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 [[TMP0]])
; VF4-NEXT: [[TMP21:%.*]] = lshr i64 [[MASK_INIT]], 32
; VF4-NEXT: [[TMP22:%.*]] = mul i64 [[TMP21]], -4294967296
-; VF4-NEXT: [[SMAX1:%.*]] = add i64 [[TMP2]], [[TMP22]]
-; VF4-NEXT: [[TMP1:%.*]] = add i64 [[SMAX1]], -1
+; VF4-NEXT: [[TMP23:%.*]] = add i64 [[TMP2]], -1
+; VF4-NEXT: [[TMP1:%.*]] = add i64 [[TMP23]], [[TMP22]]
; VF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 4
; VF4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; VF4: [[VECTOR_SCEVCHECK]]:
@@ -495,8 +495,8 @@ define i64 @induction_cast_chain_cleared_by_dce(i64 %n, i64 %mask.init) {
; IC2-NEXT: [[TMP2:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 [[TMP0]])
; IC2-NEXT: [[TMP23:%.*]] = lshr i64 [[MASK_INIT]], 32
; IC2-NEXT: [[TMP24:%.*]] = mul i64 [[TMP23]], -4294967296
-; IC2-NEXT: [[SMAX1:%.*]] = add i64 [[TMP2]], [[TMP24]]
-; IC2-NEXT: [[TMP1:%.*]] = add i64 [[SMAX1]], -1
+; IC2-NEXT: [[TMP25:%.*]] = add i64 [[TMP2]], -1
+; IC2-NEXT: [[TMP1:%.*]] = add i64 [[TMP25]], [[TMP24]]
; IC2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 2
; IC2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; IC2: [[VECTOR_SCEVCHECK]]:
diff --git a/llvm/test/Transforms/LoopVectorize/expand-ptrtoaddr.ll b/llvm/test/Transforms/LoopVectorize/expand-ptrtoaddr.ll
index 249b7d826040a..b374e24cf86ae 100644
--- a/llvm/test/Transforms/LoopVectorize/expand-ptrtoaddr.ll
+++ b/llvm/test/Transforms/LoopVectorize/expand-ptrtoaddr.ll
@@ -7,8 +7,8 @@ define void @test_ptrtoaddr_tripcount(ptr %start, ptr %end) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[START_ADDR:%.*]] = ptrtoaddr ptr [[START]] to i64
; CHECK-NEXT: [[END_ADDR:%.*]] = ptrtoaddr ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[END_ADDR]], [[START_ADDR]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 1
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END_ADDR]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START_ADDR]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll b/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
index d65625fb7ca74..0edba19738e7c 100644
--- a/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
+++ b/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
@@ -505,8 +505,8 @@ define i64 @findlast_expr_flipped_select_anyof(ptr %a, ptr %b, i64 %rdx.start, i
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[N]], i64 1)
-; CHECK-NEXT: [[TMP18:%.*]] = sub i64 [[N]], [[UMIN]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP18]], 1
+; CHECK-NEXT: [[TMP18:%.*]] = add i64 [[N]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP18]], [[UMIN]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP1]], 3
diff --git a/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll b/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
index 9edf48e1373bf..db0cbf8997c48 100644
--- a/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
+++ b/llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
@@ -701,8 +701,8 @@ define i64 @findlast_expr_flipped_select_anyof(ptr %a, ptr %b, i64 %rdx.start, i
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.umin.i64(i64 [[N]], i64 1)
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[N]], [[TMP0]]
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[N]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], [[TMP0]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/find-last.ll b/llvm/test/Transforms/LoopVectorize/find-last.ll
index 0bcd18c089e9c..691980d50c2bf 100644
--- a/llvm/test/Transforms/LoopVectorize/find-last.ll
+++ b/llvm/test/Transforms/LoopVectorize/find-last.ll
@@ -204,8 +204,8 @@ define i32 @loop_inv_select_condition_issue_182152(i32 %iv.start, i32 %a, i32 %b
; CHECK-NEXT: entry:
; CHECK-NEXT: [[INV_COND:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[IV_START:%.*]], i32 1)
-; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[SMAX]], [[IV_START]]
-; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP1]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[SMAX]], 1
+; CHECK-NEXT: [[TMP11:%.*]] = sub i32 [[TMP1]], [[IV_START]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP11]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
index d7de070feb66e..17e34d8fa0d33 100644
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
+++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
@@ -2599,8 +2599,8 @@ define i32 @sink_into_replication_region(i32 %y) {
; UNROLL-NO-IC-SAME: i32 [[Y:%.*]]) {
; UNROLL-NO-IC-NEXT: [[BB:.*:]]
; UNROLL-NO-IC-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[Y]], i32 1)
-; UNROLL-NO-IC-NEXT: [[TMP5:%.*]] = sub i32 [[Y]], [[SMIN]]
-; UNROLL-NO-IC-NEXT: [[TMP1:%.*]] = add i32 [[TMP5]], 1
+; UNROLL-NO-IC-NEXT: [[TMP5:%.*]] = add i32 [[Y]], 1
+; UNROLL-NO-IC-NEXT: [[TMP1:%.*]] = sub i32 [[TMP5]], [[SMIN]]
; UNROLL-NO-IC-NEXT: br label %[[VECTOR_PH:.*]]
; UNROLL-NO-IC: [[VECTOR_PH]]:
; UNROLL-NO-IC-NEXT: [[N_RND_UP:%.*]] = add i32 [[TMP1]], 7
@@ -2712,8 +2712,8 @@ define i32 @sink_into_replication_region(i32 %y) {
; UNROLL-NO-VF-SAME: i32 [[Y:%.*]]) {
; UNROLL-NO-VF-NEXT: [[BB:.*:]]
; UNROLL-NO-VF-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[Y]], i32 1)
-; UNROLL-NO-VF-NEXT: [[TMP4:%.*]] = sub i32 [[Y]], [[SMIN]]
-; UNROLL-NO-VF-NEXT: [[TMP1:%.*]] = add i32 [[TMP4]], 1
+; UNROLL-NO-VF-NEXT: [[TMP4:%.*]] = add i32 [[Y]], 1
+; UNROLL-NO-VF-NEXT: [[TMP1:%.*]] = sub i32 [[TMP4]], [[SMIN]]
; UNROLL-NO-VF-NEXT: br label %[[VECTOR_PH:.*]]
; UNROLL-NO-VF: [[VECTOR_PH]]:
; UNROLL-NO-VF-NEXT: [[N_RND_UP:%.*]] = add i32 [[TMP1]], 1
@@ -2761,8 +2761,8 @@ define i32 @sink_into_replication_region(i32 %y) {
; SINK-AFTER-SAME: i32 [[Y:%.*]]) {
; SINK-AFTER-NEXT: [[BB:.*:]]
; SINK-AFTER-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[Y]], i32 1)
-; SINK-AFTER-NEXT: [[TMP4:%.*]] = sub i32 [[Y]], [[SMIN]]
-; SINK-AFTER-NEXT: [[TMP1:%.*]] = add i32 [[TMP4]], 1
+; SINK-AFTER-NEXT: [[TMP4:%.*]] = add i32 [[Y]], 1
+; SINK-AFTER-NEXT: [[TMP1:%.*]] = sub i32 [[TMP4]], [[SMIN]]
; SINK-AFTER-NEXT: br label %[[VECTOR_PH:.*]]
; SINK-AFTER: [[VECTOR_PH]]:
; SINK-AFTER-NEXT: [[N_RND_UP:%.*]] = add i32 [[TMP1]], 3
@@ -2852,8 +2852,8 @@ define i32 @sink_into_replication_region_multiple(ptr %x, i32 %y) {
; UNROLL-NO-IC-SAME: ptr [[X:%.*]], i32 [[Y:%.*]]) {
; UNROLL-NO-IC-NEXT: [[BB:.*:]]
; UNROLL-NO-IC-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[Y]], i32 1)
-; UNROLL-NO-IC-NEXT: [[TMP2:%.*]] = sub i32 [[Y]], [[SMIN]]
-; UNROLL-NO-IC-NEXT: [[TMP1:%.*]] = add i32 [[TMP2]], 1
+; UNROLL-NO-IC-NEXT: [[TMP2:%.*]] = add i32 [[Y]], 1
+; UNROLL-NO-IC-NEXT: [[TMP1:%.*]] = sub i32 [[TMP2]], [[SMIN]]
; UNROLL-NO-IC-NEXT: br label %[[VECTOR_PH:.*]]
; UNROLL-NO-IC: [[VECTOR_PH]]:
; UNROLL-NO-IC-NEXT: [[N_RND_UP:%.*]] = add i32 [[TMP1]], 7
@@ -3021,8 +3021,8 @@ define i32 @sink_into_replication_region_multiple(ptr %x, i32 %y) {
; UNROLL-NO-VF-SAME: ptr [[X:%.*]], i32 [[Y:%.*]]) {
; UNROLL-NO-VF-NEXT: [[BB:.*:]]
; UNROLL-NO-VF-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[Y]], i32 1)
-; UNROLL-NO-VF-NEXT: [[TMP2:%.*]] = sub i32 [[Y]], [[SMIN]]
-; UNROLL-NO-VF-NEXT: [[TMP1:%.*]] = add i32 [[TMP2]], 1
+; UNROLL-NO-VF-NEXT: [[TMP2:%.*]] = add i32 [[Y]], 1
+; UNROLL-NO-VF-NEXT: [[TMP1:%.*]] = sub i32 [[TMP2]], [[SMIN]]
; UNROLL-NO-VF-NEXT: br label %[[VECTOR_PH:.*]]
; UNROLL-NO-VF: [[VECTOR_PH]]:
; UNROLL-NO-VF-NEXT: [[N_RND_UP:%.*]] = add i32 [[TMP1]], 1
@@ -3082,8 +3082,8 @@ define i32 @sink_into_replication_region_multiple(ptr %x, i32 %y) {
; SINK-AFTER-SAME: ptr [[X:%.*]], i32 [[Y:%.*]]) {
; SINK-AFTER-NEXT: [[BB:.*:]]
; SINK-AFTER-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[Y]], i32 1)
-; SINK-AFTER-NEXT: [[TMP2:%.*]] = sub i32 [[Y]], [[SMIN]]
-; SINK-AFTER-NEXT: [[TMP1:%.*]] = add i32 [[TMP2]], 1
+; SINK-AFTER-NEXT: [[TMP2:%.*]] = add i32 [[Y]], 1
+; SINK-AFTER-NEXT: [[TMP1:%.*]] = sub i32 [[TMP2]], [[SMIN]]
; SINK-AFTER-NEXT: br label %[[VECTOR_PH:.*]]
; SINK-AFTER: [[VECTOR_PH]]:
; SINK-AFTER-NEXT: [[N_RND_UP:%.*]] = add i32 [[TMP1]], 3
diff --git a/llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll b/llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll
index 9afd6ca0cd583..22395df8df40b 100644
--- a/llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll
+++ b/llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll
@@ -211,9 +211,9 @@ define void @load_store_noalias_via_tbaa(ptr %p, ptr %q, ptr %n) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[P6:%.*]] = ptrtoaddr ptr [[P]] to i64
; CHECK-NEXT: [[N5:%.*]] = ptrtoaddr ptr [[N]] to i64
-; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[P6]], -3074457345618258603
; CHECK-NEXT: [[TMP17:%.*]] = mul i64 [[N5]], 3074457345618258603
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], [[TMP17]]
+; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[P6]], -3074457345618258603
+; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP17]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 2
; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP4]], 4
diff --git a/llvm/test/Transforms/LoopVectorize/if-conversion.ll b/llvm/test/Transforms/LoopVectorize/if-conversion.ll
index e66c1ba55cec9..948746df3f580 100644
--- a/llvm/test/Transforms/LoopVectorize/if-conversion.ll
+++ b/llvm/test/Transforms/LoopVectorize/if-conversion.ll
@@ -25,8 +25,8 @@ define void @function0(ptr nocapture %a, ptr nocapture %b, i32 %start, i32 %end)
; CHECK-NEXT: br i1 [[CMP16]], label %[[FOR_BODY_LR_PH:.*]], label %[[FOR_END:.*]]
; CHECK: [[FOR_BODY_LR_PH]]:
; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[START]] to i64
-; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[END]], [[START]]
-; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[END]], -1
+; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], [[START]]
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP4]], 4
@@ -245,8 +245,8 @@ define void @PR34523(ptr %p, i16 %val) {
; CHECK-NEXT: [[BB1:.*]]:
; CHECK-NEXT: [[TMP0:%.*]] = add i16 [[VAL]], 1
; CHECK-NEXT: [[SMAX:%.*]] = call i16 @llvm.smax.i16(i16 [[TMP0]], i16 2)
-; CHECK-NEXT: [[TMP7:%.*]] = sub i16 [[SMAX]], [[VAL]]
-; CHECK-NEXT: [[TMP2:%.*]] = add i16 [[TMP7]], -1
+; CHECK-NEXT: [[TMP7:%.*]] = add i16 [[SMAX]], -1
+; CHECK-NEXT: [[TMP2:%.*]] = sub i16 [[TMP7]], [[VAL]]
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP2]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i32 [[TMP3]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP4]], 4
diff --git a/llvm/test/Transforms/LoopVectorize/induction-ptrcasts.ll b/llvm/test/Transforms/LoopVectorize/induction-ptrcasts.ll
index dde4c4d73fd61..3faf077880178 100644
--- a/llvm/test/Transforms/LoopVectorize/induction-ptrcasts.ll
+++ b/llvm/test/Transforms/LoopVectorize/induction-ptrcasts.ll
@@ -9,8 +9,7 @@ define void @int_iv_based_on_pointer_iv(ptr %A) {
; VF1-SAME: ptr [[A:%.*]]) {
; VF1-NEXT: [[ENTRY:.*:]]
; VF1-NEXT: [[SMIN:%.*]] = call i64 @llvm.smin.i64(i64 add (i64 ptrtoaddr (ptr @f to i64), i64 -4), i64 0)
-; VF1-NEXT: [[TMP6:%.*]] = sub i64 ptrtoaddr (ptr @f to i64), [[SMIN]]
-; VF1-NEXT: [[TMP0:%.*]] = add i64 [[TMP6]], -1
+; VF1-NEXT: [[TMP0:%.*]] = sub i64 add (i64 ptrtoaddr (ptr @f to i64), i64 -1), [[SMIN]]
; VF1-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 2
; VF1-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
; VF1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 2
@@ -41,8 +40,7 @@ define void @int_iv_based_on_pointer_iv(ptr %A) {
; VF2-SAME: ptr [[A:%.*]]) {
; VF2-NEXT: [[ENTRY:.*:]]
; VF2-NEXT: [[SMIN:%.*]] = call i64 @llvm.smin.i64(i64 add (i64 ptrtoaddr (ptr @f to i64), i64 -4), i64 0)
-; VF2-NEXT: [[TMP7:%.*]] = sub i64 ptrtoaddr (ptr @f to i64), [[SMIN]]
-; VF2-NEXT: [[TMP0:%.*]] = add i64 [[TMP7]], -1
+; VF2-NEXT: [[TMP0:%.*]] = sub i64 add (i64 ptrtoaddr (ptr @f to i64), i64 -1), [[SMIN]]
; VF2-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 2
; VF2-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
; VF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 2
diff --git a/llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll b/llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
index 3067970b929b9..df243aea6bbde 100644
--- a/llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
+++ b/llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
@@ -78,8 +78,8 @@ define void @ir_tbaa_different(ptr %base, ptr %end, ptr %src) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[BASE2:%.*]] = ptrtoaddr ptr [[BASE]] to i64
; CHECK-NEXT: [[END2:%.*]] = ptrtoaddr ptr [[END]] to i64
-; CHECK-NEXT: [[TMP16:%.*]] = sub i64 [[END2]], [[BASE2]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP16]], -8
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END2]], -8
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[BASE2]]
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
@@ -169,8 +169,8 @@ define void @noalias_metadata_from_versioning(ptr %base, ptr %end, ptr %src) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = ptrtoaddr ptr [[BASE]] to i64
-; CHECK-NEXT: [[TMP11:%.*]] = sub i64 [[END1]], [[TMP10]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP11]], -8
+; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[END1]], -8
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP11]], [[TMP10]]
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
diff --git a/llvm/test/Transforms/LoopVectorize/invalidate-scev-at-scope-after-vectorization.ll b/llvm/test/Transforms/LoopVectorize/invalidate-scev-at-scope-after-vectorization.ll
index f95b4b21978b7..90243af5e3fce 100644
--- a/llvm/test/Transforms/LoopVectorize/invalidate-scev-at-scope-after-vectorization.ll
+++ b/llvm/test/Transforms/LoopVectorize/invalidate-scev-at-scope-after-vectorization.ll
@@ -34,8 +34,8 @@ define void @test_invalidate_scevs_at_scope(ptr %p) {
; CHECK-NEXT: [[ADD_LCSSA1:%.*]] = phi i32 [ [[ADD_1]], %[[LOOP_1]] ]
; CHECK-NEXT: [[ADD_LCSSA:%.*]] = add i32 [[TMP4]], 100
; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[ADD_LCSSA]], i32 100)
-; CHECK-NEXT: [[TMP5:%.*]] = sub i32 [[SMAX]], [[TMP4]]
-; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP5]], -100
+; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[SMAX]], -100
+; CHECK-NEXT: [[TMP8:%.*]] = sub i32 [[TMP5]], [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = add nuw nsw i64 [[TMP6]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP7]], 4
diff --git a/llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll b/llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
index 578cbb7959cff..3929994915bf4 100644
--- a/llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
+++ b/llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
@@ -356,6 +356,7 @@ define void @multiple_uniform_stores(ptr nocapture %var1, ptr nocapture readonly
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[VAR1:%.*]], i64 [[TMP3]]
; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[VAR2:%.*]], i64 4
; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[ITR]], -1
+; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[ITR]], -1
; CHECK-NEXT: br label [[FOR_COND1_PREHEADER:%.*]]
; CHECK: for.cond1.preheader:
; CHECK-NEXT: [[INDVARS_IV23:%.*]] = phi i64 [ [[INDVARS_IV_NEXT24:%.*]], [[FOR_INC8:%.*]] ], [ 0, [[FOR_COND1_PREHEADER_PREHEADER]] ]
@@ -366,8 +367,7 @@ define void @multiple_uniform_stores(ptr nocapture %var1, ptr nocapture readonly
; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, ptr [[VAR1]], i64 [[INDVARS_IV23]]
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[J_022]] to i64
; CHECK-NEXT: [[ARRAYIDX5_PROMOTED:%.*]] = load i32, ptr [[ARRAYIDX5]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = sub i32 [[ITR]], [[J_022]]
-; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP10]], -1
+; CHECK-NEXT: [[TMP6:%.*]] = sub i32 [[TMP10]], [[J_022]]
; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = add nuw nsw i64 [[TMP7]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP8]], 4
diff --git a/llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll b/llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
index dca1b333799f8..83d5615e500c9 100644
--- a/llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
+++ b/llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
@@ -1106,8 +1106,8 @@ define i64 @select_decreasing_induction_icmp_non_const_start(ptr %a, ptr %b, i64
; IC1VF4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) {
; IC1VF4-NEXT: [[ENTRY:.*]]:
; IC1VF4-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[N]], i64 1)
-; IC1VF4-NEXT: [[TMP6:%.*]] = sub i64 [[N]], [[UMIN]]
-; IC1VF4-NEXT: [[TMP1:%.*]] = add i64 [[TMP6]], 1
+; IC1VF4-NEXT: [[TMP6:%.*]] = add i64 [[N]], 1
+; IC1VF4-NEXT: [[TMP1:%.*]] = sub i64 [[TMP6]], [[UMIN]]
; IC1VF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 4
; IC1VF4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; IC1VF4: [[VECTOR_PH]]:
@@ -1172,8 +1172,8 @@ define i64 @select_decreasing_induction_icmp_non_const_start(ptr %a, ptr %b, i64
; IC4VF4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) {
; IC4VF4-NEXT: [[ENTRY:.*]]:
; IC4VF4-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[N]], i64 1)
-; IC4VF4-NEXT: [[TMP6:%.*]] = sub i64 [[N]], [[UMIN]]
-; IC4VF4-NEXT: [[TMP1:%.*]] = add i64 [[TMP6]], 1
+; IC4VF4-NEXT: [[TMP6:%.*]] = add i64 [[N]], 1
+; IC4VF4-NEXT: [[TMP1:%.*]] = sub i64 [[TMP6]], [[UMIN]]
; IC4VF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; IC4VF4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; IC4VF4: [[VECTOR_PH]]:
@@ -1280,8 +1280,8 @@ define i64 @select_decreasing_induction_icmp_non_const_start(ptr %a, ptr %b, i64
; IC4VF1-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) {
; IC4VF1-NEXT: [[ENTRY:.*]]:
; IC4VF1-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[N]], i64 1)
-; IC4VF1-NEXT: [[TMP6:%.*]] = sub i64 [[N]], [[UMIN]]
-; IC4VF1-NEXT: [[TMP1:%.*]] = add i64 [[TMP6]], 1
+; IC4VF1-NEXT: [[TMP6:%.*]] = add i64 [[N]], 1
+; IC4VF1-NEXT: [[TMP1:%.*]] = sub i64 [[TMP6]], [[UMIN]]
; IC4VF1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 4
; IC4VF1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[EXIT:.*]], label %[[VECTOR_PH:.*]]
; IC4VF1: [[VECTOR_PH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll b/llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll
index c08829e535c7d..21b9c3f5226d2 100644
--- a/llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll
+++ b/llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll
@@ -65,8 +65,8 @@ define i64 @select_decreasing_induction_icmp_non_const_start(ptr %a, ptr %b, i64
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[N]], i64 1)
-; CHECK-NEXT: [[TMP4:%.*]] = sub i64 [[N]], [[UMIN]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[N]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP4]], [[UMIN]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP1]], 3
diff --git a/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll b/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
index a21ae3c1de17e..ea41682f00e08 100644
--- a/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
+++ b/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
@@ -324,8 +324,8 @@ define void @PR30742(ptr %p) {
; CHECK-NEXT: [[TMP04:%.*]] = add nsw i32 [[TMP03]], -7
; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 [[TMP03]], -15
; CHECK-NEXT: [[SMIN1:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 0)
-; CHECK-NEXT: [[TMP9:%.*]] = sub i32 [[TMP03]], [[SMIN1]]
-; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP9]], -8
+; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP03]], -8
+; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[TMP7]], [[SMIN1]]
; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i32 [[TMP3]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK4:%.*]] = icmp ult i32 [[TMP4]], 2
@@ -361,8 +361,8 @@ define void @PR30742(ptr %p) {
; CHECK-NEXT: [[TMP12:%.*]] = add nsw i32 [[TMP11]], -7
; CHECK-NEXT: [[TMP8:%.*]] = add nsw i32 [[TMP11]], -15
; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP8]], i32 0)
-; CHECK-NEXT: [[TMP19:%.*]] = sub i32 [[TMP11]], [[SMIN]]
-; CHECK-NEXT: [[TMP21:%.*]] = add i32 [[TMP19]], -8
+; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP11]], -8
+; CHECK-NEXT: [[TMP21:%.*]] = sub i32 [[TMP18]], [[SMIN]]
; CHECK-NEXT: [[TMP20:%.*]] = lshr i32 [[TMP21]], 3
; CHECK-NEXT: [[TMP14:%.*]] = add nuw nsw i32 [[TMP20]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP14]], 2
diff --git a/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll b/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
index e72eb45be8a70..16f53642aeae8 100644
--- a/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
+++ b/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
@@ -80,11 +80,10 @@ define void @pr49900(i32 %x, ptr %ptr) {
; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ 0, %[[LOOP_1_PH]] ], [ [[IV_3_NEXT_LCSSA:%.*]], %[[LOOP_1_LATCH:.*]] ]
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[IV_1]], 12
; CHECK-NEXT: [[SMAX2:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP0]], i32 65537)
-; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[SMAX2]], [[IV_1]]
-; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP3]], -12
+; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[SMAX2]], -12
+; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[TMP3]], [[IV_1]]
; CHECK-NEXT: [[UMIN3:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP2]], i32 1)
-; CHECK-NEXT: [[TMP10:%.*]] = sub i32 [[TMP3]], [[UMIN3]]
-; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP10]], -12
+; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP2]], [[UMIN3]]
; CHECK-NEXT: [[TMP5:%.*]] = udiv i32 [[TMP4]], 13
; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[UMIN3]], [[TMP5]]
; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP12]], 1
@@ -119,11 +118,10 @@ define void @pr49900(i32 %x, ptr %ptr) {
; CHECK-NEXT: [[IV_2_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_2_NEXT]], %[[LOOP_2]] ], [ [[TMP8]], %[[MIDDLE_BLOCK12]] ]
; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[IV_1]], 12
; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP11]], i32 65537)
-; CHECK-NEXT: [[TMP19:%.*]] = sub i32 [[SMAX]], [[IV_1]]
-; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP19]], -12
+; CHECK-NEXT: [[TMP19:%.*]] = add i32 [[SMAX]], -12
+; CHECK-NEXT: [[TMP13:%.*]] = sub i32 [[TMP19]], [[IV_1]]
; CHECK-NEXT: [[UMIN:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP13]], i32 1)
-; CHECK-NEXT: [[TMP22:%.*]] = sub i32 [[TMP19]], [[UMIN]]
-; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP22]], -12
+; CHECK-NEXT: [[TMP14:%.*]] = sub i32 [[TMP13]], [[UMIN]]
; CHECK-NEXT: [[TMP15:%.*]] = udiv i32 [[TMP14]], 13
; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[UMIN]], [[TMP15]]
; CHECK-NEXT: [[TMP17:%.*]] = mul i32 [[TMP16]], 13
@@ -131,14 +129,13 @@ define void @pr49900(i32 %x, ptr %ptr) {
; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP30]], 26
; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP18]], i32 65536)
; CHECK-NEXT: [[TMP31:%.*]] = mul i32 [[TMP16]], -13
-; CHECK-NEXT: [[TMP20:%.*]] = sub i32 [[UMAX]], [[IV_1]]
+; CHECK-NEXT: [[TMP34:%.*]] = add i32 [[UMAX]], -26
+; CHECK-NEXT: [[TMP20:%.*]] = sub i32 [[TMP34]], [[IV_1]]
; CHECK-NEXT: [[TMP33:%.*]] = add i32 [[TMP20]], [[TMP31]]
-; CHECK-NEXT: [[TMP21:%.*]] = add i32 [[TMP33]], -26
-; CHECK-NEXT: [[UMIN1:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP21]], i32 1)
+; CHECK-NEXT: [[UMIN1:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP33]], i32 1)
; CHECK-NEXT: [[TMP23:%.*]] = sub i32 [[TMP20]], [[UMIN1]]
; CHECK-NEXT: [[TMP32:%.*]] = add i32 [[TMP23]], [[TMP31]]
-; CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP32]], -26
-; CHECK-NEXT: [[TMP25:%.*]] = udiv i32 [[TMP24]], 13
+; CHECK-NEXT: [[TMP25:%.*]] = udiv i32 [[TMP32]], 13
; CHECK-NEXT: [[TMP35:%.*]] = add i32 [[UMIN1]], [[TMP25]]
; CHECK-NEXT: [[TMP26:%.*]] = add i32 [[TMP35]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP26]], 4
diff --git a/llvm/test/Transforms/LoopVectorize/opaque-ptr.ll b/llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
index d28737fe39489..37dd2afb7da4c 100644
--- a/llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
+++ b/llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
@@ -6,8 +6,8 @@ define void @test_ptr_iv_no_inbounds(ptr %p1.start, ptr %p2.start, ptr %p1.end)
; CHECK-NEXT: entry:
; CHECK-NEXT: [[P1_END1:%.*]] = ptrtoaddr ptr [[P1_END:%.*]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = ptrtoaddr ptr [[P1_START:%.*]] to i64
-; CHECK-NEXT: [[TMP14:%.*]] = sub i64 [[TMP8]], [[P1_END1]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP14]], -4
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[TMP8]], -4
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[P1_END1]]
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 2
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
@@ -94,8 +94,8 @@ define void @test_ptr_iv_with_inbounds(ptr %p1.start, ptr %p2.start, ptr %p1.end
; CHECK-NEXT: entry:
; CHECK-NEXT: [[P1_END1:%.*]] = ptrtoaddr ptr [[P1_END:%.*]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoaddr ptr [[P1_START:%.*]] to i64
-; CHECK-NEXT: [[TMP10:%.*]] = sub i64 [[TMP4]], [[P1_END1]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP10]], -4
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[TMP4]], -4
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[P1_END1]]
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 2
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
@@ -175,8 +175,8 @@ define void @store_pointer_induction(ptr %start, ptr %end) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[START2:%.*]] = ptrtoaddr ptr [[START:%.*]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END:%.*]] to i64
-; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[START2]], [[END1]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], -8
+; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[START2]], -8
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP9]], [[END1]]
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
diff --git a/llvm/test/Transforms/LoopVectorize/pr37248.ll b/llvm/test/Transforms/LoopVectorize/pr37248.ll
index 8fc09b2dbb2ba..45540d86f54a2 100644
--- a/llvm/test/Transforms/LoopVectorize/pr37248.ll
+++ b/llvm/test/Transforms/LoopVectorize/pr37248.ll
@@ -17,8 +17,8 @@ define void @f1(ptr noalias %b, i1 %c, i32 %start) {
; CHECK-SAME: ptr noalias [[B:%.*]], i1 [[C:%.*]], i32 [[START:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[SMIN1:%.*]] = call i32 @llvm.smin.i32(i32 [[START]], i32 1)
-; CHECK-NEXT: [[TMP0:%.*]] = sub i32 [[START]], [[SMIN1]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 1
+; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[START]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP7]], [[SMIN1]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 2
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
@@ -90,8 +90,8 @@ define void @f2(ptr noalias %b, i1 %c, i32 %start) {
; CHECK-SAME: ptr noalias [[B:%.*]], i1 [[C:%.*]], i32 [[START:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[SMIN1:%.*]] = call i32 @llvm.smin.i32(i32 [[START]], i32 1)
-; CHECK-NEXT: [[TMP0:%.*]] = sub i32 [[START]], [[SMIN1]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 1
+; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[START]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP7]], [[SMIN1]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 2
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
diff --git a/llvm/test/Transforms/LoopVectorize/pr45259.ll b/llvm/test/Transforms/LoopVectorize/pr45259.ll
index 361ebbe201bf6..75e21c0be9b0d 100644
--- a/llvm/test/Transforms/LoopVectorize/pr45259.ll
+++ b/llvm/test/Transforms/LoopVectorize/pr45259.ll
@@ -15,8 +15,8 @@ define i8 @widget(ptr %arr, i8 %t9) {
; CHECK-NEXT: br i1 [[C]], label [[FOR_PREHEADER:%.*]], label [[BB6]]
; CHECK: for.preheader:
; CHECK-NEXT: [[T1_0_LCSSA1:%.*]] = phi ptr [ [[T1_0]], [[BB6]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[ARR1]] to i32
; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[T1_0_LCSSA2]] to i32
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[ARR1]] to i32
; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP16]], [[TMP1]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP3]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/pr58811-scev-expansion.ll b/llvm/test/Transforms/LoopVectorize/pr58811-scev-expansion.ll
index c3b17ec128234..8d1b7ec5b574b 100644
--- a/llvm/test/Transforms/LoopVectorize/pr58811-scev-expansion.ll
+++ b/llvm/test/Transforms/LoopVectorize/pr58811-scev-expansion.ll
@@ -344,8 +344,8 @@ define void @test3_pr58811(ptr %dst) {
; VF2-NEXT: [[ADD101_LCSSA:%.*]] = phi i32 [ [[ADD101]], %[[LOOP_2]] ]
; VF2-NEXT: [[TMP0:%.*]] = udiv i32 1, [[P_1]]
; VF2-NEXT: [[TMP1:%.*]] = mul nuw i32 [[P_1]], [[TMP0]]
-; VF2-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], [[P_2]]
-; VF2-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], -1
+; VF2-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -1
+; VF2-NEXT: [[TMP3:%.*]] = sub i32 [[TMP2]], [[P_2]]
; VF2-NEXT: br label %[[VECTOR_PH:.*]]
; VF2: [[VECTOR_PH]]:
; VF2-NEXT: [[TMP15:%.*]] = mul i32 198, [[TMP3]]
@@ -405,8 +405,8 @@ define void @test3_pr58811(ptr %dst) {
; CHECK-NEXT: [[ADD101_LCSSA:%.*]] = phi i32 [ [[ADD101]], %[[LOOP_2]] ]
; CHECK-NEXT: [[TMP0:%.*]] = udiv i32 1, [[P_1]]
; CHECK-NEXT: [[TMP1:%.*]] = mul nuw i32 [[P_1]], [[TMP0]]
-; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], [[P_2]]
-; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], -1
+; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -1
+; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP2]], [[P_2]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[IND_END:%.*]] = mul i32 196, [[TMP3]]
diff --git a/llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll b/llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll
index d85a53d53ca96..7a080f305ead6 100644
--- a/llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll
+++ b/llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll
@@ -73,8 +73,8 @@ define void @widen_ptr_induction_dbg(ptr %start, ptr %end) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[TMP0:%.*]] = ptrtoaddr ptr [[END]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = ptrtoaddr ptr [[START]] to i64
-; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP0]], [[TMP1]]
-; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], -8
+; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP0]], -8
+; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[TMP2]], [[TMP1]]
; CHECK-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP3]], 3
; CHECK-NEXT: [[TMP5:%.*]] = add nuw nsw i64 [[TMP4]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP5]], 4
@@ -115,8 +115,8 @@ define void @widen_ptr_induction_dbg(ptr %start, ptr %end) {
; DEBUGLOC-NEXT: [[ENTRY:.*]]:
; DEBUGLOC-NEXT: [[TMP0:%.*]] = ptrtoaddr ptr [[END]] to i64, !dbg [[DBG34:![0-9]+]]
; DEBUGLOC-NEXT: [[TMP1:%.*]] = ptrtoaddr ptr [[START]] to i64, !dbg [[DBG34]]
-; DEBUGLOC-NEXT: [[TMP2:%.*]] = sub i64 [[TMP0]], [[TMP1]], !dbg [[DBG34]]
-; DEBUGLOC-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], -8, !dbg [[DBG34]]
+; DEBUGLOC-NEXT: [[TMP2:%.*]] = add i64 [[TMP0]], -8, !dbg [[DBG34]]
+; DEBUGLOC-NEXT: [[TMP3:%.*]] = sub i64 [[TMP2]], [[TMP1]], !dbg [[DBG34]]
; DEBUGLOC-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP3]], 3, !dbg [[DBG34]]
; DEBUGLOC-NEXT: [[TMP5:%.*]] = add nuw nsw i64 [[TMP4]], 1, !dbg [[DBG34]]
; DEBUGLOC-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP5]], 4, !dbg [[DBG34]]
diff --git a/llvm/test/Transforms/LoopVectorize/reduction-minmax-users-and-predicated.ll b/llvm/test/Transforms/LoopVectorize/reduction-minmax-users-and-predicated.ll
index f933f42ce0c0e..9dc76f92c31ca 100644
--- a/llvm/test/Transforms/LoopVectorize/reduction-minmax-users-and-predicated.ll
+++ b/llvm/test/Transforms/LoopVectorize/reduction-minmax-users-and-predicated.ll
@@ -507,8 +507,8 @@ define i32 @smax_reduction_multiple_incoming(ptr %src, i32 %n, i1 %cond) {
; CHECK: [[LOOP_HEADER_PREHEADER]]:
; CHECK-NEXT: [[IV_PH:%.*]] = phi i32 [ 10, %[[ELSE]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: [[MAX_PH:%.*]] = phi i32 [ 5, %[[ELSE]] ], [ 0, %[[ENTRY]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = sub i32 [[N]], [[IV_PH]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 1
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[IV_PH]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
diff --git a/llvm/test/Transforms/LoopVectorize/reduction-small-size.ll b/llvm/test/Transforms/LoopVectorize/reduction-small-size.ll
index ed08731f92c3b..592c60a40bf6f 100644
--- a/llvm/test/Transforms/LoopVectorize/reduction-small-size.ll
+++ b/llvm/test/Transforms/LoopVectorize/reduction-small-size.ll
@@ -172,8 +172,8 @@ define i32 @PR35734(i32 %x, i32 %y) {
; CHECK-LABEL: @PR35734(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 78)
-; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[SMAX]], [[X]]
-; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP1]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[SMAX]], 1
+; CHECK-NEXT: [[TMP8:%.*]] = sub i32 [[TMP1]], [[X]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP8]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
diff --git a/llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll b/llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
index 87536c693660e..6340a44d8bb37 100644
--- a/llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
+++ b/llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
@@ -11,8 +11,8 @@ define void @test_runtime_check_known_false_after_construction(ptr %start.1, ptr
; CHECK-NEXT: [[START_2_INT:%.*]] = ptrtoint ptr [[GEP_START_2]] to i64
; CHECK-NEXT: [[DIFF:%.*]] = sub i64 [[START_1_INT]], [[START_2_INT]]
; CHECK-NEXT: [[START_2_DIFF:%.*]] = getelementptr i8, ptr [[START_2]], i64 [[DIFF]]
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[END1]], [[START_1_INT]]
-; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP1]], 8
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 8
+; CHECK-NEXT: [[TMP12:%.*]] = sub i64 [[TMP0]], [[START_1_INT]]
; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP12]], 2305843009213693951
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/runtime-checks-difference.ll b/llvm/test/Transforms/LoopVectorize/runtime-checks-difference.ll
index 1c1f483834f50..f91cfbc686ac0 100644
--- a/llvm/test/Transforms/LoopVectorize/runtime-checks-difference.ll
+++ b/llvm/test/Transforms/LoopVectorize/runtime-checks-difference.ll
@@ -509,12 +509,12 @@ define void @diff_check_via_i32_ptrarith(ptr %origin, ptr %dst, ptr %base, i32 %
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[OP]], [[N]]
; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP_PH:.*]], [[EXIT:label %.*]]
; CHECK: [[LOOP_PH]]:
-; CHECK-NEXT: [[TMP9:%.*]] = trunc i64 [[LHS]] to i32
; CHECK-NEXT: [[TMP11:%.*]] = trunc i64 [[RHS]] to i32
-; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[D]], [[TMP9]]
-; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP2]], [[TMP11]]
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS]] to i32
+; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[D]], [[TMP11]]
; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP14]], -1
-; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
+; CHECK-NEXT: [[TMP7:%.*]] = sub i32 [[TMP4]], [[TMP1]]
+; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP7]] to i64
; CHECK-NEXT: [[TMP6:%.*]] = add nuw nsw i64 [[TMP5]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP6]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], [[SCALAR_PH:label %.*]], label %[[VECTOR_MEMCHECK:.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll b/llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
index 7222760ad1e7b..a254043798280 100644
--- a/llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
+++ b/llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
@@ -126,8 +126,8 @@ define void @implied_wrap_predicate(ptr %A, ptr %B, ptr %C) {
; CHECK-NEXT: [[A3:%.*]] = ptrtoaddr ptr [[A]] to i64
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[A3]], 16
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP0]], i64 add (i64 ptrtoaddr (ptr @h to i64), i64 1))
-; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], [[A3]]
-; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[TMP2]], -9
+; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], -9
+; CHECK-NEXT: [[TMP20:%.*]] = sub i64 [[TMP2]], [[A3]]
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP20]], 3
; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP4]], 4
@@ -210,8 +210,8 @@ define void @no_signed_wrap_iv_via_btc(ptr %dst, i32 %N) mustprogress {
; CHECK: [[LOOP_PREHEADER]]:
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], 1
; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[SUB4]], i32 [[TMP0]])
-; CHECK-NEXT: [[TMP7:%.*]] = sub i32 [[SMAX]], [[N]]
-; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP7]], 100
+; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[SMAX]], 100
+; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[TMP7]], [[N]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP2]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll b/llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
index 25b8f6f30fffd..7df597c46b751 100644
--- a/llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
+++ b/llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
@@ -398,8 +398,8 @@ define ptr @find_deref_pointer_distance_align_attribute_argument(ptr align 2 %fi
; CHECK-NEXT: [[C_0:%.*]] = icmp eq ptr [[FIRST]], [[LAST]]
; CHECK-NEXT: br i1 [[C_0]], label %[[EXIT:.*]], label %[[LOOP_HEADER_PREHEADER:.*]]
; CHECK: [[LOOP_HEADER_PREHEADER]]:
-; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[LAST_I64]], [[FIRST_I64]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], -2
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[LAST_I64]], -2
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[FIRST_I64]]
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 1
; CHECK-NEXT: [[TMP3:%.*]] = add nuw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
@@ -491,8 +491,8 @@ define ptr @find_deref_pointer_distance_align_assumption(ptr %first, ptr %last)
; CHECK-NEXT: [[C_0:%.*]] = icmp eq ptr [[FIRST]], [[LAST]]
; CHECK-NEXT: br i1 [[C_0]], label %[[EXIT:.*]], label %[[LOOP_HEADER_PREHEADER:.*]]
; CHECK: [[LOOP_HEADER_PREHEADER]]:
-; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[LAST_I64]], [[FIRST_I64]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], -2
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[LAST_I64]], -2
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[FIRST_I64]]
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 1
; CHECK-NEXT: [[TMP3:%.*]] = add nuw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
@@ -704,8 +704,8 @@ define i64 @find_if_pointer_distance_deref_via_assumption(ptr %vec) nofree nosyn
; CHECK-NEXT: br i1 [[IS_EMPTY]], label %[[EXIT:.*]], label %[[LOOP_PREHEADER:.*]]
; CHECK: [[LOOP_PREHEADER]]:
; CHECK-NEXT: [[END_PTR:%.*]] = getelementptr i8, ptr [[BEGIN]], i64 [[DISTANCE]]
-; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[END_INT]], [[BEGIN_INT]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], -2
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END_INT]], -2
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[BEGIN_INT]]
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 1
; CHECK-NEXT: [[TMP3:%.*]] = add nuw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
@@ -1108,8 +1108,8 @@ define i64 @VectorizingWithoutNoSyncAttributeTest(ptr noundef nonnull readonly a
; CHECK-NEXT: [[C_1:%.*]] = icmp eq ptr [[L_V]], [[L_GEP_V]]
; CHECK-NEXT: br i1 [[C_1]], label %[[EXIT:.*]], label %[[LOOP_PREHEADER:.*]]
; CHECK: [[LOOP_PREHEADER]]:
-; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[PI_L_GEP_V]], [[PI_L_V]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], -4
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[PI_L_GEP_V]], -4
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[PI_L_V]]
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 2
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
@@ -1225,8 +1225,8 @@ define i64 @volatileNotVectorizingTest(ptr noundef nonnull readonly align 8 capt
; CHECK-NEXT: [[C_1:%.*]] = icmp eq ptr [[L_V]], [[L_GEP_V]]
; CHECK-NEXT: br i1 [[C_1]], label %[[EXIT:.*]], label %[[LOOP_PREHEADER:.*]]
; CHECK: [[LOOP_PREHEADER]]:
-; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[PI_L_GEP_V]], [[PI_L_V]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], -4
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[PI_L_GEP_V]], -4
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[PI_L_V]]
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 2
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/std-find.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/std-find.ll
index 69b23200b239b..5941eb6fa8046 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/std-find.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/std-find.ll
@@ -253,8 +253,8 @@ define ptr @std_find_caller(ptr noundef %first, ptr noundef %last) {
; CHECK-NEXT: [[FIRST3:%.*]] = ptrtoint ptr [[FIRST]] to i64
; CHECK-NEXT: [[PTR_SUB:%.*]] = sub i64 [[LAST_I64]], [[FIRST3]]
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[FIRST]], i64 [[PTR_SUB]]
-; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[LAST_I64]], [[FIRST3]]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], -2
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[LAST_I64]], -2
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[FIRST3]]
; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i64 [[TMP1]], 1
; CHECK-NEXT: [[TMP3:%.*]] = add nuw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 14
>From d0eb454d9e7759e8125ad62351f93ae548b813a6 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Mon, 10 Aug 2026 09:29:37 +0100
Subject: [PATCH 2/2] [VPlan] Expand negated add operands as a subtract in
VPSCEVExpander.
Update VPSCEVExpander to try to expand adds of negative values as
subtract, instead of adding the negated operand. This matches IR
SCEVExpander behavior and improves expansions slightly.
It also avoids regressions when expanding more expressions.
Alive2 Proof: https://alive2.llvm.org/ce/z/Emgeqv
---
llvm/lib/Transforms/Vectorize/VPlanUtils.cpp | 29 ++++++++++++++-----
.../LoopVectorize/VPlan/expand-scev.ll | 2 +-
.../LoopVectorize/cast-induction.ll | 8 ++---
...nd-sink-mem-ops-with-invariant-pointers.ll | 4 +--
.../nested-loops-scev-expansion.ll | 5 ++--
.../trip-count-expansion-may-introduce-ub.ll | 4 +--
6 files changed, 31 insertions(+), 21 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
index 7cae96192453c..f9ac85eb8d481 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
@@ -892,26 +892,41 @@ VPValue *VPSCEVExpander::tryToExpand(const SCEV *S) {
return Builder.createNoWrapPtrAdd(Base, Offset, GEPFlags, DL);
}
- unsigned Opcode =
- S->getSCEVType() == scAddExpr ? Instruction::Add : Instruction::Mul;
+ bool IsAdd = S->getSCEVType() == scAddExpr;
+ unsigned Opcode = IsAdd ? Instruction::Add : Instruction::Mul;
// Iterate in reverse so that constants are emitted last. For adds, sort
// non-constant-negative operands last, matching SCEVExpander's LoopCompare,
- // so that they are accumulated into the result rather than starting it.
+ // so that they are negated and subtracted from the running result rather
+ // than starting it.
SmallVector<const SCEV *, 2> SCEVOps(reverse(NAry->operands()));
- if (Opcode == Instruction::Add)
+ if (IsAdd)
stable_sort(SCEVOps, [](const SCEV *L, const SCEV *R) {
return !L->isNonConstantNegative() && R->isNonConstantNegative();
});
SmallVector<VPValue *, 2> Ops;
for (const SCEV *Op : SCEVOps) {
- VPValue *OpV = tryToExpand(Op);
+ // Expand the negation of the operands that are subtracted below.
+ bool Negate = IsAdd && !Ops.empty() && Op->isNonConstantNegative();
+ VPValue *OpV = tryToExpand(Negate ? SE.getNegativeSCEV(Op) : Op);
if (!OpV)
return nullptr;
Ops.push_back(OpV);
}
VPValue *Result = Ops.front();
- for (VPValue *Op : drop_begin(Ops))
- Result = Builder.createOverflowingOp(Opcode, {Result, Op}, WrapFlags, DL);
+ for (auto [Op, OpV] : drop_begin(zip_equal(SCEVOps, Ops))) {
+ if (IsAdd && Op->isNonConstantNegative()) {
+ // Result + (-Op) = Result - Op unless negating Op overflows. This saves
+ // a extra multiply for the negation and allows carrying over the NSW
+ // flag from the SCEV expression.
+ bool HasNSW =
+ WrapFlags.HasNSW && !SE.getSignedRangeMin(Op).isMinSignedValue();
+ Result = Builder.createOverflowingOp(Instruction::Sub, {Result, OpV},
+ {/*HasNUW=*/false, HasNSW}, DL);
+ } else {
+ Result =
+ Builder.createOverflowingOp(Opcode, {Result, OpV}, WrapFlags, DL);
+ }
+ }
return Result;
}
case scUDivExpr: {
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
index 94ccb5b33273e..2a67b62797b02 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
@@ -294,7 +294,7 @@ define i32 @mul_by_signed_min_expanded_to_shl(i1 %a) {
; CHECK-NEXT: IR %sub = sub i32 %rem.neg, 1
; CHECK-NEXT: IR %shl = shl i32 %sub, 31
; CHECK-NEXT: EMIT vp<[[VP2:%[0-9]+]]> = shl nuw ir<%rem.neg>, ir<31>
-; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = add ir<-2147483547>, vp<[[VP2]]>
+; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = sub ir<-2147483547>, vp<[[VP2]]>
; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult vp<[[VP3]]>, ir<4>
; CHECK-NEXT: EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, vector.ph
diff --git a/llvm/test/Transforms/LoopVectorize/cast-induction.ll b/llvm/test/Transforms/LoopVectorize/cast-induction.ll
index edf7aaca124bc..2cf2970fc2f06 100644
--- a/llvm/test/Transforms/LoopVectorize/cast-induction.ll
+++ b/llvm/test/Transforms/LoopVectorize/cast-induction.ll
@@ -423,10 +423,8 @@ define i64 @induction_cast_chain_cleared_by_dce(i64 %n, i64 %mask.init) {
; VF4-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[MASK]], 1
; VF4-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[MASK]], 2
; VF4-NEXT: [[TMP2:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 [[TMP0]])
-; VF4-NEXT: [[TMP21:%.*]] = lshr i64 [[MASK_INIT]], 32
-; VF4-NEXT: [[TMP22:%.*]] = mul i64 [[TMP21]], -4294967296
; VF4-NEXT: [[TMP23:%.*]] = add i64 [[TMP2]], -1
-; VF4-NEXT: [[TMP1:%.*]] = add i64 [[TMP23]], [[TMP22]]
+; VF4-NEXT: [[TMP1:%.*]] = sub i64 [[TMP23]], [[MASK]]
; VF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 4
; VF4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; VF4: [[VECTOR_SCEVCHECK]]:
@@ -493,10 +491,8 @@ define i64 @induction_cast_chain_cleared_by_dce(i64 %n, i64 %mask.init) {
; IC2-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[MASK]], 1
; IC2-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[MASK]], 2
; IC2-NEXT: [[TMP2:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 [[TMP0]])
-; IC2-NEXT: [[TMP23:%.*]] = lshr i64 [[MASK_INIT]], 32
-; IC2-NEXT: [[TMP24:%.*]] = mul i64 [[TMP23]], -4294967296
; IC2-NEXT: [[TMP25:%.*]] = add i64 [[TMP2]], -1
-; IC2-NEXT: [[TMP1:%.*]] = add i64 [[TMP25]], [[TMP24]]
+; IC2-NEXT: [[TMP1:%.*]] = sub i64 [[TMP25]], [[MASK]]
; IC2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 2
; IC2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; IC2: [[VECTOR_SCEVCHECK]]:
diff --git a/llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll b/llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll
index 22395df8df40b..ce40a054337c0 100644
--- a/llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll
+++ b/llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll
@@ -212,8 +212,8 @@ define void @load_store_noalias_via_tbaa(ptr %p, ptr %q, ptr %n) {
; CHECK-NEXT: [[P6:%.*]] = ptrtoaddr ptr [[P]] to i64
; CHECK-NEXT: [[N5:%.*]] = ptrtoaddr ptr [[N]] to i64
; CHECK-NEXT: [[TMP17:%.*]] = mul i64 [[N5]], 3074457345618258603
-; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[P6]], -3074457345618258603
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP17]], [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[P6]], 3074457345618258603
+; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP17]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 2
; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP4]], 4
diff --git a/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll b/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
index 16f53642aeae8..9014cc606ad78 100644
--- a/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
+++ b/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
@@ -128,13 +128,12 @@ define void @pr49900(i32 %x, ptr %ptr) {
; CHECK-NEXT: [[TMP30:%.*]] = add i32 [[IV_1]], [[TMP17]]
; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP30]], 26
; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP18]], i32 65536)
-; CHECK-NEXT: [[TMP31:%.*]] = mul i32 [[TMP16]], -13
; CHECK-NEXT: [[TMP34:%.*]] = add i32 [[UMAX]], -26
; CHECK-NEXT: [[TMP20:%.*]] = sub i32 [[TMP34]], [[IV_1]]
-; CHECK-NEXT: [[TMP33:%.*]] = add i32 [[TMP20]], [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = sub i32 [[TMP20]], [[TMP17]]
; CHECK-NEXT: [[UMIN1:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP33]], i32 1)
; CHECK-NEXT: [[TMP23:%.*]] = sub i32 [[TMP20]], [[UMIN1]]
-; CHECK-NEXT: [[TMP32:%.*]] = add i32 [[TMP23]], [[TMP31]]
+; CHECK-NEXT: [[TMP32:%.*]] = sub i32 [[TMP23]], [[TMP17]]
; CHECK-NEXT: [[TMP25:%.*]] = udiv i32 [[TMP32]], 13
; CHECK-NEXT: [[TMP35:%.*]] = add i32 [[UMIN1]], [[TMP25]]
; CHECK-NEXT: [[TMP26:%.*]] = add i32 [[TMP35]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/trip-count-expansion-may-introduce-ub.ll b/llvm/test/Transforms/LoopVectorize/trip-count-expansion-may-introduce-ub.ll
index 67d40e12c0b5d..662cf84b676bc 100644
--- a/llvm/test/Transforms/LoopVectorize/trip-count-expansion-may-introduce-ub.ll
+++ b/llvm/test/Transforms/LoopVectorize/trip-count-expansion-may-introduce-ub.ll
@@ -985,8 +985,8 @@ define i64 @multi_exit_4_exit_count_with_urem_by_constant_in_latch(ptr %dst, i64
; CHECK-NEXT: entry:
; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 0)
; CHECK-NEXT: [[TMP4:%.*]] = udiv i64 [[N]], 42
-; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], -42
-; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[N]], [[TMP5]]
+; CHECK-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 42
+; CHECK-NEXT: [[TMP6:%.*]] = sub i64 [[N]], [[TMP5]]
; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP6]], i64 0)
; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[SMAX]], i64 [[TMP0]])
; CHECK-NEXT: [[TMP1:%.*]] = add nuw i64 [[UMIN]], 1
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