[llvm] [AArch64][RegAlloc] Enable callee-saved register optimization for AArch64 (PR #214773)

[Cullen Rhodes via llvm-commits]

c-rhodes wrote:

this increases compile-time significantly, CTMark geomean +1.06% sqlite +4.85%: https://llvm-compile-time-tracker.com/compare.php?from=20d5962141fd3f340840b86666f58c7f230f717c&to=f2d4d0e2fc023db3b984331cbddb8c4425076dc3&stat=instructions%3Au

I don't think the performance numbers are compelling enough as is.

FWIW I found myself looking in this area last week after discovering allocating CSRs in reverse order improves sqlite O3 compile-time by ~1%: https://llvm-compile-time-tracker.com/compare.php?from=2ef2ab65e8622a81b060b96a2ed579816d01f03f&to=921a67ccfdc99b15915dbb6321318017b425a652&stat=instructions%3Au

but it caused perf regressions (it's worth checking both mcpu=generic and mcpu=native) and a lot of codegen churn.

https://github.com/llvm/llvm-project/pull/214773