[llvm] [AArch64][GISel] Recover ADDHN from OR comparison masks (PR #213925)
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Mon Aug 10 02:30:45 PDT 2026
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git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp --diff_from_common_commit
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diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
index 3e7c1c352..f8030f4a0 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
@@ -407,10 +407,10 @@ bool matchTruncOrToADDHN(MachineInstr &MI, MachineRegisterInfo &MRI,
// If the narrow result is immediately any-extended back to the original type,
// the G_OR is cheaper than G_ADDHN followed by a vector widen.
if (MRI.hasOneNonDBGUse(Dst)) {
- MachineInstr &UseMI = *MRI.use_nodbg_instructions(Dst).begin();
- if (UseMI.getOpcode() == TargetOpcode::G_ANYEXT &&
- MRI.getType(UseMI.getOperand(0).getReg()) == SrcTy)
- return false;
+ MachineInstr &UseMI = *MRI.use_nodbg_instructions(Dst).begin();
+ if (UseMI.getOpcode() == TargetOpcode::G_ANYEXT &&
+ MRI.getType(UseMI.getOperand(0).getReg()) == SrcTy)
+ return false;
}
unsigned EltSize = SrcTy.getScalarSizeInBits();
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https://github.com/llvm/llvm-project/pull/213925
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