[llvm] [X86] concatvectors(cvtneps2bf16(x),cvtneps2bf16(y)) -> cvtne2ps2bf16(y,x) (PR #215215)

[via llvm-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-x86

Author: Simon Pilgrim (RKSimon)

<details>
<summary>Changes</summary>

Handle cvtne2ps2bf16 operands swap

Fixes #<!-- -->214676

---
Full diff: https://github.com/llvm/llvm-project/pull/215215.diff


3 Files Affected:

- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+10) 
- (modified) llvm/test/CodeGen/X86/avx512bf16-intrinsics.ll (+1-3) 
- (modified) llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll (+1-3) 


``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c74d342fed1cb..4428c184c1f73 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -61342,6 +61342,16 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
         return DAG.getNode(Opcode, DL, VT, ConcatSubOperand(NewSrcVT, Ops, 0));
       }
       break;
+    case X86ISD::CVTNEPS2BF16:
+      // Always profitable to concat to a single op.
+      // NOTE: Swapped operands.
+      if (NumOps == 2 && (VT.is256BitVector() || VT.is512BitVector()) &&
+          llvm::all_of(Ops, [VT](SDValue Op) {
+            return Op.getOperand(0).getValueSizeInBits() == VT.getSizeInBits();
+          }))
+        return DAG.getNode(X86ISD::VFPROUND2, DL, VT, Ops[1].getOperand(0),
+                           Ops[0].getOperand(0));
+      break;
     case X86ISD::HADD:
     case X86ISD::HSUB:
     case X86ISD::FHADD:
diff --git a/llvm/test/CodeGen/X86/avx512bf16-intrinsics.ll b/llvm/test/CodeGen/X86/avx512bf16-intrinsics.ll
index ea0be592de710..cf35fb986db48 100644
--- a/llvm/test/CodeGen/X86/avx512bf16-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx512bf16-intrinsics.ll
@@ -39,9 +39,7 @@ entry:
 define <8 x i64> @test_mm512_cvtne2ps2bf16_512_concat(<16 x float> %A, <16 x float> %B) {
 ; CHECK-LABEL: test_mm512_cvtne2ps2bf16_512_concat:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vcvtneps2bf16 %zmm0, %ymm0 # encoding: [0x62,0xf2,0x7e,0x48,0x72,0xc0]
-; CHECK-NEXT:    vcvtneps2bf16 %zmm1, %ymm1 # encoding: [0x62,0xf2,0x7e,0x48,0x72,0xc9]
-; CHECK-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 # encoding: [0x62,0xf3,0xfd,0x48,0x1a,0xc1,0x01]
+; CHECK-NEXT:    vcvtne2ps2bf16 %zmm0, %zmm1, %zmm0 # encoding: [0x62,0xf2,0x77,0x48,0x72,0xc0]
 ; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
 entry:
   %0 = tail call <16 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.512(<16 x float> %A)
diff --git a/llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll b/llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll
index 936d764a909e0..783b8e2ee4c8e 100644
--- a/llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll
@@ -133,9 +133,7 @@ entry:
 define <4 x i64> @test_mm256_cvtne2ps2bf16_256_concat(<8 x float> %A, <8 x float> %B) {
 ; CHECK-LABEL: test_mm256_cvtne2ps2bf16_256_concat:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vcvtneps2bf16 %ymm0, %xmm0 # encoding: [0x62,0xf2,0x7e,0x28,0x72,0xc0]
-; CHECK-NEXT:    vcvtneps2bf16 %ymm1, %xmm1 # encoding: [0x62,0xf2,0x7e,0x28,0x72,0xc9]
-; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x18,0xc1,0x01]
+; CHECK-NEXT:    vcvtne2ps2bf16 %ymm0, %ymm1, %ymm0 # encoding: [0x62,0xf2,0x77,0x28,0x72,0xc0]
 ; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
 entry:
   %0 = tail call <8 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.256(<8 x float> %A)

``````````

</details>


https://github.com/llvm/llvm-project/pull/215215