[llvm] [VPlan] Fix miscompile when widening induction with loop-variant step (PR #206010)

[Florian Hahn via llvm-commits]

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@@ -0,0 +1,265 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -passes=loop-vectorize -S -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
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fhahn wrote:

does the test need to be X86 specific? If not,pl ease move out and use force-vector-width instead

https://github.com/llvm/llvm-project/pull/206010