[llvm] [AMDGPU][NFC] Pre-commit test for eliminateFrameIndex SVS fallback with frame-register. (PR #215180)

[Vikash Gupta via llvm-commits]

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@@ -0,0 +1,66 @@
+; RUN: not --crash llc -O3 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s 2>&1 | FileCheck %s
+; REQUIRES: asserts
+
+; NOTE: SIRegisterInfo::eliminateFrameIndex currently asserts on a
+; flat-scratch target when a frame index used by a VALU instruction reaches the
+; generic SGPR scavenging path, the function has a frame register, and no SGPR
+; is free for the scavenger. Control then enters the branch that assumes no
+; frame register exists: it asserts !FrameReg and its SVS lowering materializes
+; the address from the offset alone, without a frame-register term.
+;
+; The reproducer needs all of following conditions:
+;   1. A VALU frame-index user (V_SUB_CO_U32_e32 from the addrspacecast).
+;   2. A frame register (non-entry function with a stack object).
+;   3. A non-zero frame offset (large stack arg area from the many arguments).
+;   4. No free SGPR for the scavenger (all pinned by the inline asm).
+;   5. A flat-scratch target (gfx942/gfx950).
+; The data dependency through %diff keeps every SGPR live across the subtract so
+; the scheduler cannot free one up.
+
+; CHECK: there is a frame register!
+
+target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
+target triple = "amdgcn-amd-amdhsa"
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vg0204 wrote:

Done!


https://github.com/llvm/llvm-project/pull/215180