[llvm] [AMDGPU][MC] Fix out-of-range MFMA tuple register-name assertion (PR #215147)

[Matt Arsenault via llvm-commits]

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@@ -109,6 +110,21 @@
 # GFX90A: [[@LINE+1]]:1: warning: invalid instruction encoding
 0x00,0x00,0x6d,0xd8,0x01,0x00,0x00,0x00
 
+# The f8f6f4 source tuples are narrowed down according to cbsz/blgp, but ttmp
+# registers have no 192-bit tuple.
+# GFX950-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
+0x00,0x00,0xae,0xd3,0x00,0xe9,0x00,0x64
+
+# Same, except that the source selector is an inline constant, which is not a
+# register at all.
+# GFX950-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
+0x00,0x00,0xae,0xd3,0xf2,0x00,0x02,0x64
+
+# The wmma source tuples are narrowed down according to the matrix formats, but
+# scalar registers have no 384-bit tuple.
+# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
+0x00,0x18,0x33,0xcc,0x08,0x30,0xa2,0x04
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arsenm wrote:

Seems like there are 3 size error cases, but only 2 size error tests?

https://github.com/llvm/llvm-project/pull/215147