[llvm] [AMDGPU] Precommit Tests for 'Fold redundant inf/nan checks into frexp instructions' (PR #214964)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 9 06:26:01 PDT 2026
https://github.com/addmisol updated https://github.com/llvm/llvm-project/pull/214964
>From 258951e392a37c72a7a0b4501a77bd04eeaa9eb7 Mon Sep 17 00:00:00 2001
From: addmisol <addmisol9 at gmail.com>
Date: Sat, 8 Aug 2026 18:55:23 +0530
Subject: [PATCH 1/5] [AMDGPU] Precommit Tests for 'Fold redundant inf/nan
checks into frexp instructions'
Signed-off-by: addmisol <addmisol9 at gmail.com>
---
.../CodeGen/AMDGPU/frexp-inf-nan-combine.ll | 804 ++++++++++++++++++
1 file changed, 804 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
diff --git a/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll b/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
new file mode 100644
index 0000000000000..d8faddb556499
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
@@ -0,0 +1,804 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950 %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s
+
+; Test that redundant inf/nan checks are folded into frexp instructions.
+; The AMDGPU frexp instructions already return 0 for inf/nan inputs.
+; This optimization should NOT apply on SI (Southern Islands) which has hasFractBug.
+
+declare {float, i32} @llvm.frexp.f32.i32(float)
+declare {double, i32} @llvm.frexp.f64.i32(double)
+declare {half, i16} @llvm.frexp.f16.i16(half)
+declare {bfloat, i16} @llvm.frexp.bf16.i16(bfloat)
+declare {<2 x float>, <2 x i32>} @llvm.frexp.v2f32.v2i32(<2 x float>)
+declare float @llvm.fabs.f32(float)
+declare double @llvm.fabs.f64(double)
+declare half @llvm.fabs.f16(half)
+declare bfloat @llvm.fabs.bf16(bfloat)
+declare <2 x float> @llvm.fabs.v2f32(<2 x float>)
+declare float @llvm.copysign.f32(float, float)
+
+; Pattern 1: select (fcmp uno x, 0), 0, (frexp_exp x)
+; NaN check - should fold to just frexp_exp
+define i32 @frexp_nan_clamp_exp_f32(float %x) {
+; GFX9-LABEL: frexp_nan_clamp_exp_f32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_nan_clamp_exp_f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_nan_clamp_exp_f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_nan_clamp_exp_f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: frexp_nan_clamp_exp_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; SI-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
+ %exp = extractvalue {float, i32} %frexp, 1
+ %is_nan = fcmp uno float %x, 0.0
+ %result = select i1 %is_nan, i32 0, i32 %exp
+ ret i32 %result
+}
+
+; Pattern 2: select (fcmp oeq |x|, inf), 0, (frexp_exp x)
+; Inf check - should fold to just frexp_exp
+define i32 @frexp_inf_clamp_exp_f32(float %x) {
+; GFX9-LABEL: frexp_inf_clamp_exp_f32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX9-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_inf_clamp_exp_f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX10-NEXT: v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_inf_clamp_exp_f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_inf_clamp_exp_f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: s_mov_b32 s0, 0x7f800000
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX950-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: frexp_inf_clamp_exp_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
+ %exp = extractvalue {float, i32} %frexp, 1
+ %abs = call float @llvm.fabs.f32(float %x)
+ %is_inf = fcmp oeq float %abs, 0x7FF0000000000000
+ %result = select i1 %is_inf, i32 0, i32 %exp
+ ret i32 %result
+}
+
+; Pattern 3: select (fcmp ueq |x|, inf), 0, (frexp_exp x)
+; Inf-or-NaN check - should fold to just frexp_exp
+define i32 @frexp_inf_or_nan_clamp_exp_f32(float %x) {
+; GFX9-LABEL: frexp_inf_or_nan_clamp_exp_f32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_movk_i32 s4, 0x1f8
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, s4
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_inf_or_nan_clamp_exp_f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_inf_or_nan_clamp_exp_f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_inf_or_nan_clamp_exp_f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: s_movk_i32 s0, 0x1f8
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX950-NEXT: v_cmp_class_f32_e64 vcc, v0, s0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: frexp_inf_or_nan_clamp_exp_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-NEXT: s_movk_i32 s6, 0x1f8
+; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-NEXT: v_cmp_class_f32_e64 s[6:7], v0, s6
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; SI-NEXT: s_and_b64 vcc, s[6:7], s[4:5]
+; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x)
+ %exp = extractvalue { float, i32 } %frexp, 1
+ %abs = call float @llvm.fabs.f32(float %x)
+ %is_non_finite = fcmp ueq float %abs, 0x7FF0000000000000
+ %result = select i1 %is_non_finite, i32 0, i32 %exp
+ ret i32 %result
+}
+
+; Test with frexp_mant instead of frexp_exp
+define float @frexp_nan_clamp_mant_f32(float %x) {
+; GFX9-LABEL: frexp_nan_clamp_mant_f32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_frexp_mant_f32_e32 v1, v0
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_nan_clamp_mant_f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_mant_f32_e32 v1, v0
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_nan_clamp_mant_f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_mant_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_nan_clamp_mant_f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_mant_f32_e32 v1, v0
+; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: frexp_nan_clamp_mant_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-NEXT: v_frexp_mant_f32_e32 v1, v0
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
+; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
+ %mant = extractvalue {float, i32} %frexp, 0
+ %is_nan = fcmp uno float %x, 0.0
+ %result = select i1 %is_nan, float 0.0, float %mant
+ ret float %result
+}
+
+; Test with reversed select operands: select (fcmp ord x, 0), frexp, 0
+define i32 @frexp_ord_clamp_exp_f32(float %x) {
+; GFX9-LABEL: frexp_ord_clamp_exp_f32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_ord_clamp_exp_f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_ord_clamp_exp_f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_ord_clamp_exp_f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: frexp_ord_clamp_exp_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; SI-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
+ %exp = extractvalue {float, i32} %frexp, 1
+ %is_ord = fcmp ord float %x, 0.0
+ %result = select i1 %is_ord, i32 %exp, i32 0
+ ret i32 %result
+}
+
+; Test with fcmp one |x|, inf (not inf check -> select frexp)
+define i32 @frexp_not_inf_clamp_exp_f32(float %x) {
+; GFX9-LABEL: frexp_not_inf_clamp_exp_f32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_movk_i32 s4, 0x1f8
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, s4
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_not_inf_clamp_exp_f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_not_inf_clamp_exp_f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_not_inf_clamp_exp_f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: s_movk_i32 s0, 0x1f8
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX950-NEXT: v_cmp_class_f32_e64 vcc, v0, s0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: frexp_not_inf_clamp_exp_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-NEXT: s_movk_i32 s6, 0x1f8
+; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-NEXT: v_cmp_class_f32_e64 s[6:7], v0, s6
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; SI-NEXT: s_and_b64 vcc, s[6:7], s[4:5]
+; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
+ %exp = extractvalue {float, i32} %frexp, 1
+ %abs = call float @llvm.fabs.f32(float %x)
+ %is_not_inf = fcmp one float %abs, 0x7FF0000000000000
+ %result = select i1 %is_not_inf, i32 %exp, i32 0
+ ret i32 %result
+}
+
+; Test f64
+define i32 @frexp_nan_clamp_exp_f64(double %x) {
+; GFX9-LABEL: frexp_nan_clamp_exp_f64:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1]
+; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_nan_clamp_exp_f64:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1]
+; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_nan_clamp_exp_f64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1]
+; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_nan_clamp_exp_f64:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1]
+; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: frexp_nan_clamp_exp_f64:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_and_b32_e32 v2, 0x7fffffff, v1
+; SI-NEXT: s_mov_b32 s4, 0x7ff00000
+; SI-NEXT: v_cmp_gt_i32_e32 vcc, s4, v2
+; SI-NEXT: v_cmp_o_f64_e64 s[4:5], v[0:1], v[0:1]
+; SI-NEXT: v_frexp_exp_i32_f64_e32 v0, v[0:1]
+; SI-NEXT: s_and_b64 vcc, s[4:5], vcc
+; SI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call {double, i32} @llvm.frexp.f64.i32(double %x)
+ %exp = extractvalue {double, i32} %frexp, 1
+ %is_nan = fcmp uno double %x, 0.0
+ %result = select i1 %is_nan, i32 0, i32 %exp
+ ret i32 %result
+}
+
+; Test f16
+define i16 @frexp_nan_clamp_exp_f16(half %x) {
+; GFX9-LABEL: frexp_nan_clamp_exp_f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_frexp_exp_i16_f16_e32 v1, v0
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_nan_clamp_exp_f16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_exp_i16_f16_e32 v1, v0
+; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_nan_clamp_exp_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_exp_i16_f16_e32 v0.h, v0.l
+; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b16 v0.l, 0, v0.h, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_nan_clamp_exp_f16:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v1, v0
+; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: frexp_nan_clamp_exp_f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; SI-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call {half, i16} @llvm.frexp.f16.i16(half %x)
+ %exp = extractvalue {half, i16} %frexp, 1
+ %is_nan = fcmp uno half %x, 0.0
+ %result = select i1 %is_nan, i16 0, i16 %exp
+ ret i16 %result
+}
+
+; Negative test: different input to frexp vs comparison
+define i32 @frexp_nan_different_input(float %x, float %y) {
+; GFX9-LABEL: frexp_nan_different_input:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_nan_different_input:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_nan_different_input:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_nan_different_input:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: frexp_nan_different_input:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; SI-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; SI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
+ %exp = extractvalue {float, i32} %frexp, 1
+ %is_nan = fcmp uno float %y, 0.0
+ %result = select i1 %is_nan, i32 0, i32 %exp
+ ret i32 %result
+}
+
+; Negative test: non-zero constant in select
+define i32 @frexp_nan_nonzero_const(float %x) {
+; GFX9-LABEL: frexp_nan_nonzero_const:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_nan_nonzero_const:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_nan_nonzero_const:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_nan_nonzero_const:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: frexp_nan_nonzero_const:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; SI-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
+ %exp = extractvalue {float, i32} %frexp, 1
+ %is_nan = fcmp uno float %x, 0.0
+ %result = select i1 %is_nan, i32 42, i32 %exp
+ ret i32 %result
+}
+
+; Negative test: unrelated comparison (not inf/nan test)
+define i32 @frexp_lt_zero_not_folded(float %x) {
+; GFX9-LABEL: frexp_lt_zero_not_folded:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_lt_zero_not_folded:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_lt_zero_not_folded:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_lt_zero_not_folded:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX950-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: frexp_lt_zero_not_folded:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; SI-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
+ %exp = extractvalue {float, i32} %frexp, 1
+ %is_lt_zero = fcmp olt float %x, 0.0
+ %result = select i1 %is_lt_zero, i32 0, i32 %exp
+ ret i32 %result
+}
+
+; Test with copysign - should still fold since frexp ignores sign
+define i32 @frexp_nan_clamp_copysign_f32(float %x, float %sign) {
+; GFX9-LABEL: frexp_nan_clamp_copysign_f32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_nan_clamp_copysign_f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_nan_clamp_copysign_f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_nan_clamp_copysign_f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: frexp_nan_clamp_copysign_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: s_brev_b32 s4, -2
+; SI-NEXT: v_bfi_b32 v1, s4, v0, v1
+; SI-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, s4
+; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; SI-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+ %copysign = call float @llvm.copysign.f32(float %x, float %sign)
+ %frexp = call {float, i32} @llvm.frexp.f32.i32(float %copysign)
+ %exp = extractvalue {float, i32} %frexp, 1
+ %is_nan = fcmp uno float %x, 0.0
+ %result = select i1 %is_nan, i32 0, i32 %exp
+ ret i32 %result
+}
+
+; Test bfloat16
+define i16 @frexp_nan_clamp_exp_bf16(bfloat %x) {
+; GFX9-LABEL: frexp_nan_clamp_exp_bf16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_nan_clamp_exp_bf16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_nan_clamp_exp_bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b16 v0.l, 0, v1.l, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_nan_clamp_exp_bf16:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: frexp_nan_clamp_exp_bf16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; SI-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call {bfloat, i16} @llvm.frexp.bf16.i16(bfloat %x)
+ %exp = extractvalue {bfloat, i16} %frexp, 1
+ %is_nan = fcmp uno bfloat %x, 0.0
+ %result = select i1 %is_nan, i16 0, i16 %exp
+ ret i16 %result
+}
+
+; Test v2f32 vector case
+define <2 x i32> @frexp_nan_clamp_exp_v2f32(<2 x float> %x) {
+; GFX9-LABEL: frexp_nan_clamp_exp_v2f32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_nan_clamp_exp_v2f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v2, v0
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v3, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_nan_clamp_exp_v2f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v2, v0
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v3, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_nan_clamp_exp_v2f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
+; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: frexp_nan_clamp_exp_v2f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s6, 0x7f800000
+; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, s6
+; SI-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, s6
+; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
+; SI-NEXT: s_and_b64 vcc, vcc, s[6:7]
+; SI-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; SI-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
+; SI-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; SI-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call {<2 x float>, <2 x i32>} @llvm.frexp.v2f32.v2i32(<2 x float> %x)
+ %exp = extractvalue {<2 x float>, <2 x i32>} %frexp, 1
+ %is_nan = fcmp uno <2 x float> %x, zeroinitializer
+ %result = select <2 x i1> %is_nan, <2 x i32> zeroinitializer, <2 x i32> %exp
+ ret <2 x i32> %result
+}
>From 7fa40a2a1c5a6ef41130f87d6b820339e62c070a Mon Sep 17 00:00:00 2001
From: addmisol <addmisol9 at gmail.com>
Date: Sat, 8 Aug 2026 21:13:58 +0530
Subject: [PATCH 2/5] Fix: Address comments
Signed-off-by: addmisol <addmisol9 at gmail.com>
---
.../CodeGen/AMDGPU/frexp-inf-nan-combine.ll | 20 ++++---------------
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll b/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
index d8faddb556499..e85cafd8721db 100644
--- a/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
@@ -1,26 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950 %s
++; RUN: llc -mtriple=amdgcn-amd-amdgpu -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
++; RUN: llc -mtriple=amdgcn-amd-amdgpu -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX10 %s
++; RUN: llc -mtriple=amdgcn-amd-amdgpu -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
++; RUN: llc -mtriple=amdgcn-amd-amdgpu -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950 %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s
; Test that redundant inf/nan checks are folded into frexp instructions.
; The AMDGPU frexp instructions already return 0 for inf/nan inputs.
; This optimization should NOT apply on SI (Southern Islands) which has hasFractBug.
-declare {float, i32} @llvm.frexp.f32.i32(float)
-declare {double, i32} @llvm.frexp.f64.i32(double)
-declare {half, i16} @llvm.frexp.f16.i16(half)
-declare {bfloat, i16} @llvm.frexp.bf16.i16(bfloat)
-declare {<2 x float>, <2 x i32>} @llvm.frexp.v2f32.v2i32(<2 x float>)
-declare float @llvm.fabs.f32(float)
-declare double @llvm.fabs.f64(double)
-declare half @llvm.fabs.f16(half)
-declare bfloat @llvm.fabs.bf16(bfloat)
-declare <2 x float> @llvm.fabs.v2f32(<2 x float>)
-declare float @llvm.copysign.f32(float, float)
-
; Pattern 1: select (fcmp uno x, 0), 0, (frexp_exp x)
; NaN check - should fold to just frexp_exp
define i32 @frexp_nan_clamp_exp_f32(float %x) {
>From addea798ecb6ca2b03902bf18713ebb2c9e59736 Mon Sep 17 00:00:00 2001
From: Addmisol <addmisol9 at gmail.com>
Date: Sat, 8 Aug 2026 21:16:15 +0530
Subject: [PATCH 3/5] Fix special char
---
llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll b/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
index e85cafd8721db..891375d1be908 100644
--- a/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-+; RUN: llc -mtriple=amdgcn-amd-amdgpu -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
-+; RUN: llc -mtriple=amdgcn-amd-amdgpu -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX10 %s
-+; RUN: llc -mtriple=amdgcn-amd-amdgpu -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
-+; RUN: llc -mtriple=amdgcn-amd-amdgpu -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950 %s
+; RUN: llc -mtriple=amdgcn-amd-amdgpu -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -mtriple=amdgcn-amd-amdgpu -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -mtriple=amdgcn-amd-amdgpu -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgcn-amd-amdgpu -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950 %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s
; Test that redundant inf/nan checks are folded into frexp instructions.
>From ea85d2ed6a6583f8cd86834d000d194511668909 Mon Sep 17 00:00:00 2001
From: addmisol <addmisol9 at gmail.com>
Date: Sun, 9 Aug 2026 07:55:27 +0530
Subject: [PATCH 4/5] Fix: New triple targets
Signed-off-by: addmisol <addmisol9 at gmail.com>
---
llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll b/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
index 891375d1be908..0ab452f0a4d1c 100644
--- a/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-amdgpu -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -mtriple=amdgcn-amd-amdgpu -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgcn-amd-amdgpu -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
-; RUN: llc -mtriple=amdgcn-amd-amdgpu -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950 %s
+; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -mtriple=amdgpu10.30-amd-amdhsa < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa < %s | FileCheck -check-prefix=GFX950 %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s
; Test that redundant inf/nan checks are folded into frexp instructions.
>From 89539ddebe0d6ca160c35033040fc0a4332e6688 Mon Sep 17 00:00:00 2001
From: addmisol <addmisol9 at gmail.com>
Date: Sun, 9 Aug 2026 18:54:37 +0530
Subject: [PATCH 5/5] Fix: Address Comments for tests
Signed-off-by: addmisol <addmisol9 at gmail.com>
---
.../CodeGen/AMDGPU/frexp-inf-nan-combine.ll | 1054 ++++++++++-------
1 file changed, 627 insertions(+), 427 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll b/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
index 0ab452f0a4d1c..42daf96e0fcb9 100644
--- a/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
@@ -1,13 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -mtriple=amdgpu10.30-amd-amdhsa < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX11 %s
-; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa < %s | FileCheck -check-prefix=GFX950 %s
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -mtriple=amdgpu9.00--amdpal < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -mtriple=amdgpu10.30--amdpal < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -mtriple=amdgpu11.00--amdpal < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgpu9.50--amdpal < %s | FileCheck -check-prefix=GFX950 %s
+; RUN: llc -mtriple=amdgpu6.00--amdpal < %s | FileCheck -check-prefix=GFX6 %s
; Test that redundant inf/nan checks are folded into frexp instructions.
; The AMDGPU frexp instructions already return 0 for inf/nan inputs.
-; This optimization should NOT apply on SI (Southern Islands) which has hasFractBug.
+; This optimization should NOT apply on GFX6 (Southern Islands) which has hasFractBug.
; Pattern 1: select (fcmp uno x, 0), 0, (frexp_exp x)
; NaN check - should fold to just frexp_exp
@@ -15,106 +15,184 @@ define i32 @frexp_nan_clamp_exp_f32(float %x) {
; GFX9-LABEL: frexp_nan_clamp_exp_f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frexp_nan_clamp_exp_f32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: frexp_nan_clamp_exp_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: frexp_nan_clamp_exp_f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
-; SI-LABEL: frexp_nan_clamp_exp_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; SI-NEXT: s_and_b64 vcc, vcc, s[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
- %frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
- %exp = extractvalue {float, i32} %frexp, 1
+; GFX6-LABEL: frexp_nan_clamp_exp_f32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x)
+ %exp = extractvalue { float, i32 } %frexp, 1
%is_nan = fcmp uno float %x, 0.0
%result = select i1 %is_nan, i32 0, i32 %exp
ret i32 %result
}
+; Commuted form: select (fcmp ord x, 0), frexp, 0
+define i32 @frexp_ord_clamp_exp_f32(float %x) {
+; GFX9-LABEL: frexp_ord_clamp_exp_f32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_ord_clamp_exp_f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_ord_clamp_exp_f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_ord_clamp_exp_f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-LABEL: frexp_ord_clamp_exp_f32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x)
+ %exp = extractvalue { float, i32 } %frexp, 1
+ %is_ord = fcmp ord float %x, 0.0
+ %result = select i1 %is_ord, i32 %exp, i32 0
+ ret i32 %result
+}
+
; Pattern 2: select (fcmp oeq |x|, inf), 0, (frexp_exp x)
; Inf check - should fold to just frexp_exp
define i32 @frexp_inf_clamp_exp_f32(float %x) {
; GFX9-LABEL: frexp_inf_clamp_exp_f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_inf_clamp_exp_f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_inf_clamp_exp_f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_inf_clamp_exp_f32:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-LABEL: frexp_inf_clamp_exp_f32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x)
+ %exp = extractvalue { float, i32 } %frexp, 1
+ %abs = call float @llvm.fabs.f32(float %x)
+ %is_inf = fcmp oeq float %abs, +inf
+ %result = select i1 %is_inf, i32 0, i32 %exp
+ ret i32 %result
+}
+
+; Commuted form: fcmp one |x|, inf (not inf check -> select frexp)
+define i32 @frexp_not_inf_clamp_exp_f32(float %x) {
+; GFX9-LABEL: frexp_not_inf_clamp_exp_f32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_movk_i32 s4, 0x1f8
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX9-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4
+; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, s4
; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: frexp_inf_clamp_exp_f32:
+; GFX10-LABEL: frexp_not_inf_clamp_exp_f32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX10-NEXT: v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: frexp_inf_clamp_exp_f32:
+; GFX11-LABEL: frexp_not_inf_clamp_exp_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX11-NEXT: v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX950-LABEL: frexp_inf_clamp_exp_f32:
+; GFX950-LABEL: frexp_not_inf_clamp_exp_f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: s_mov_b32 s0, 0x7f800000
+; GFX950-NEXT: s_movk_i32 s0, 0x1f8
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX950-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s0
+; GFX950-NEXT: v_cmp_class_f32_e64 vcc, v0, s0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
-; SI-LABEL: frexp_inf_clamp_exp_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
- %frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
- %exp = extractvalue {float, i32} %frexp, 1
+; GFX6-LABEL: frexp_not_inf_clamp_exp_f32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-NEXT: s_movk_i32 s6, 0x1f8
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX6-NEXT: v_cmp_class_f32_e64 s[6:7], v0, s6
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX6-NEXT: s_and_b64 vcc, s[6:7], s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x)
+ %exp = extractvalue { float, i32 } %frexp, 1
%abs = call float @llvm.fabs.f32(float %x)
- %is_inf = fcmp oeq float %abs, 0x7FF0000000000000
- %result = select i1 %is_inf, i32 0, i32 %exp
+ %is_not_inf = fcmp one float %abs, +inf
+ %result = select i1 %is_not_inf, i32 %exp, i32 0
ret i32 %result
}
@@ -157,21 +235,21 @@ define i32 @frexp_inf_or_nan_clamp_exp_f32(float %x) {
; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
-; SI-LABEL: frexp_inf_or_nan_clamp_exp_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: s_movk_i32 s6, 0x1f8
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cmp_class_f32_e64 s[6:7], v0, s6
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; SI-NEXT: s_and_b64 vcc, s[6:7], s[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
+; GFX6-LABEL: frexp_inf_or_nan_clamp_exp_f32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-NEXT: s_movk_i32 s6, 0x1f8
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX6-NEXT: v_cmp_class_f32_e64 s[6:7], v0, s6
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX6-NEXT: s_and_b64 vcc, s[6:7], s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
%frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x)
%exp = extractvalue { float, i32 } %frexp, 1
%abs = call float @llvm.fabs.f32(float %x)
- %is_non_finite = fcmp ueq float %abs, 0x7FF0000000000000
+ %is_non_finite = fcmp ueq float %abs, +inf
%result = select i1 %is_non_finite, i32 0, i32 %exp
ret i32 %result
}
@@ -181,429 +259,531 @@ define float @frexp_nan_clamp_mant_f32(float %x) {
; GFX9-LABEL: frexp_nan_clamp_mant_f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_frexp_mant_f32_e32 v1, v0
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frexp_nan_clamp_mant_f32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_frexp_mant_f32_e32 v1, v0
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX10-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: frexp_nan_clamp_mant_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_frexp_mant_f32_e32 v1, v0
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX11-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: frexp_nan_clamp_mant_f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_mant_f32_e32 v1, v0
-; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX950-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
-; SI-LABEL: frexp_nan_clamp_mant_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_frexp_mant_f32_e32 v1, v0
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
-; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
- %frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
- %mant = extractvalue {float, i32} %frexp, 0
+; GFX6-LABEL: frexp_nan_clamp_mant_f32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-NEXT: v_frexp_mant_f32_e32 v1, v0
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
+; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x)
+ %mant = extractvalue { float, i32 } %frexp, 0
%is_nan = fcmp uno float %x, 0.0
%result = select i1 %is_nan, float 0.0, float %mant
ret float %result
}
-; Test with reversed select operands: select (fcmp ord x, 0), frexp, 0
-define i32 @frexp_ord_clamp_exp_f32(float %x) {
-; GFX9-LABEL: frexp_ord_clamp_exp_f32:
+; Test f64
+define i32 @frexp_nan_clamp_exp_f64(double %x) {
+; GFX9-LABEL: frexp_nan_clamp_exp_f64:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v0, v[0:1]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_nan_clamp_exp_f64:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v0, v[0:1]
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_nan_clamp_exp_f64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v0, v[0:1]
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_nan_clamp_exp_f64:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i32_f64_e32 v0, v[0:1]
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-LABEL: frexp_nan_clamp_exp_f64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v1
+; GFX6-NEXT: s_mov_b32 s4, 0x7ff00000
+; GFX6-NEXT: v_cmp_gt_i32_e32 vcc, s4, v2
+; GFX6-NEXT: v_cmp_o_f64_e64 s[4:5], v[0:1], v[0:1]
+; GFX6-NEXT: v_frexp_exp_i32_f64_e32 v0, v[0:1]
+; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call { double, i32 } @llvm.frexp.f64.i32(double %x)
+ %exp = extractvalue { double, i32 } %frexp, 1
+ %is_nan = fcmp uno double %x, 0.0
+ %result = select i1 %is_nan, i32 0, i32 %exp
+ ret i32 %result
+}
+
+; Test f16
+define i16 @frexp_nan_clamp_exp_f16(half %x) {
+; GFX9-LABEL: frexp_nan_clamp_exp_f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_frexp_exp_i16_f16_e32 v0, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_nan_clamp_exp_f16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_exp_i16_f16_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_nan_clamp_exp_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_nan_clamp_exp_f16:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v0, v0
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-LABEL: frexp_nan_clamp_exp_f16:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call { half, i16 } @llvm.frexp.f16.i16(half %x)
+ %exp = extractvalue { half, i16 } %frexp, 1
+ %is_nan = fcmp uno half %x, 0.0
+ %result = select i1 %is_nan, i16 0, i16 %exp
+ ret i16 %result
+}
+
+; Test bfloat16
+define i16 @frexp_nan_clamp_exp_bf16(bfloat %x) {
+; GFX9-LABEL: frexp_nan_clamp_exp_bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: frexp_ord_clamp_exp_f32:
+; GFX10-LABEL: frexp_nan_clamp_exp_bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: frexp_ord_clamp_exp_f32:
+; GFX11-LABEL: frexp_nan_clamp_exp_bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX11-NEXT: v_cndmask_b16 v0.l, 0, v1.l, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX950-LABEL: frexp_ord_clamp_exp_f32:
+; GFX950-LABEL: frexp_nan_clamp_exp_bf16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
-; SI-LABEL: frexp_ord_clamp_exp_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; SI-NEXT: s_and_b64 vcc, vcc, s[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
- %frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
- %exp = extractvalue {float, i32} %frexp, 1
- %is_ord = fcmp ord float %x, 0.0
- %result = select i1 %is_ord, i32 %exp, i32 0
- ret i32 %result
+; GFX6-LABEL: frexp_nan_clamp_exp_bf16:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call { bfloat, i16 } @llvm.frexp.bf16.i16(bfloat %x)
+ %exp = extractvalue { bfloat, i16 } %frexp, 1
+ %is_nan = fcmp uno bfloat %x, 0.0
+ %result = select i1 %is_nan, i16 0, i16 %exp
+ ret i16 %result
}
-; Test with fcmp one |x|, inf (not inf check -> select frexp)
-define i32 @frexp_not_inf_clamp_exp_f32(float %x) {
-; GFX9-LABEL: frexp_not_inf_clamp_exp_f32:
+; Test v2f32 vector case
+define <2 x i32> @frexp_nan_clamp_exp_v2f32(<2 x float> %x) {
+; GFX9-LABEL: frexp_nan_clamp_exp_v2f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_movk_i32 s4, 0x1f8
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, s4
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: frexp_not_inf_clamp_exp_f32:
+; GFX10-LABEL: frexp_nan_clamp_exp_v2f32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: frexp_not_inf_clamp_exp_f32:
+; GFX11-LABEL: frexp_nan_clamp_exp_v2f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX950-LABEL: frexp_not_inf_clamp_exp_f32:
+; GFX950-LABEL: frexp_nan_clamp_exp_v2f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: s_movk_i32 s0, 0x1f8
-; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX950-NEXT: v_cmp_class_f32_e64 vcc, v0, s0
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
-; SI-LABEL: frexp_not_inf_clamp_exp_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: s_movk_i32 s6, 0x1f8
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cmp_class_f32_e64 s[6:7], v0, s6
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; SI-NEXT: s_and_b64 vcc, s[6:7], s[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
- %frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
- %exp = extractvalue {float, i32} %frexp, 1
- %abs = call float @llvm.fabs.f32(float %x)
- %is_not_inf = fcmp one float %abs, 0x7FF0000000000000
- %result = select i1 %is_not_inf, i32 %exp, i32 0
- ret i32 %result
+; GFX6-LABEL: frexp_nan_clamp_exp_v2f32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s6, 0x7f800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, s6
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, s6
+; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %x)
+ %exp = extractvalue { <2 x float>, <2 x i32> } %frexp, 1
+ %is_nan = fcmp uno <2 x float> %x, zeroinitializer
+ %result = select <2 x i1> %is_nan, <2 x i32> zeroinitializer, <2 x i32> %exp
+ ret <2 x i32> %result
}
-; Test f64
-define i32 @frexp_nan_clamp_exp_f64(double %x) {
-; GFX9-LABEL: frexp_nan_clamp_exp_f64:
+; Test v2f16 vector case
+define <2 x i16> @frexp_nan_clamp_exp_v2f16(<2 x half> %x) {
+; GFX9-LABEL: frexp_nan_clamp_exp_v2f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1]
-; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX9-NEXT: v_frexp_exp_i16_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_frexp_exp_i16_f16_e32 v0, v0
+; GFX9-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: frexp_nan_clamp_exp_f64:
+; GFX10-LABEL: frexp_nan_clamp_exp_v2f16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1]
-; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[0:1]
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX10-NEXT: v_frexp_exp_i16_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_frexp_exp_i16_f16_e32 v0, v0
+; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: frexp_nan_clamp_exp_f64:
+; GFX11-LABEL: frexp_nan_clamp_exp_v2f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1]
-; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT: v_frexp_exp_i16_f16_e32 v0.l, v0.l
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX11-NEXT: v_frexp_exp_i16_f16_e32 v0.h, v1.l
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX950-LABEL: frexp_nan_clamp_exp_f64:
+; GFX950-LABEL: frexp_nan_clamp_exp_v2f16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1]
-; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v0, v0
+; GFX950-NEXT: s_mov_b32 s0, 0x5040100
+; GFX950-NEXT: v_perm_b32 v0, v1, v0, s0
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
-; SI-LABEL: frexp_nan_clamp_exp_f64:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_and_b32_e32 v2, 0x7fffffff, v1
-; SI-NEXT: s_mov_b32 s4, 0x7ff00000
-; SI-NEXT: v_cmp_gt_i32_e32 vcc, s4, v2
-; SI-NEXT: v_cmp_o_f64_e64 s[4:5], v[0:1], v[0:1]
-; SI-NEXT: v_frexp_exp_i32_f64_e32 v0, v[0:1]
-; SI-NEXT: s_and_b64 vcc, s[4:5], vcc
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
- %frexp = call {double, i32} @llvm.frexp.f64.i32(double %x)
- %exp = extractvalue {double, i32} %frexp, 1
- %is_nan = fcmp uno double %x, 0.0
- %result = select i1 %is_nan, i32 0, i32 %exp
- ret i32 %result
+; GFX6-LABEL: frexp_nan_clamp_exp_v2f16:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX6-NEXT: s_mov_b32 s6, 0x7f800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s6
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, s6
+; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call { <2 x half>, <2 x i16> } @llvm.frexp.v2f16.v2i16(<2 x half> %x)
+ %exp = extractvalue { <2 x half>, <2 x i16> } %frexp, 1
+ %is_nan = fcmp uno <2 x half> %x, zeroinitializer
+ %result = select <2 x i1> %is_nan, <2 x i16> zeroinitializer, <2 x i16> %exp
+ ret <2 x i16> %result
}
-; Test f16
-define i16 @frexp_nan_clamp_exp_f16(half %x) {
-; GFX9-LABEL: frexp_nan_clamp_exp_f16:
+; Test v2bf16 vector case
+define <2 x i16> @frexp_nan_clamp_exp_v2bf16(<2 x bfloat> %x) {
+; GFX9-LABEL: frexp_nan_clamp_exp_v2bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_frexp_exp_i16_f16_e32 v1, v0
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: frexp_nan_clamp_exp_f16:
+; GFX10-LABEL: frexp_nan_clamp_exp_v2bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_frexp_exp_i16_f16_e32 v1, v0
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo
+; GFX10-NEXT: v_perm_b32 v0, v0, v1, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: frexp_nan_clamp_exp_f16:
+; GFX11-LABEL: frexp_nan_clamp_exp_v2bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_frexp_exp_i16_f16_e32 v0.h, v0.l
-; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b16 v0.l, 0, v0.h, vcc_lo
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cmp_o_f32_e64 s0, v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b16 v0.h, 0, v3.l, vcc_lo
+; GFX11-NEXT: v_cndmask_b16 v0.l, 0, v2.l, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX950-LABEL: frexp_nan_clamp_exp_f16:
+; GFX950-LABEL: frexp_nan_clamp_exp_v2bf16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v1, v0
-; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0
+; GFX950-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
+; GFX950-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
+; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
+; GFX950-NEXT: s_mov_b32 s0, 0x5040100
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX950-NEXT: v_perm_b32 v0, v1, v0, s0
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
-; SI-LABEL: frexp_nan_clamp_exp_f16:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; SI-NEXT: s_and_b64 vcc, vcc, s[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
- %frexp = call {half, i16} @llvm.frexp.f16.i16(half %x)
- %exp = extractvalue {half, i16} %frexp, 1
- %is_nan = fcmp uno half %x, 0.0
- %result = select i1 %is_nan, i16 0, i16 %exp
- ret i16 %result
+; GFX6-LABEL: frexp_nan_clamp_exp_v2bf16:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX6-NEXT: s_mov_b32 s6, 0x7f800000
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, s6
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, s6
+; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call { <2 x bfloat>, <2 x i16> } @llvm.frexp.v2bf16.v2i16(<2 x bfloat> %x)
+ %exp = extractvalue { <2 x bfloat>, <2 x i16> } %frexp, 1
+ %is_nan = fcmp uno <2 x bfloat> %x, zeroinitializer
+ %result = select <2 x i1> %is_nan, <2 x i16> zeroinitializer, <2 x i16> %exp
+ ret <2 x i16> %result
}
-; Negative test: different input to frexp vs comparison
-define i32 @frexp_nan_different_input(float %x, float %y) {
-; GFX9-LABEL: frexp_nan_different_input:
+; Test with amdgcn.frexp.exp intrinsic directly
+define i32 @frexp_nan_clamp_amdgcn_exp_f32(float %x) {
+; GFX9-LABEL: frexp_nan_clamp_amdgcn_exp_f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: frexp_nan_different_input:
+; GFX10-LABEL: frexp_nan_clamp_amdgcn_exp_f32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: frexp_nan_different_input:
+; GFX11-LABEL: frexp_nan_clamp_amdgcn_exp_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX950-LABEL: frexp_nan_different_input:
+; GFX950-LABEL: frexp_nan_clamp_amdgcn_exp_f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
-; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
-; SI-LABEL: frexp_nan_different_input:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
-; SI-NEXT: s_and_b64 vcc, vcc, s[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
- %frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
- %exp = extractvalue {float, i32} %frexp, 1
- %is_nan = fcmp uno float %y, 0.0
+; GFX6-LABEL: frexp_nan_clamp_amdgcn_exp_f32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+ %exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %x)
+ %is_nan = fcmp uno float %x, 0.0
%result = select i1 %is_nan, i32 0, i32 %exp
ret i32 %result
}
-; Negative test: non-zero constant in select
-define i32 @frexp_nan_nonzero_const(float %x) {
-; GFX9-LABEL: frexp_nan_nonzero_const:
+; Test with amdgcn.frexp.mant intrinsic directly
+define float @frexp_nan_clamp_amdgcn_mant_f32(float %x) {
+; GFX9-LABEL: frexp_nan_clamp_amdgcn_mant_f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc
+; GFX9-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: frexp_nan_nonzero_const:
+; GFX10-LABEL: frexp_nan_clamp_amdgcn_mant_f32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc_lo
+; GFX10-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: frexp_nan_nonzero_const:
+; GFX11-LABEL: frexp_nan_clamp_amdgcn_mant_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc_lo
+; GFX11-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX950-LABEL: frexp_nan_nonzero_const:
+; GFX950-LABEL: frexp_nan_clamp_amdgcn_mant_f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc
+; GFX950-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
-; SI-LABEL: frexp_nan_nonzero_const:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; SI-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
- %frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
- %exp = extractvalue {float, i32} %frexp, 1
+; GFX6-LABEL: frexp_nan_clamp_amdgcn_mant_f32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_frexp_mant_f32_e32 v1, v0
+; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+ %mant = call float @llvm.amdgcn.frexp.mant.f32(float %x)
%is_nan = fcmp uno float %x, 0.0
- %result = select i1 %is_nan, i32 42, i32 %exp
- ret i32 %result
+ %result = select i1 %is_nan, float 0.0, float %mant
+ ret float %result
}
-; Negative test: unrelated comparison (not inf/nan test)
-define i32 @frexp_lt_zero_not_folded(float %x) {
-; GFX9-LABEL: frexp_lt_zero_not_folded:
+; Test optimization applied to both mant and exp from the same frexp (most realistic case)
+define { float, i32 } @frexp_nan_clamp_both_f32(float %x) {
+; GFX9-LABEL: frexp_nan_clamp_both_f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: v_mov_b32_e32 v0, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: frexp_lt_zero_not_folded:
+; GFX10-LABEL: frexp_nan_clamp_both_f32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v0, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: frexp_lt_zero_not_folded:
+; GFX11-LABEL: frexp_nan_clamp_both_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX11-NEXT: v_mov_b32_e32 v0, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX950-LABEL: frexp_lt_zero_not_folded:
+; GFX950-LABEL: frexp_nan_clamp_both_f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX950-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX950-NEXT: v_mov_b32_e32 v0, v2
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
-; SI-LABEL: frexp_lt_zero_not_folded:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; SI-NEXT: s_and_b64 vcc, vcc, s[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
- %frexp = call {float, i32} @llvm.frexp.f32.i32(float %x)
- %exp = extractvalue {float, i32} %frexp, 1
- %is_lt_zero = fcmp olt float %x, 0.0
- %result = select i1 %is_lt_zero, i32 0, i32 %exp
- ret i32 %result
+; GFX6-LABEL: frexp_nan_clamp_both_f32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-NEXT: v_frexp_mant_f32_e32 v2, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; GFX6-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x)
+ %mant = extractvalue { float, i32 } %frexp, 0
+ %exp = extractvalue { float, i32 } %frexp, 1
+ %is_nan = fcmp uno float %x, 0.0
+ %mant_result = select i1 %is_nan, float 0.0, float %mant
+ %exp_result = select i1 %is_nan, i32 0, i32 %exp
+ %result0 = insertvalue { float, i32 } undef, float %mant_result, 0
+ %result1 = insertvalue { float, i32 } %result0, i32 %exp_result, 1
+ ret { float, i32 } %result1
}
; Test with copysign - should still fold since frexp ignores sign
@@ -611,182 +791,202 @@ define i32 @frexp_nan_clamp_copysign_f32(float %x, float %sign) {
; GFX9-LABEL: frexp_nan_clamp_copysign_f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: frexp_nan_clamp_copysign_f32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: frexp_nan_clamp_copysign_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: frexp_nan_clamp_copysign_f32:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
-; SI-LABEL: frexp_nan_clamp_copysign_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_brev_b32 s4, -2
-; SI-NEXT: v_bfi_b32 v1, s4, v0, v1
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, s4
-; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; SI-NEXT: s_and_b64 vcc, vcc, s[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
+; GFX6-LABEL: frexp_nan_clamp_copysign_f32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_brev_b32 s4, -2
+; GFX6-NEXT: v_bfi_b32 v1, s4, v0, v1
+; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, s4
+; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
%copysign = call float @llvm.copysign.f32(float %x, float %sign)
- %frexp = call {float, i32} @llvm.frexp.f32.i32(float %copysign)
- %exp = extractvalue {float, i32} %frexp, 1
+ %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %copysign)
+ %exp = extractvalue { float, i32 } %frexp, 1
%is_nan = fcmp uno float %x, 0.0
%result = select i1 %is_nan, i32 0, i32 %exp
ret i32 %result
}
-; Test bfloat16
-define i16 @frexp_nan_clamp_exp_bf16(bfloat %x) {
-; GFX9-LABEL: frexp_nan_clamp_exp_bf16:
+; Negative test: different input to frexp vs comparison
+define i32 @frexp_nan_different_input(float %x, float %y) {
+; GFX9-LABEL: frexp_nan_different_input:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: frexp_nan_different_input:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: frexp_nan_different_input:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-LABEL: frexp_nan_different_input:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
+; GFX950-NEXT: s_nop 1
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-LABEL: frexp_nan_different_input:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x)
+ %exp = extractvalue { float, i32 } %frexp, 1
+ %is_nan = fcmp uno float %y, 0.0
+ %result = select i1 %is_nan, i32 0, i32 %exp
+ ret i32 %result
+}
+
+; Negative test: non-zero constant in select
+define i32 @frexp_nan_nonzero_const(float %x) {
+; GFX9-LABEL: frexp_nan_nonzero_const:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: frexp_nan_clamp_exp_bf16:
+; GFX10-LABEL: frexp_nan_nonzero_const:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: frexp_nan_clamp_exp_bf16:
+; GFX11-LABEL: frexp_nan_nonzero_const:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: v_cndmask_b16 v0.l, 0, v1.l, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX950-LABEL: frexp_nan_clamp_exp_bf16:
+; GFX950-LABEL: frexp_nan_nonzero_const:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
-; SI-LABEL: frexp_nan_clamp_exp_bf16:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
-; SI-NEXT: s_and_b64 vcc, vcc, s[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
- %frexp = call {bfloat, i16} @llvm.frexp.bf16.i16(bfloat %x)
- %exp = extractvalue {bfloat, i16} %frexp, 1
- %is_nan = fcmp uno bfloat %x, 0.0
- %result = select i1 %is_nan, i16 0, i16 %exp
- ret i16 %result
+; GFX6-LABEL: frexp_nan_nonzero_const:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x)
+ %exp = extractvalue { float, i32 } %frexp, 1
+ %is_nan = fcmp uno float %x, 0.0
+ %result = select i1 %is_nan, i32 42, i32 %exp
+ ret i32 %result
}
-; Test v2f32 vector case
-define <2 x i32> @frexp_nan_clamp_exp_v2f32(<2 x float> %x) {
-; GFX9-LABEL: frexp_nan_clamp_exp_v2f32:
+; Negative test: unrelated comparison (not inf/nan test)
+define i32 @frexp_lt_zero_not_folded(float %x) {
+; GFX9-LABEL: frexp_lt_zero_not_folded:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: frexp_nan_clamp_exp_v2f32:
+; GFX10-LABEL: frexp_lt_zero_not_folded:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v2, v0
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v3, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc_lo
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: frexp_nan_clamp_exp_v2f32:
+; GFX11-LABEL: frexp_lt_zero_not_folded:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v2, v0
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v3, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc_lo
+; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX950-LABEL: frexp_nan_clamp_exp_v2f32:
+; GFX950-LABEL: frexp_lt_zero_not_folded:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
-; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
+; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX950-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX950-NEXT: s_setpc_b64 s[30:31]
;
-; SI-LABEL: frexp_nan_clamp_exp_v2f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s6, 0x7f800000
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, s6
-; SI-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, s6
-; SI-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
-; SI-NEXT: s_and_b64 vcc, vcc, s[6:7]
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; SI-NEXT: v_cmp_o_f32_e32 vcc, v1, v1
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
-; SI-NEXT: s_and_b64 vcc, vcc, s[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
- %frexp = call {<2 x float>, <2 x i32>} @llvm.frexp.v2f32.v2i32(<2 x float> %x)
- %exp = extractvalue {<2 x float>, <2 x i32>} %frexp, 1
- %is_nan = fcmp uno <2 x float> %x, zeroinitializer
- %result = select <2 x i1> %is_nan, <2 x i32> zeroinitializer, <2 x i32> %exp
- ret <2 x i32> %result
+; GFX6-LABEL: frexp_lt_zero_not_folded:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX6-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0
+; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0
+; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+ %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x)
+ %exp = extractvalue { float, i32 } %frexp, 1
+ %is_lt_zero = fcmp olt float %x, 0.0
+ %result = select i1 %is_lt_zero, i32 0, i32 %exp
+ ret i32 %result
}
More information about the llvm-commits
mailing list