[llvm] [VPlan] Fix miscompile when widening induction with loop-variant step (PR #206010)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 9 02:00:45 PDT 2026
https://github.com/clarence1121 updated https://github.com/llvm/llvm-project/pull/206010
>From 89eb9bc6b65d1426c9db5577e23dce2f062da0db Mon Sep 17 00:00:00 2001
From: clarence1121 <kevin25731568 at gmail.com>
Date: Fri, 26 Jun 2026 22:45:53 +0800
Subject: [PATCH 1/4] [LV][NFC] Add test for loop vectorizer miscompile with
variant-step induction (PR #205799)
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The test exposes the bug: a loop whose i8 induction variable %iv has a
loop-variant step (zext i1 %cmp to i8 — zero on the last iteration) is
miscompiled when vectorized. InductionDescriptor classifies %iv as
IK_IntInduction with step=1, so VPlan wides it with a constant step of 1.
ReplaceExtractsWithExitingIVValue then replaces the exit value of %iv
with 'trunc i32 %n.vec to i8' (the vector iteration count) rather than
extracting the actual last-lane value. For inputs a={7,15,31,63,127}
the scalar loop computes the correct counter, but the vectorized loop
returns n.vec instead, producing an off-by-one result.
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
---
.../Transforms/LoopVectorize/X86/pr205799.ll | 173 ++++++++++++++++++
1 file changed, 173 insertions(+)
create mode 100644 llvm/test/Transforms/LoopVectorize/X86/pr205799.ll
diff --git a/llvm/test/Transforms/LoopVectorize/X86/pr205799.ll b/llvm/test/Transforms/LoopVectorize/X86/pr205799.ll
new file mode 100644
index 0000000000000..4a8584e07506a
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/X86/pr205799.ll
@@ -0,0 +1,173 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -passes=loop-vectorize -S -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; Loop with i8 induction using a variant step (zext of comparison).
+; InductionDescriptor classifies %iv as IK_IntInduction with step=1,
+; but the VPlan backedge step is loop-variant (zext i1 %cmp to i8).
+; Without the fix, ReplaceExtractsWithExitingIVValue replaces the iv
+; exit value with 'trunc i32 %n.vec to i8' (the vector iteration count)
+; instead of the actual last iv value, producing an off-by-one result.
+define { i32, i32 } @variant_step_induction(i8 %a, i32 %b) {
+; CHECK-LABEL: define { i32, i32 } @variant_step_induction(
+; CHECK-SAME: i8 [[A:%.*]], i32 [[B:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[A]] to i32
+; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i32 [[TMP0]], 1
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 8
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 8
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]]
+; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[N_VEC]] to i8
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i8> poison, i8 [[A]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT]], <4 x i8> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i32> poison, i32 [[B]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT1]], <4 x i32> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ <i8 0, i8 1, i8 2, i8 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[STEP_ADD:%.*]] = add <4 x i8> [[VEC_IND]], splat (i8 4)
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <4 x i8> [[VEC_IND]], [[BROADCAST_SPLAT]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ult <4 x i8> [[STEP_ADD]], [[BROADCAST_SPLAT]]
+; CHECK-NEXT: [[TMP5:%.*]] = select <4 x i1> [[TMP3]], <4 x i32> [[BROADCAST_SPLAT2]], <4 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP6:%.*]] = select <4 x i1> [[TMP4]], <4 x i32> [[BROADCAST_SPLAT2]], <4 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP7]] = add <4 x i32> [[TMP5]], [[VEC_PHI]]
+; CHECK-NEXT: [[TMP8]] = add <4 x i32> [[TMP6]], [[VEC_PHI3]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[STEP_ADD]], splat (i8 4)
+; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP8]], [[TMP7]]
+; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX]])
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i8 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP10]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i8 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[RDX_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[IV]], [[A]]
+; CHECK-NEXT: [[ADD:%.*]] = select i1 [[CMP]], i32 [[B]], i32 0
+; CHECK-NEXT: [[RDX_NEXT]] = add nsw i32 [[ADD]], [[RDX]]
+; CHECK-NEXT: [[INC:%.*]] = zext i1 [[CMP]] to i8
+; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], [[INC]]
+; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[RDX_NEXT_LCSSA:%.*]] = phi i32 [ [[RDX_NEXT]], %[[LOOP]] ], [ [[TMP10]], %[[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i8 [ [[IV_NEXT]], %[[LOOP]] ], [ [[TMP2]], %[[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[IV_NEXT_LCSSA]] to i32
+; CHECK-NEXT: [[R0:%.*]] = insertvalue { i32, i32 } undef, i32 [[CONV]], 0
+; CHECK-NEXT: [[R1:%.*]] = insertvalue { i32, i32 } [[R0]], i32 [[RDX_NEXT_LCSSA]], 1
+; CHECK-NEXT: ret { i32, i32 } [[R1]]
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i8 [ 0, %entry ], [ %iv.next, %loop ]
+ %rdx = phi i32 [ 0, %entry ], [ %rdx.next, %loop ]
+ %cmp = icmp ult i8 %iv, %a
+ %add = select i1 %cmp, i32 %b, i32 0
+ %rdx.next = add nsw i32 %add, %rdx
+ %inc = zext i1 %cmp to i8
+ %iv.next = add i8 %iv, %inc
+ br i1 %cmp, label %loop, label %exit
+
+exit:
+ %conv = zext i8 %iv.next to i32
+ %r0 = insertvalue { i32, i32 } undef, i32 %conv, 0
+ %r1 = insertvalue { i32, i32 } %r0, i32 %rdx.next, 1
+ ret { i32, i32 } %r1
+}
+
+; Constant-step Sub induction: %iv decrements by 1 each iteration (step loop-invariant).
+; Exercises the Instruction::Sub branch in hasVariantStepIncrement, which must
+; correctly identify the step as loop-invariant and allow normal VPlan widening.
+define void @induction_sub_const_step(i32 %n, ptr %a) {
+; CHECK-LABEL: define void @induction_sub_const_step(
+; CHECK-SAME: i32 [[N:%.*]], ptr [[A:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[TMP0:%.*]] = add nsw i32 [[N]], -1
+; CHECK-NEXT: [[SMIN1:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP0]], i32 0)
+; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[N]], [[SMIN1]]
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 20
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
+; CHECK: [[VECTOR_SCEVCHECK]]:
+; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[N]], -1
+; CHECK-NEXT: [[TMP3:%.*]] = add nsw i32 [[N]], -1
+; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP3]], i32 0)
+; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP2]], [[SMIN]]
+; CHECK-NEXT: [[TMP5:%.*]] = sub i32 [[N]], [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = icmp sgt i32 [[TMP5]], [[N]]
+; CHECK-NEXT: br i1 [[TMP6]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 8
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]]
+; CHECK-NEXT: [[TMP7:%.*]] = sub i32 [[N]], [[N_VEC]]
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[N]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP8:%.*]] = sub nsw <4 x i32> [[BROADCAST_SPLAT]], <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ [[TMP8]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[STEP_ADD:%.*]] = add nsw <4 x i32> [[VEC_IND]], splat (i32 -4)
+; CHECK-NEXT: [[TMP9:%.*]] = sub i32 [[N]], [[INDEX]]
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP9]]
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i64 -3
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i64 -7
+; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <4 x i32> [[VEC_IND]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT: [[REVERSE2:%.*]] = shufflevector <4 x i32> [[STEP_ADD]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT: store <4 x i32> [[REVERSE]], ptr [[TMP11]], align 4
+; CHECK-NEXT: store <4 x i32> [[REVERSE2]], ptr [[TMP12]], align 4
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <4 x i32> [[STEP_ADD]], splat (i32 -4)
+; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP7]], %[[MIDDLE_BLOCK]] ], [ [[N]], %[[ENTRY]] ], [ [[N]], %[[VECTOR_SCEVCHECK]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[IV]]
+; CHECK-NEXT: store i32 [[IV]], ptr [[PTR]], align 4
+; CHECK-NEXT: [[IV_NEXT]] = sub nsw i32 [[IV]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[IV_NEXT]], 0
+; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [ %n, %entry ], [ %iv.next, %loop ]
+ %ptr = getelementptr inbounds i32, ptr %a, i32 %iv
+ store i32 %iv, ptr %ptr, align 4
+ %iv.next = sub nsw i32 %iv, 1
+ %cmp = icmp sgt i32 %iv.next, 0
+ br i1 %cmp, label %loop, label %exit
+
+exit:
+ ret void
+}
+;.
+; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
+; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
+; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
+;.
>From 56a7686bb5238a77dfa7c7adec138945e95ff9f2 Mon Sep 17 00:00:00 2001
From: clarence1121 <kevin25731568 at gmail.com>
Date: Fri, 26 Jun 2026 22:46:06 +0800
Subject: [PATCH 2/4] [LV] Fix miscompile when widening induction with
loop-variant step
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
InductionDescriptor::isInductionPHI classifies a phi as IK_IntInduction
whenever the backedge value is formed by an add/sub of any step — even a
loop-variant one. createWidenInductionRecipe was then calling
setOperand(1, IndDesc.getStep()), replacing the real VPlan step with the
loop-invariant IndDesc step; and ReplaceExtractsWithExitingIVValue was
computing ExitingIVValue(WideIV) = start + n_iterations * IndDesc.step,
which is wrong when the true step is variant.
Add hasVariantStepIncrement, which walks the VPlan step operand through
Add/Sub looking for a non-loop-invariant leaf via getSCEVExprForVPValue.
Guard both the setOperand clobber and the extract-replacement with
!HasVariantStepIncrement so variant-step inductions use the correct
per-lane exit value from an extractelement instead.
Fixes https://github.com/llvm/llvm-project/issues/205799.
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
---
.../Vectorize/VPlanConstruction.cpp | 42 ++++++++++++++++++-
.../Transforms/LoopVectorize/X86/pr205799.ll | 34 ++++++++-------
2 files changed, 58 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
index 34fbf85cbad42..27a6fbd49e058 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
@@ -615,6 +615,40 @@ static void simplifyLiveInsWithSCEV(VPlan &Plan,
/// To make RUN_VPLAN_PASS print initial VPlan.
static void printAfterInitialConstruction(VPlan &) {}
+/// Returns true if \p BackedgeVal advances \p PhiR by a loop-variant step.
+static bool hasVariantStepIncrement(VPValue *BackedgeVal, VPPhi *PhiR,
+ const InductionDescriptor &IndDesc,
+ PredicatedScalarEvolution &PSE,
+ Loop &OrigLoop) {
+ if (IndDesc.getKind() != InductionDescriptor::IK_IntInduction)
+ return false;
+
+ // Use m_c_Add to capture ActualStep regardless of operand order; subtraction
+ // is non-commutative so m_Sub requires PhiR on the left.
+ VPValue *ActualStep = nullptr;
+ switch (IndDesc.getInductionOpcode()) {
+ case Instruction::Add:
+ if (!match(BackedgeVal, m_c_Add(m_Specific(PhiR), m_VPValue(ActualStep))))
+ return false;
+ break;
+ case Instruction::Sub:
+ if (!match(BackedgeVal, m_Sub(m_Specific(PhiR), m_VPValue(ActualStep))))
+ return false;
+ break;
+ default:
+ return false;
+ }
+
+ const SCEV *ActualStepSCEV = vputils::getSCEVExprForVPValue(ActualStep, PSE);
+ // If the VPlan step has no computable SCEV, conservatively treat it as
+ // variant to avoid replacing it with the (potentially mismatched) IndDesc
+ // step or computing a wrong exit value.
+ if (isa<SCEVCouldNotCompute>(ActualStepSCEV))
+ return true;
+
+ return !PSE.getSE()->isLoopInvariant(ActualStepSCEV, &OrigLoop);
+}
+
std::unique_ptr<VPlan>
VPlanTransforms::buildVPlan0(Loop *TheLoop, LoopInfo &LI, Type *InductionTy,
PredicatedScalarEvolution &PSE,
@@ -700,7 +734,10 @@ createWidenInductionRecipe(PHINode *Phi, VPPhi *PhiR, VPIRValue *Start,
// Update wide induction increments to use the same step as the corresponding
// wide induction. This enables detecting induction increments directly in
// VPlan and removes redundant splats.
- if (match(BackedgeVal, m_Add(m_Specific(PhiR), m_VPValue())))
+ bool HasVariantStepIncrement =
+ hasVariantStepIncrement(BackedgeVal, PhiR, IndDesc, PSE, OrigLoop);
+ if (!HasVariantStepIncrement &&
+ match(BackedgeVal, m_Add(m_Specific(PhiR), m_VPValue())))
BackedgeVal->getDefiningRecipe()->setOperand(1, Step);
// It is always safe to copy over the NoWrap and FastMath flags. In
@@ -711,7 +748,8 @@ createWidenInductionRecipe(PHINode *Phi, VPPhi *PhiR, VPIRValue *Start,
auto *WideIV = new VPWidenIntOrFpInductionRecipe(
Phi, Start, Step, &Plan.getVF(), IndDesc, Flags, DL);
- ReplaceExtractsWithExitingIVValueIfPossible(WideIV);
+ if (!HasVariantStepIncrement)
+ ReplaceExtractsWithExitingIVValueIfPossible(WideIV);
return WideIV;
}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/pr205799.ll b/llvm/test/Transforms/LoopVectorize/X86/pr205799.ll
index 4a8584e07506a..1bbfa81be090f 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/pr205799.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/pr205799.ll
@@ -21,7 +21,6 @@ define { i32, i32 } @variant_step_induction(i8 %a, i32 %b) {
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 8
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]]
-; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[N_VEC]] to i8
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i8> poison, i8 [[A]], i64 0
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT]], <4 x i8> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i32> poison, i32 [[B]], i64 0
@@ -30,27 +29,30 @@ define { i32, i32 } @variant_step_induction(i8 %a, i32 %b) {
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ <i8 0, i8 1, i8 2, i8 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[STEP_ADD:%.*]] = add <4 x i8> [[VEC_IND]], splat (i8 4)
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <4 x i8> [[VEC_IND]], [[BROADCAST_SPLAT]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ult <4 x i8> [[STEP_ADD]], [[BROADCAST_SPLAT]]
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult <4 x i8> [[VEC_IND]], [[BROADCAST_SPLAT]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <4 x i8> [[STEP_ADD]], [[BROADCAST_SPLAT]]
+; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> [[BROADCAST_SPLAT2]], <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = select <4 x i1> [[TMP3]], <4 x i32> [[BROADCAST_SPLAT2]], <4 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP6:%.*]] = select <4 x i1> [[TMP4]], <4 x i32> [[BROADCAST_SPLAT2]], <4 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP7]] = add <4 x i32> [[TMP5]], [[VEC_PHI]]
-; CHECK-NEXT: [[TMP8]] = add <4 x i32> [[TMP6]], [[VEC_PHI3]]
+; CHECK-NEXT: [[TMP6]] = add <4 x i32> [[TMP4]], [[VEC_PHI]]
+; CHECK-NEXT: [[TMP7]] = add <4 x i32> [[TMP5]], [[VEC_PHI3]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[STEP_ADD]], splat (i8 4)
-; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP8]], [[TMP7]]
-; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX]])
+; CHECK-NEXT: [[TMP9:%.*]] = zext <4 x i1> [[TMP3]] to <4 x i8>
+; CHECK-NEXT: [[TMP10:%.*]] = add <4 x i8> [[STEP_ADD]], [[TMP9]]
+; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP7]], [[TMP6]]
+; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX]])
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i8> [[TMP10]], i64 3
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i8 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP10]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i8 [ [[TMP12]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i8 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
@@ -62,8 +64,8 @@ define { i32, i32 } @variant_step_induction(i8 %a, i32 %b) {
; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], [[INC]]
; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[RDX_NEXT_LCSSA:%.*]] = phi i32 [ [[RDX_NEXT]], %[[LOOP]] ], [ [[TMP10]], %[[MIDDLE_BLOCK]] ]
-; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i8 [ [[IV_NEXT]], %[[LOOP]] ], [ [[TMP2]], %[[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[RDX_NEXT_LCSSA:%.*]] = phi i32 [ [[RDX_NEXT]], %[[LOOP]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i8 [ [[IV_NEXT]], %[[LOOP]] ], [ [[TMP12]], %[[MIDDLE_BLOCK]] ]
; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[IV_NEXT_LCSSA]] to i32
; CHECK-NEXT: [[R0:%.*]] = insertvalue { i32, i32 } undef, i32 [[CONV]], 0
; CHECK-NEXT: [[R1:%.*]] = insertvalue { i32, i32 } [[R0]], i32 [[RDX_NEXT_LCSSA]], 1
>From 0e0a6319284e47ea3560c4fe73ba90a5490e2270 Mon Sep 17 00:00:00 2001
From: clarence1121 <kevin25731568 at gmail.com>
Date: Wed, 22 Jul 2026 05:55:54 +0800
Subject: [PATCH 3/4] [LV] Inline variant-step SCEV invariance check
Inline the variant-step check in createWidenInductionRecipe and reuse
the existing ScalarEvolution reference.
Retain support for both add and sub backedge updates. Add coverage for
a loop-variant sub step to ensure the optimizations are skipped when
the decrement is not loop-invariant.
---
.../Vectorize/VPlanConstruction.cpp | 49 +++-------
.../Transforms/LoopVectorize/X86/pr205799.ll | 94 ++++++++++++++++++-
2 files changed, 105 insertions(+), 38 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
index 27a6fbd49e058..09ee06be8e603 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
@@ -615,40 +615,6 @@ static void simplifyLiveInsWithSCEV(VPlan &Plan,
/// To make RUN_VPLAN_PASS print initial VPlan.
static void printAfterInitialConstruction(VPlan &) {}
-/// Returns true if \p BackedgeVal advances \p PhiR by a loop-variant step.
-static bool hasVariantStepIncrement(VPValue *BackedgeVal, VPPhi *PhiR,
- const InductionDescriptor &IndDesc,
- PredicatedScalarEvolution &PSE,
- Loop &OrigLoop) {
- if (IndDesc.getKind() != InductionDescriptor::IK_IntInduction)
- return false;
-
- // Use m_c_Add to capture ActualStep regardless of operand order; subtraction
- // is non-commutative so m_Sub requires PhiR on the left.
- VPValue *ActualStep = nullptr;
- switch (IndDesc.getInductionOpcode()) {
- case Instruction::Add:
- if (!match(BackedgeVal, m_c_Add(m_Specific(PhiR), m_VPValue(ActualStep))))
- return false;
- break;
- case Instruction::Sub:
- if (!match(BackedgeVal, m_Sub(m_Specific(PhiR), m_VPValue(ActualStep))))
- return false;
- break;
- default:
- return false;
- }
-
- const SCEV *ActualStepSCEV = vputils::getSCEVExprForVPValue(ActualStep, PSE);
- // If the VPlan step has no computable SCEV, conservatively treat it as
- // variant to avoid replacing it with the (potentially mismatched) IndDesc
- // step or computing a wrong exit value.
- if (isa<SCEVCouldNotCompute>(ActualStepSCEV))
- return true;
-
- return !PSE.getSE()->isLoopInvariant(ActualStepSCEV, &OrigLoop);
-}
-
std::unique_ptr<VPlan>
VPlanTransforms::buildVPlan0(Loop *TheLoop, LoopInfo &LI, Type *InductionTy,
PredicatedScalarEvolution &PSE,
@@ -734,8 +700,19 @@ createWidenInductionRecipe(PHINode *Phi, VPPhi *PhiR, VPIRValue *Start,
// Update wide induction increments to use the same step as the corresponding
// wide induction. This enables detecting induction increments directly in
// VPlan and removes redundant splats.
- bool HasVariantStepIncrement =
- hasVariantStepIncrement(BackedgeVal, PhiR, IndDesc, PSE, OrigLoop);
+ bool HasVariantStepIncrement = false;
+ // Use m_c_Add to capture IncStep regardless of operand order; subtraction
+ // is non-commutative so m_Sub requires PhiR on the left.
+ VPValue *IncStep;
+ if (match(BackedgeVal, m_c_Add(m_Specific(PhiR), m_VPValue(IncStep))) ||
+ match(BackedgeVal, m_Sub(m_Specific(PhiR), m_VPValue(IncStep)))) {
+ const SCEV *IncStepSCEV = vputils::getSCEVExprForVPValue(IncStep, PSE);
+ // If the VPlan step has no computable SCEV, conservatively treat it as
+ // variant to avoid replacing it with the (potentially mismatched) IndDesc
+ // step or computing a wrong exit value.
+ HasVariantStepIncrement = isa<SCEVCouldNotCompute>(IncStepSCEV) ||
+ !SE.isLoopInvariant(IncStepSCEV, &OrigLoop);
+ }
if (!HasVariantStepIncrement &&
match(BackedgeVal, m_Add(m_Specific(PhiR), m_VPValue())))
BackedgeVal->getDefiningRecipe()->setOperand(1, Step);
diff --git a/llvm/test/Transforms/LoopVectorize/X86/pr205799.ll b/llvm/test/Transforms/LoopVectorize/X86/pr205799.ll
index 1bbfa81be090f..c546c3fa785ea 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/pr205799.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/pr205799.ll
@@ -92,8 +92,9 @@ exit:
}
; Constant-step Sub induction: %iv decrements by 1 each iteration (step loop-invariant).
-; Exercises the Instruction::Sub branch in hasVariantStepIncrement, which must
-; correctly identify the step as loop-invariant and allow normal VPlan widening.
+; Exercises the Sub branch of the variant-step check in createWidenInductionRecipe,
+; which must correctly identify the step as loop-invariant and allow normal VPlan
+; widening.
define void @induction_sub_const_step(i32 %n, ptr %a) {
; CHECK-LABEL: define void @induction_sub_const_step(
; CHECK-SAME: i32 [[N:%.*]], ptr [[A:%.*]]) {
@@ -165,6 +166,93 @@ loop:
exit:
ret void
}
+
+; Sub analog of variant_step_induction: %iv decrements by a loop-variant
+; amount (zext of a comparison) instead of incrementing. Without covering the
+; Sub case of the variant-step check, this would regress to the same class of
+; miscompile as the Add case above, computing the exit value as
+; 'trunc i32 %n.vec to i8' instead of extracting the true last lane.
+define { i32, i32 } @variant_step_induction_sub(i8 %a, i32 %b) {
+; CHECK-LABEL: define { i32, i32 } @variant_step_induction_sub(
+; CHECK-SAME: i8 [[A:%.*]], i32 [[B:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[A]] to i32
+; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i32 [[TMP0]], 1
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 8
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 8
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]]
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i32> poison, i32 [[B]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT1]], <4 x i32> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <4 x i8> poison, i8 [[A]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT2]], <4 x i8> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = sub <4 x i8> [[BROADCAST_SPLAT]], <i8 0, i8 1, i8 2, i8 3>
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ [[TMP3]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[STEP_ADD:%.*]] = add <4 x i8> [[VEC_IND]], splat (i8 -4)
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt <4 x i8> [[VEC_IND]], zeroinitializer
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ugt <4 x i8> [[STEP_ADD]], zeroinitializer
+; CHECK-NEXT: [[TMP6:%.*]] = select <4 x i1> [[TMP4]], <4 x i32> [[BROADCAST_SPLAT2]], <4 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> [[BROADCAST_SPLAT2]], <4 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP8]] = add <4 x i32> [[TMP6]], [[VEC_PHI]]
+; CHECK-NEXT: [[TMP9]] = add <4 x i32> [[TMP7]], [[VEC_PHI3]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[STEP_ADD]], splat (i8 -4)
+; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[TMP11:%.*]] = zext <4 x i1> [[TMP5]] to <4 x i8>
+; CHECK-NEXT: [[TMP12:%.*]] = sub <4 x i8> [[STEP_ADD]], [[TMP11]]
+; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP9]], [[TMP8]]
+; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX]])
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i8> [[TMP12]], i64 3
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i8 [ [[TMP14]], %[[MIDDLE_BLOCK]] ], [ [[A]], %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP13]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i8 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[RDX_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i8 [[IV]], 0
+; CHECK-NEXT: [[ADD:%.*]] = select i1 [[CMP]], i32 [[B]], i32 0
+; CHECK-NEXT: [[RDX_NEXT]] = add nsw i32 [[ADD]], [[RDX]]
+; CHECK-NEXT: [[DEC:%.*]] = zext i1 [[CMP]] to i8
+; CHECK-NEXT: [[IV_NEXT]] = sub i8 [[IV]], [[DEC]]
+; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[RDX_NEXT_LCSSA:%.*]] = phi i32 [ [[RDX_NEXT]], %[[LOOP]] ], [ [[TMP13]], %[[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i8 [ [[IV_NEXT]], %[[LOOP]] ], [ [[TMP14]], %[[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[IV_NEXT_LCSSA]] to i32
+; CHECK-NEXT: [[R0:%.*]] = insertvalue { i32, i32 } undef, i32 [[CONV]], 0
+; CHECK-NEXT: [[R1:%.*]] = insertvalue { i32, i32 } [[R0]], i32 [[RDX_NEXT_LCSSA]], 1
+; CHECK-NEXT: ret { i32, i32 } [[R1]]
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i8 [ %a, %entry ], [ %iv.next, %loop ]
+ %rdx = phi i32 [ 0, %entry ], [ %rdx.next, %loop ]
+ %cmp = icmp ugt i8 %iv, 0
+ %add = select i1 %cmp, i32 %b, i32 0
+ %rdx.next = add nsw i32 %add, %rdx
+ %dec = zext i1 %cmp to i8
+ %iv.next = sub i8 %iv, %dec
+ br i1 %cmp, label %loop, label %exit
+
+exit:
+ %conv = zext i8 %iv.next to i32
+ %r0 = insertvalue { i32, i32 } undef, i32 %conv, 0
+ %r1 = insertvalue { i32, i32 } %r0, i32 %rdx.next, 1
+ ret { i32, i32 } %r1
+}
;.
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
@@ -172,4 +260,6 @@ exit:
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
+; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
+; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]}
;.
>From 3e8d118c6c4740920c428310558f303a6ae5323d Mon Sep 17 00:00:00 2001
From: clarence1121 <kevin25731568 at gmail.com>
Date: Sun, 9 Aug 2026 16:50:37 +0800
Subject: [PATCH 4/4] [LV][NFC] Use poison instead of undef in pr205799.ll
Address review feedback: tests should use poison rather than undef,
which also silences the undef-deprecator CI warning.
Co-Authored-By: Claude <noreply at anthropic.com>
---
llvm/test/Transforms/LoopVectorize/X86/pr205799.ll | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/test/Transforms/LoopVectorize/X86/pr205799.ll b/llvm/test/Transforms/LoopVectorize/X86/pr205799.ll
index c546c3fa785ea..fa91709bf8d0e 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/pr205799.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/pr205799.ll
@@ -67,7 +67,7 @@ define { i32, i32 } @variant_step_induction(i8 %a, i32 %b) {
; CHECK-NEXT: [[RDX_NEXT_LCSSA:%.*]] = phi i32 [ [[RDX_NEXT]], %[[LOOP]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ]
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i8 [ [[IV_NEXT]], %[[LOOP]] ], [ [[TMP12]], %[[MIDDLE_BLOCK]] ]
; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[IV_NEXT_LCSSA]] to i32
-; CHECK-NEXT: [[R0:%.*]] = insertvalue { i32, i32 } undef, i32 [[CONV]], 0
+; CHECK-NEXT: [[R0:%.*]] = insertvalue { i32, i32 } poison, i32 [[CONV]], 0
; CHECK-NEXT: [[R1:%.*]] = insertvalue { i32, i32 } [[R0]], i32 [[RDX_NEXT_LCSSA]], 1
; CHECK-NEXT: ret { i32, i32 } [[R1]]
;
@@ -86,7 +86,7 @@ loop:
exit:
%conv = zext i8 %iv.next to i32
- %r0 = insertvalue { i32, i32 } undef, i32 %conv, 0
+ %r0 = insertvalue { i32, i32 } poison, i32 %conv, 0
%r1 = insertvalue { i32, i32 } %r0, i32 %rdx.next, 1
ret { i32, i32 } %r1
}
@@ -230,7 +230,7 @@ define { i32, i32 } @variant_step_induction_sub(i8 %a, i32 %b) {
; CHECK-NEXT: [[RDX_NEXT_LCSSA:%.*]] = phi i32 [ [[RDX_NEXT]], %[[LOOP]] ], [ [[TMP13]], %[[MIDDLE_BLOCK]] ]
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i8 [ [[IV_NEXT]], %[[LOOP]] ], [ [[TMP14]], %[[MIDDLE_BLOCK]] ]
; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[IV_NEXT_LCSSA]] to i32
-; CHECK-NEXT: [[R0:%.*]] = insertvalue { i32, i32 } undef, i32 [[CONV]], 0
+; CHECK-NEXT: [[R0:%.*]] = insertvalue { i32, i32 } poison, i32 [[CONV]], 0
; CHECK-NEXT: [[R1:%.*]] = insertvalue { i32, i32 } [[R0]], i32 [[RDX_NEXT_LCSSA]], 1
; CHECK-NEXT: ret { i32, i32 } [[R1]]
;
@@ -249,7 +249,7 @@ loop:
exit:
%conv = zext i8 %iv.next to i32
- %r0 = insertvalue { i32, i32 } undef, i32 %conv, 0
+ %r0 = insertvalue { i32, i32 } poison, i32 %conv, 0
%r1 = insertvalue { i32, i32 } %r0, i32 %rdx.next, 1
ret { i32, i32 } %r1
}
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