[llvm] [AArch64] Improve lowering of pure fixed-length partial add reductions. (PR #214691)

[Adam Scott via llvm-commits]

as4230 wrote:

Don't drop this. They compose quite well I think. FoldPairwiseTo is the same idea you have for 2:1 run more than once for the 4:1 and 8:1 shapes I need. [SU]ADDLP folds one step, and i8 into i32 or i64 needs two or three. Some plain sums never leave a one-step node behind for this to catch for example like the udot_no_bin_op case in neon-partial-reduce-dot-product.ll. Merge this and I can rebase my PR.


https://github.com/llvm/llvm-project/pull/214691