[llvm] [RISCV] Canonicalize mask-producing SETCC for easier conversion on the consuming instruction to be VL-predicate (PR #214877)
Min-Yih Hsu via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 8 12:45:10 PDT 2026
https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/214877
>From 60b75fe98705bb4664eaca30e3b82a523de8cbe8 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Fri, 7 Aug 2026 14:48:38 -0700
Subject: [PATCH 1/3] Pre-commit Tests
---
.../RISCV/rvv/masked-load-vl-predicatable.ll | 236 ++++++++++++++++++
1 file changed, 236 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/masked-load-vl-predicatable.ll
diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-load-vl-predicatable.ll b/llvm/test/CodeGen/RISCV/rvv/masked-load-vl-predicatable.ll
new file mode 100644
index 0000000000000..7d82175322d21
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/masked-load-vl-predicatable.ll
@@ -0,0 +1,236 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -O3 -mtriple=riscv64 -mattr=+v,+d,+b,+unaligned-vector-mem < %s | FileCheck %s
+
+define <16 x float> @masked_load(ptr %p, i32 signext %n, i32 signext %iv) nounwind {
+; CHECK-LABEL: masked_load:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vor.vx v8, v8, a2
+; CHECK-NEXT: vmsltu.vx v0, v8, a1
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: ret
+ %11 = insertelement <16 x i32> poison, i32 %iv, i32 0
+ %12 = shufflevector <16 x i32> %11, <16 x i32> poison, <16 x i32> zeroinitializer
+ %13 = or disjoint <16 x i32> %12, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %14 = insertelement <16 x i32> poison, i32 %n, i32 0
+ %15 = shufflevector <16 x i32> %14, <16 x i32> poison, <16 x i32> zeroinitializer
+ %16 = icmp ult <16 x i32> %13, %15
+ %19 = tail call <16 x float> @llvm.masked.load(ptr %p, <16 x i1> %16, <16 x float> zeroinitializer)
+ ret <16 x float> %19
+}
+
+define <16 x float> @masked_load_no_passthru(ptr %p, i32 signext %n, i32 signext %iv) nounwind {
+; CHECK-LABEL: masked_load_no_passthru:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vor.vx v8, v8, a2
+; CHECK-NEXT: vmsltu.vx v0, v8, a1
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: ret
+ %11 = insertelement <16 x i32> poison, i32 %iv, i32 0
+ %12 = shufflevector <16 x i32> %11, <16 x i32> poison, <16 x i32> zeroinitializer
+ %13 = or disjoint <16 x i32> %12, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %14 = insertelement <16 x i32> poison, i32 %n, i32 0
+ %15 = shufflevector <16 x i32> %14, <16 x i32> poison, <16 x i32> zeroinitializer
+ %16 = icmp ult <16 x i32> %13, %15
+ %19 = tail call <16 x float> @llvm.masked.load(ptr %p, <16 x i1> %16, <16 x float> splat (float poison))
+ ret <16 x float> %19
+}
+
+define <16 x float> @masked_load_add(ptr %p, i32 signext %n, i32 signext %iv) nounwind {
+; CHECK-LABEL: masked_load_add:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vadd.vx v8, v8, a2
+; CHECK-NEXT: vmsltu.vx v0, v8, a1
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: ret
+ %11 = insertelement <16 x i32> poison, i32 %iv, i32 0
+ %12 = shufflevector <16 x i32> %11, <16 x i32> poison, <16 x i32> zeroinitializer
+ %13 = add nuw <16 x i32> %12, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %14 = insertelement <16 x i32> poison, i32 %n, i32 0
+ %15 = shufflevector <16 x i32> %14, <16 x i32> poison, <16 x i32> zeroinitializer
+ %16 = icmp ult <16 x i32> %13, %15
+ %19 = tail call <16 x float> @llvm.masked.load(ptr %p, <16 x i1> %16, <16 x float> zeroinitializer)
+ ret <16 x float> %19
+}
+
+define <16 x float> @masked_load_gt(ptr %p, i32 signext %n, i32 signext %iv) nounwind {
+; CHECK-LABEL: masked_load_gt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vor.vx v8, v8, a2
+; CHECK-NEXT: vmsltu.vx v0, v8, a1
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: ret
+ %11 = insertelement <16 x i32> poison, i32 %iv, i32 0
+ %12 = shufflevector <16 x i32> %11, <16 x i32> poison, <16 x i32> zeroinitializer
+ %13 = or disjoint <16 x i32> %12, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %14 = insertelement <16 x i32> poison, i32 %n, i32 0
+ %15 = shufflevector <16 x i32> %14, <16 x i32> poison, <16 x i32> zeroinitializer
+ %16 = icmp ugt <16 x i32> %15, %13
+ %19 = tail call <16 x float> @llvm.masked.load(ptr %p, <16 x i1> %16, <16 x float> zeroinitializer)
+ ret <16 x float> %19
+}
+
+define <16 x float> @masked_load_signed_cmp(ptr %p, i32 signext %n, i32 signext %iv) nounwind {
+; CHECK-LABEL: masked_load_signed_cmp:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vor.vx v8, v8, a2
+; CHECK-NEXT: vmslt.vx v0, v8, a1
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: ret
+ %11 = insertelement <16 x i32> poison, i32 %iv, i32 0
+ %12 = shufflevector <16 x i32> %11, <16 x i32> poison, <16 x i32> zeroinitializer
+ %13 = or disjoint <16 x i32> %12, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %14 = insertelement <16 x i32> poison, i32 %n, i32 0
+ %15 = shufflevector <16 x i32> %14, <16 x i32> poison, <16 x i32> zeroinitializer
+ %16 = icmp slt <16 x i32> %13, %15
+ %19 = tail call <16 x float> @llvm.masked.load(ptr %p, <16 x i1> %16, <16 x float> zeroinitializer)
+ ret <16 x float> %19
+}
+
+define <16 x float> @masked_load_sgt(ptr %p, i32 signext %n, i32 signext %iv) nounwind {
+; CHECK-LABEL: masked_load_sgt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vor.vx v8, v8, a2
+; CHECK-NEXT: vmslt.vx v0, v8, a1
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: ret
+ %11 = insertelement <16 x i32> poison, i32 %iv, i32 0
+ %12 = shufflevector <16 x i32> %11, <16 x i32> poison, <16 x i32> zeroinitializer
+ %13 = or disjoint <16 x i32> %12, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %14 = insertelement <16 x i32> poison, i32 %n, i32 0
+ %15 = shufflevector <16 x i32> %14, <16 x i32> poison, <16 x i32> zeroinitializer
+ %16 = icmp sgt <16 x i32> %15, %13
+ %19 = tail call <16 x float> @llvm.masked.load(ptr %p, <16 x i1> %16, <16 x float> zeroinitializer)
+ ret <16 x float> %19
+}
+
+define <16 x float> @masked_load_get_active_lane(ptr %p, i32 signext %n, i32 signext %iv) nounwind {
+; CHECK-LABEL: masked_load_get_active_lane:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: vor.vx v8, v8, a2
+; CHECK-NEXT: vmsltu.vx v0, v8, a1
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: ret
+ %s = shl i32 %iv, 4
+ %m = tail call <16 x i1> @llvm.get.active.lane.mask(i32 %s, i32 %n)
+ %l = tail call <16 x float> @llvm.masked.load(ptr %p, <16 x i1> %m, <16 x float> zeroinitializer)
+ ret <16 x float> %l
+}
+
+define <64 x float> @masked_load_wide(ptr %p, i32 signext %n, i32 signext %iv) nounwind {
+; CHECK-LABEL: masked_load_wide:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a3, 32
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vor.vx v16, v8, a2
+; CHECK-NEXT: vmsltu.vx v0, v16, a1
+; CHECK-NEXT: vadd.vx v24, v8, a3
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vor.vx v24, v24, a2
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: vmsltu.vx v0, v24, a1
+; CHECK-NEXT: addi a0, a0, 128
+; CHECK-NEXT: vle32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+ %11 = insertelement <64 x i32> poison, i32 %iv, i32 0
+ %12 = shufflevector <64 x i32> %11, <64 x i32> poison, <64 x i32> zeroinitializer
+ %13 = or disjoint <64 x i32> %12, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
+ %14 = insertelement <64 x i32> poison, i32 %n, i32 0
+ %15 = shufflevector <64 x i32> %14, <64 x i32> poison, <64 x i32> zeroinitializer
+ %16 = icmp ult <64 x i32> %13, %15
+ %19 = tail call <64 x float> @llvm.masked.load(ptr %p, <64 x i1> %16, <64 x float> zeroinitializer)
+ ret <64 x float> %19
+}
+
+define <64 x float> @masked_load_get_active_lane_wide(ptr %p, i32 signext %n, i32 signext %iv) nounwind {
+; CHECK-LABEL: masked_load_get_active_lane_wide:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a3, 32
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: slli a2, a2, 6
+; CHECK-NEXT: vor.vx v16, v8, a2
+; CHECK-NEXT: vmsltu.vx v0, v16, a1
+; CHECK-NEXT: vadd.vx v24, v8, a3
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vor.vx v24, v24, a2
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: vmsltu.vx v0, v24, a1
+; CHECK-NEXT: addi a0, a0, 128
+; CHECK-NEXT: vle32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+ %s = shl i32 %iv, 6
+ %m = tail call <64 x i1> @llvm.get.active.lane.mask(i32 %s, i32 %n)
+ %l = tail call <64 x float> @llvm.masked.load(ptr %p, <64 x i1> %m, <64 x float> zeroinitializer)
+ ret <64 x float> %l
+}
+
+; We're not sure if the add between %iv and step vector will overflow or not.
+define <16 x float> @negative_masked_load_add(ptr %p, i32 signext %n, i32 signext %iv) nounwind {
+; CHECK-LABEL: negative_masked_load_add:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vadd.vx v8, v8, a2
+; CHECK-NEXT: vmsltu.vx v0, v8, a1
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: ret
+ %11 = insertelement <16 x i32> poison, i32 %iv, i32 0
+ %12 = shufflevector <16 x i32> %11, <16 x i32> poison, <16 x i32> zeroinitializer
+ %13 = add <16 x i32> %12, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %14 = insertelement <16 x i32> poison, i32 %n, i32 0
+ %15 = shufflevector <16 x i32> %14, <16 x i32> poison, <16 x i32> zeroinitializer
+ %16 = icmp ult <16 x i32> %13, %15
+ %19 = tail call <16 x float> @llvm.masked.load(ptr %p, <16 x i1> %16, <16 x float> zeroinitializer)
+ ret <16 x float> %19
+}
+
+define <16 x float> @negative_masked_load_wrong_step_vector(ptr %p, i32 signext %n, i32 signext %iv) nounwind {
+; CHECK-LABEL: negative_masked_load_wrong_step_vector:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.x v8, a2
+; CHECK-NEXT: lui a2, %hi(.LCPI10_0)
+; CHECK-NEXT: addi a2, a2, %lo(.LCPI10_0)
+; CHECK-NEXT: vle8.v v14, (a2)
+; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsext.vf2 v12, v14
+; CHECK-NEXT: vwadd.wv v8, v8, v12
+; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; CHECK-NEXT: vmsltu.vx v0, v8, a1
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: ret
+ %11 = insertelement <16 x i32> poison, i32 %iv, i32 0
+ %12 = shufflevector <16 x i32> %11, <16 x i32> poison, <16 x i32> zeroinitializer
+ %13 = or disjoint <16 x i32> %12, <i32 1, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %14 = insertelement <16 x i32> poison, i32 %n, i32 0
+ %15 = shufflevector <16 x i32> %14, <16 x i32> poison, <16 x i32> zeroinitializer
+ %16 = icmp ult <16 x i32> %13, %15
+ %19 = tail call <16 x float> @llvm.masked.load(ptr %p, <16 x i1> %16, <16 x float> zeroinitializer)
+ ret <16 x float> %19
+}
>From 60391255b96eeb73fd84fa71041693b4c50642db Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Fri, 7 Aug 2026 14:38:49 -0700
Subject: [PATCH 2/3] [RISCV] Canonicalize vector SETCC for easier conversion
to VL-predicate
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 85 +++++++++++++++++++
.../RISCV/rvv/masked-load-vl-predicatable.ll | 57 +++++++------
2 files changed, 117 insertions(+), 25 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ea4803e59ebc1..9d5566c0cee30 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -18750,6 +18750,88 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &D
return true;
}
+/// Given
+/// ```
+/// %b = splat %base
+/// %s = <%offset, %offset + 1, %offset + 2, %offset + 3, ...>
+/// %a = add nuw %b, %s
+/// %N = splat %n
+/// %p = setcc ult %a, %N
+/// ```
+/// in which the SETCC's condition code could be (U)LT or (U)GT.
+/// We can turn it into
+/// ```
+/// %s = <0, 1, 2, 3, ...>
+/// %m = sub %n, min(%n, %base + %offset)
+/// %M = splat %m
+/// %p = setcc ult %s, %M
+/// ```
+/// where the SETCC's condition code is also canonicalized into (U)LT;
+/// The idea behind this canonicalization is that if %p is used as a mask
+/// in a masked.load/store, we can easily turn it to use VL-predicate later
+/// by assigning `vl = min(%m, <number of vector elements>)`.
+static SDValue canonicalizeMaskForVLPredicate(EVT MaskVT, SDValue LHS,
+ SDValue RHS, ISD::CondCode CC,
+ const SDLoc &DL,
+ SelectionDAG &DAG) {
+ using namespace SDPatternMatch;
+ if (!MaskVT.isFixedLengthVector() ||
+ !(CC == ISD::SETUGT || CC == ISD::SETGT || CC == ISD::SETULT ||
+ CC == ISD::SETLT))
+ return SDValue();
+
+ // Canonicalize the comparison.
+ if (CC == ISD::SETUGT || CC == ISD::SETGT) {
+ std::swap(LHS, RHS);
+ // Flip the 'L' and 'G' bits.
+ CC = ISD::CondCode(static_cast<unsigned>(CC) ^ 6);
+ }
+ bool IsSigned = ISD::isSignedIntSetCC(CC);
+
+ SDValue Boundary = DAG.getSplatValue(RHS, /*LegalizeType=*/true);
+ if (!Boundary)
+ return SDValue();
+
+ SDValue LHSOp0, LHSOp1;
+ if (IsSigned) {
+ if (!sd_match(LHS, m_NSWAddLike(m_Value(LHSOp0), m_Value(LHSOp1))))
+ return SDValue();
+ } else {
+ if (!sd_match(LHS, m_NUWAddLike(m_Value(LHSOp0), m_Value(LHSOp1))))
+ return SDValue();
+ }
+
+ SDValue BaseIndex = DAG.getSplatValue(LHSOp0, /*LegalizeType=*/true);
+ if (!BaseIndex) {
+ std::swap(LHSOp0, LHSOp1);
+ BaseIndex = DAG.getSplatValue(LHSOp0, /*LegalizeType=*/true);
+ }
+ if (!BaseIndex || !isa<BuildVectorSDNode>(LHSOp1) ||
+ BaseIndex.getValueType() != Boundary.getValueType())
+ return SDValue();
+
+ // Return {a,n} from a build_vector sequence of {a, a+n, a+2n, a+3n, ....}
+ auto StepVector = cast<BuildVectorSDNode>(LHSOp1)->isArithmeticSequence();
+ if (!StepVector || !StepVector->second.isOne())
+ return SDValue();
+ EVT LenVT = BaseIndex.getValueType();
+ const APInt &Start = StepVector->first;
+ unsigned LenWidth = LenVT.getScalarSizeInBits();
+ APInt Offset =
+ IsSigned ? Start.sextOrTrunc(LenWidth) : Start.zextOrTrunc(LenWidth);
+
+ unsigned MinOpc = IsSigned ? ISD::SMIN : ISD::UMIN;
+ SDValue NewStepVector = DAG.getStepVector(DL, LHS.getValueType());
+ BaseIndex = DAG.getNode(
+ ISD::ADD, DL, LenVT, BaseIndex, DAG.getConstant(Offset, DL, LenVT),
+ IsSigned ? SDNodeFlags::NoSignedWrap : SDNodeFlags::NoUnsignedWrap);
+ BaseIndex = DAG.getNode(MinOpc, DL, LenVT, Boundary, BaseIndex);
+ Boundary = DAG.getNode(ISD::SUB, DL, LenVT, Boundary, BaseIndex);
+ Boundary = DAG.getSplat(RHS.getValueType(), DL, Boundary);
+
+ return DAG.getSetCC(DL, MaskVT, NewStepVector, Boundary, CC);
+}
+
/// Try to map an integer comparison with size > XLEN to vector instructions
/// before type legalization splits it up into chunks.
static SDValue
@@ -18879,6 +18961,9 @@ static SDValue performSETCCCombine(SDNode *N,
EVT OpVT = N0.getValueType();
ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
+ if (SDValue V = canonicalizeMaskForVLPredicate(VT, N0, N1, Cond, dl, DAG))
+ return V;
+
// Looking for an equality compare.
if (!isIntEqualitySetCC(Cond))
return SDValue();
diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-load-vl-predicatable.ll b/llvm/test/CodeGen/RISCV/rvv/masked-load-vl-predicatable.ll
index 7d82175322d21..ec311c9c393e7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/masked-load-vl-predicatable.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/masked-load-vl-predicatable.ll
@@ -6,7 +6,8 @@ define <16 x float> @masked_load(ptr %p, i32 signext %n, i32 signext %iv) nounwi
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vid.v v8
-; CHECK-NEXT: vor.vx v8, v8, a2
+; CHECK-NEXT: maxu a1, a1, a2
+; CHECK-NEXT: sub a1, a1, a2
; CHECK-NEXT: vmsltu.vx v0, v8, a1
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vle32.v v8, (a0), v0.t
@@ -26,7 +27,8 @@ define <16 x float> @masked_load_no_passthru(ptr %p, i32 signext %n, i32 signext
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vid.v v8
-; CHECK-NEXT: vor.vx v8, v8, a2
+; CHECK-NEXT: maxu a1, a1, a2
+; CHECK-NEXT: sub a1, a1, a2
; CHECK-NEXT: vmsltu.vx v0, v8, a1
; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: ret
@@ -45,7 +47,8 @@ define <16 x float> @masked_load_add(ptr %p, i32 signext %n, i32 signext %iv) no
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vid.v v8
-; CHECK-NEXT: vadd.vx v8, v8, a2
+; CHECK-NEXT: maxu a1, a1, a2
+; CHECK-NEXT: sub a1, a1, a2
; CHECK-NEXT: vmsltu.vx v0, v8, a1
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vle32.v v8, (a0), v0.t
@@ -65,7 +68,8 @@ define <16 x float> @masked_load_gt(ptr %p, i32 signext %n, i32 signext %iv) nou
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vid.v v8
-; CHECK-NEXT: vor.vx v8, v8, a2
+; CHECK-NEXT: maxu a1, a1, a2
+; CHECK-NEXT: sub a1, a1, a2
; CHECK-NEXT: vmsltu.vx v0, v8, a1
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vle32.v v8, (a0), v0.t
@@ -85,7 +89,8 @@ define <16 x float> @masked_load_signed_cmp(ptr %p, i32 signext %n, i32 signext
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vid.v v8
-; CHECK-NEXT: vor.vx v8, v8, a2
+; CHECK-NEXT: min a2, a1, a2
+; CHECK-NEXT: sub a1, a1, a2
; CHECK-NEXT: vmslt.vx v0, v8, a1
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vle32.v v8, (a0), v0.t
@@ -105,7 +110,8 @@ define <16 x float> @masked_load_sgt(ptr %p, i32 signext %n, i32 signext %iv) no
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vid.v v8
-; CHECK-NEXT: vor.vx v8, v8, a2
+; CHECK-NEXT: min a2, a1, a2
+; CHECK-NEXT: sub a1, a1, a2
; CHECK-NEXT: vmslt.vx v0, v8, a1
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vle32.v v8, (a0), v0.t
@@ -125,8 +131,9 @@ define <16 x float> @masked_load_get_active_lane(ptr %p, i32 signext %n, i32 sig
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vid.v v8
-; CHECK-NEXT: slli a2, a2, 4
-; CHECK-NEXT: vor.vx v8, v8, a2
+; CHECK-NEXT: slliw a2, a2, 4
+; CHECK-NEXT: maxu a1, a1, a2
+; CHECK-NEXT: sub a1, a1, a2
; CHECK-NEXT: vmsltu.vx v0, v8, a1
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vle32.v v8, (a0), v0.t
@@ -142,17 +149,17 @@ define <64 x float> @masked_load_wide(ptr %p, i32 signext %n, i32 signext %iv) n
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu
-; CHECK-NEXT: vid.v v8
-; CHECK-NEXT: vor.vx v16, v8, a2
+; CHECK-NEXT: vid.v v24
+; CHECK-NEXT: vadd.vx v16, v24, a3
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: maxu a1, a1, a2
+; CHECK-NEXT: sub a1, a1, a2
; CHECK-NEXT: vmsltu.vx v0, v16, a1
-; CHECK-NEXT: vadd.vx v24, v8, a3
; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vor.vx v24, v24, a2
-; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: addi a2, a0, 128
+; CHECK-NEXT: vle32.v v16, (a2), v0.t
; CHECK-NEXT: vmsltu.vx v0, v24, a1
-; CHECK-NEXT: addi a0, a0, 128
-; CHECK-NEXT: vle32.v v16, (a0), v0.t
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: ret
%11 = insertelement <64 x i32> poison, i32 %iv, i32 0
%12 = shufflevector <64 x i32> %11, <64 x i32> poison, <64 x i32> zeroinitializer
@@ -169,18 +176,18 @@ define <64 x float> @masked_load_get_active_lane_wide(ptr %p, i32 signext %n, i3
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu
-; CHECK-NEXT: vid.v v8
-; CHECK-NEXT: slli a2, a2, 6
-; CHECK-NEXT: vor.vx v16, v8, a2
+; CHECK-NEXT: vid.v v24
+; CHECK-NEXT: vadd.vx v16, v24, a3
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: slliw a2, a2, 6
+; CHECK-NEXT: maxu a1, a1, a2
+; CHECK-NEXT: sub a1, a1, a2
; CHECK-NEXT: vmsltu.vx v0, v16, a1
-; CHECK-NEXT: vadd.vx v24, v8, a3
; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vor.vx v24, v24, a2
-; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: addi a2, a0, 128
+; CHECK-NEXT: vle32.v v16, (a2), v0.t
; CHECK-NEXT: vmsltu.vx v0, v24, a1
-; CHECK-NEXT: addi a0, a0, 128
-; CHECK-NEXT: vle32.v v16, (a0), v0.t
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: ret
%s = shl i32 %iv, 6
%m = tail call <64 x i1> @llvm.get.active.lane.mask(i32 %s, i32 %n)
>From f921aea6eef55ac4680707eb6c33fb57e6d2bef3 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Fri, 7 Aug 2026 16:27:11 -0700
Subject: [PATCH 3/3] fixup! Reject non-integer comparison
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 9d5566c0cee30..b42eabda1d3fa 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -18777,7 +18777,8 @@ static SDValue canonicalizeMaskForVLPredicate(EVT MaskVT, SDValue LHS,
using namespace SDPatternMatch;
if (!MaskVT.isFixedLengthVector() ||
!(CC == ISD::SETUGT || CC == ISD::SETGT || CC == ISD::SETULT ||
- CC == ISD::SETLT))
+ CC == ISD::SETLT) ||
+ !LHS.getValueType().isInteger())
return SDValue();
// Canonicalize the comparison.
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