[llvm] fe4a02e - [AMDGPU] Fix a decoder crash in disassembler (#214969)

[via llvm-commits]

Author: Shilei Tian
Date: 2026-08-08T14:13:56-04:00
New Revision: fe4a02e9ccc5a0e612eeaca9a384040455504bd0

URL: https://github.com/llvm/llvm-project/commit/fe4a02e9ccc5a0e612eeaca9a384040455504bd0
DIFF: https://github.com/llvm/llvm-project/commit/fe4a02e9ccc5a0e612eeaca9a384040455504bd0.diff

LOG: [AMDGPU] Fix a decoder crash in disassembler (#214969)

Fixes #214915.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
    llvm/test/MC/Disassembler/AMDGPU/decode-err.txt

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 526d9f1bf8eb4..d8378895a7335 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -218,7 +218,8 @@ static DecodeStatus decodeDpp8FI(MCInst &Inst, unsigned Val, uint64_t Addr,
 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm)                           \
   static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,      \
                            const MCDisassembler *Decoder) {                    \
-    assert(Imm < (1 << EncSize) && #EncSize "-bit encoding");                  \
+    if (!isUInt<EncSize>(Imm))                                                 \
+      return MCDisassembler::Fail;                                             \
     auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
     return addOperand(Inst, DAsm->decodeSrcOp(Inst, OpWidth, EncImm));         \
   }

diff  --git a/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt b/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
index 6855d2e687951..71b6214eb6be3 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
@@ -7,6 +7,16 @@
 # GCN-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
 0xdf,0x00,0x00,0x02
 
+# This is v_readfirstlane_b32 with an SGPR destination that does not fit the
+# 7-bit scalar register encoding of the 8-bit VOP1 vdst field.
+# GCN-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
+0x00,0x05,0xf4,0x7f
+
+# This is v_s_exp_f32 with an SGPR destination that does not fit the 7-bit
+# scalar register encoding of the 8-bit VOP3 vdst field.
+# GFX12-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
+0xfa,0x00,0x80,0xd6,0x01,0x00,0x01,0x02
+
 # this is s_waitcnt_vscnt exec_hi, 0x1234, which is valid on gfx11, but not on gfx12
 # GFX12-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
 0x34,0x12,0x7f,0xbc