[llvm] [AMDGPU][MC] Check lit64 availability because decode (PR #214976)

[via llvm-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Shilei Tian (shiltian)

<details>
<summary>Changes</summary>

Fixes #<!-- -->214953.


---
Full diff: https://github.com/llvm/llvm-project/pull/214976.diff


2 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (+7) 
- (added) llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_lit64_err.txt (+30) 


``````````diff
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 526d9f1bf8eb4..4f8375d12ef5f 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -2061,6 +2061,13 @@ MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp(const MCInst &Inst,
     return MCOperand::createImm(Val);
 
   if (Val == LITERAL64_CONST && STI.hasFeature(AMDGPU::Feature64BitLiterals)) {
+    // Only VOP1, VOP2, VOPC, SOP1, SOP2 and SOPC may encode a 64-bit literal.
+    // VOP3, VOP3P and VOPD have to use a 32-bit one.
+    if (SIInstrFlags::isVOP3Like(*MCII, Inst) ||
+        AMDGPU::isVOPD(Inst.getOpcode())) {
+      return errOperand(Val,
+                        "64-bit literal is not supported by this instruction");
+    }
     return decodeLiteral64Constant();
   }
 
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_lit64_err.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_lit64_err.txt
new file mode 100644
index 0000000000000..fd123d32b5224
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_lit64_err.txt
@@ -0,0 +1,30 @@
+# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
+# RUN: not llvm-mc -disassemble -triple=amdgpu12.50 -filetype=null < %s 2>&1 | FileCheck --implicit-check-not=warning: --check-prefix=GFX1250 %s
+
+# The 64-bit literal source selector 254 is only available to the VOP1, VOP2,
+# VOPC, SOP1, SOP2 and SOPC formats. Replacing the 32-bit literal selector 255
+# with it must not decode.
+
+# v_add_f64_e64 v[0:1], lit64(0x10abcdef12345678), v[2:3]
+[0x00,0x00,0x02,0xd5,0xfe,0x04,0x02,0x02,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
+# GFX1250: :[[@LINE-1]]:2: warning: invalid instruction encoding
+
+# v_fma_f32 v0, v1, lit64(0x10abcdef12345678), v2
+[0x00,0x00,0x13,0xd6,0x01,0xfd,0x09,0x04,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
+# GFX1250: :[[@LINE-1]]:2: warning: invalid instruction encoding
+
+# v_fma_f32 v0, v1, v2, lit64(0x10abcdef12345678)
+[0x00,0x00,0x13,0xd6,0x01,0x05,0xfa,0x03,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
+# GFX1250: :[[@LINE-1]]:2: warning: invalid instruction encoding
+
+# v_pk_add_f32 v[0:1], lit64(0x10abcdef12345678), v[2:3]
+[0x00,0x40,0x29,0xcc,0xfe,0x04,0x02,0x1a,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
+# GFX1250: :[[@LINE-1]]:2: warning: invalid instruction encoding
+
+# v_dual_mul_f32 v0, lit64(0x10abcdef12345678), v2 :: v_dual_mul_f32 v3, v4, v5
+[0xfe,0x04,0xc6,0xc8,0x04,0x0b,0x02,0x00,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
+# GFX1250: :[[@LINE-1]]:2: warning: invalid instruction encoding
+
+# v_dual_mul_f32 v0, v1, v2 :: v_dual_mul_f32 v3, lit64(0x10abcdef12345678), v5
+[0x01,0x05,0xc6,0xc8,0xfe,0x0a,0x02,0x00,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
+# GFX1250: :[[@LINE-1]]:2: warning: invalid instruction encoding

``````````

</details>


https://github.com/llvm/llvm-project/pull/214976