[llvm] [AMDGPU][MC] Check availability of certain registers (PR #214973)
Shilei Tian via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 8 08:07:14 PDT 2026
https://github.com/shiltian created https://github.com/llvm/llvm-project/pull/214973
Fixes #214952.
>From 92a87059476e604d25853b0fae383bedbcb38c55 Mon Sep 17 00:00:00 2001
From: Shilei Tian <i at tianshilei.me>
Date: Sat, 8 Aug 2026 11:06:29 -0400
Subject: [PATCH] [AMDGPU][MC] Check availability of certain registers
Fixes #214952.
---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 3 +-
.../Disassembler/AMDGPUDisassembler.cpp | 51 ++++++++++++----
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 5 ++
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 6 ++
llvm/test/MC/AMDGPU/gfx1250_asm_operands.s | 15 ++++-
llvm/test/MC/AMDGPU/literals.s | 59 +++++++++++--------
.../MC/Disassembler/AMDGPU/decode-err.txt | 30 ++++++++++
7 files changed, 130 insertions(+), 39 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 4c3038db2c747..b84b6c833a75e 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -7072,11 +7072,12 @@ bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
case SRC_SHARED_BASE:
case SRC_SHARED_LIMIT_LO:
case SRC_SHARED_LIMIT:
+ return isGFX9Plus();
case SRC_PRIVATE_BASE_LO:
case SRC_PRIVATE_BASE:
case SRC_PRIVATE_LIMIT_LO:
case SRC_PRIVATE_LIMIT:
- return isGFX9Plus();
+ return AMDGPU::hasPrivateApertureRegs(getSTI());
case SRC_FLAT_SCRATCH_BASE_LO:
case SRC_FLAT_SCRATCH_BASE_HI:
return hasGloballyAddressableScratch();
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 526d9f1bf8eb4..51f41e4a67953 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -2118,11 +2118,26 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
case 231: return createRegOperand(SRC_FLAT_SCRATCH_BASE_HI);
case 235: return createRegOperand(SRC_SHARED_BASE_LO);
case 236: return createRegOperand(SRC_SHARED_LIMIT_LO);
- case 237: return createRegOperand(SRC_PRIVATE_BASE_LO);
- case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO);
- case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
- case 251: return createRegOperand(SRC_VCCZ);
- case 252: return createRegOperand(SRC_EXECZ);
+ case 237:
+ if (AMDGPU::hasPrivateApertureRegs(STI))
+ return createRegOperand(SRC_PRIVATE_BASE_LO);
+ break;
+ case 238:
+ if (AMDGPU::hasPrivateApertureRegs(STI))
+ return createRegOperand(SRC_PRIVATE_LIMIT_LO);
+ break;
+ case 239:
+ if (AMDGPU::hasPopsExitingWaveID(STI))
+ return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
+ break;
+ case 251:
+ if (!isGFX11Plus())
+ return createRegOperand(SRC_VCCZ);
+ break;
+ case 252:
+ if (!isGFX11Plus())
+ return createRegOperand(SRC_EXECZ);
+ break;
case 253: return createRegOperand(SRC_SCC);
case 254: return createRegOperand(LDS_DIRECT);
default: break;
@@ -2152,11 +2167,26 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
case 230: return createRegOperand(SRC_FLAT_SCRATCH_BASE_LO);
case 235: return createRegOperand(SRC_SHARED_BASE);
case 236: return createRegOperand(SRC_SHARED_LIMIT);
- case 237: return createRegOperand(SRC_PRIVATE_BASE);
- case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
- case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
- case 251: return createRegOperand(SRC_VCCZ);
- case 252: return createRegOperand(SRC_EXECZ);
+ case 237:
+ if (AMDGPU::hasPrivateApertureRegs(STI))
+ return createRegOperand(SRC_PRIVATE_BASE);
+ break;
+ case 238:
+ if (AMDGPU::hasPrivateApertureRegs(STI))
+ return createRegOperand(SRC_PRIVATE_LIMIT);
+ break;
+ case 239:
+ if (AMDGPU::hasPopsExitingWaveID(STI))
+ return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
+ break;
+ case 251:
+ if (!isGFX11Plus())
+ return createRegOperand(SRC_VCCZ);
+ break;
+ case 252:
+ if (!isGFX11Plus())
+ return createRegOperand(SRC_EXECZ);
+ break;
case 253: return createRegOperand(SRC_SCC);
default: break;
}
@@ -2372,7 +2402,6 @@ bool AMDGPUDisassembler::hasArchitectedFlatScratch() const {
bool AMDGPUDisassembler::hasKernargPreload() const {
return AMDGPU::hasKernargPreload(STI);
}
-
//===----------------------------------------------------------------------===//
// AMDGPU specific symbol handling
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 38329d6295538..b2b1e4237367d 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -2562,6 +2562,11 @@ bool hasPopsExitingWaveID(const MCSubtargetInfo &STI) {
return STI.hasFeature(AMDGPU::FeaturePopsExitingWaveID);
}
+bool hasPrivateApertureRegs(const MCSubtargetInfo &STI) {
+ return STI.hasFeature(AMDGPU::FeatureApertureRegs) &&
+ !STI.hasFeature(AMDGPU::FeatureGloballyAddressableScratch);
+}
+
bool isGFX10(const MCSubtargetInfo &STI) {
return STI.hasFeature(AMDGPU::FeatureGFX10);
}
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 44476d4d555c0..7d0bdbc661bc1 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -1525,6 +1525,12 @@ bool isGFX940(const MCSubtargetInfo &STI);
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI);
bool hasMAIInsts(const MCSubtargetInfo &STI);
bool hasPopsExitingWaveID(const MCSubtargetInfo &STI);
+
+/// \returns true if the src_private_base and src_private_limit aperture
+/// registers are available on \p STI. Targets with globally addressable
+/// scratch have no private aperture and expose src_flat_scratch_base instead.
+bool hasPrivateApertureRegs(const MCSubtargetInfo &STI);
+
bool hasVOPD(const MCSubtargetInfo &STI);
bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI);
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_operands.s b/llvm/test/MC/AMDGPU/gfx1250_asm_operands.s
index f6746af03df41..14ad95cbf7366 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_operands.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_operands.s
@@ -1,5 +1,6 @@
// RUN: not llvm-mc -triple=amdgpu12.00 -filetype=null %s 2>&1 | FileCheck --check-prefixes=GFX1200-ERR %s
-// RUN: llvm-mc -triple=amdgpu12.50 -show-encoding %s | FileCheck --check-prefix=GFX1250 %s
+// RUN: not llvm-mc -triple=amdgpu12.50 -filetype=null %s 2>&1 | FileCheck --check-prefixes=GFX1250-ERR %s
+// RUN: not llvm-mc -triple=amdgpu12.50 -show-encoding %s | FileCheck --check-prefix=GFX1250 %s
s_mov_b32 s0, src_flat_scratch_base_lo
// GFX1200-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: src_flat_scratch_base_lo register not available on this GPU
@@ -25,6 +26,18 @@ s_mov_b64 s[0:1], shared_limit
s_mov_b64 s[0:1], src_shared_limit
// GFX1250: encoding: [0xec,0x01,0x80,0xbe]
+s_mov_b32 s0, src_private_base
+// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: src_private_base register not available on this GPU
+
+s_mov_b32 s0, src_private_limit
+// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: src_private_limit register not available on this GPU
+
+s_mov_b64 s[0:1], src_private_base
+// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: src_private_base register not available on this GPU
+
+s_mov_b64 s[0:1], src_private_limit
+// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: src_private_limit register not available on this GPU
+
s_getreg_b32 s1, hwreg(33)
// GFX1250: encoding: [0x21,0xf8,0x81,0xb8]
diff --git a/llvm/test/MC/AMDGPU/literals.s b/llvm/test/MC/AMDGPU/literals.s
index 391fb93c55926..471d484a4df3b 100644
--- a/llvm/test/MC/AMDGPU/literals.s
+++ b/llvm/test/MC/AMDGPU/literals.s
@@ -1406,17 +1406,19 @@ s_add_i32 s0, src_shared_limit, s0
s_add_i32 s0, src_private_base, s0
// GFX11: s_add_i32 s0, src_private_base, s0 ; encoding: [0xed,0x00,0x00,0x81]
-// GFX12XX: s_add_co_i32 s0, src_private_base, s0 ; encoding: [0xed,0x00,0x00,0x81]
+// GFX12: s_add_co_i32 s0, src_private_base, s0 ; encoding: [0xed,0x00,0x00,0x81]
// GFX9: s_add_i32 s0, src_private_base, s0 ; encoding: [0xed,0x00,0x00,0x81]
-// NOSICI: :[[@LINE-4]]:15: error: src_private_base register not available on this GPU
-// NOVI: :[[@LINE-5]]:15: error: src_private_base register not available on this GPU
+// NOGFX1250: :[[@LINE-4]]:15: error: src_private_base register not available on this GPU
+// NOSICI: :[[@LINE-5]]:15: error: src_private_base register not available on this GPU
+// NOVI: :[[@LINE-6]]:15: error: src_private_base register not available on this GPU
s_add_i32 s0, src_private_limit, s0
// GFX11: s_add_i32 s0, src_private_limit, s0 ; encoding: [0xee,0x00,0x00,0x81]
-// GFX12XX: s_add_co_i32 s0, src_private_limit, s0 ; encoding: [0xee,0x00,0x00,0x81]
+// GFX12: s_add_co_i32 s0, src_private_limit, s0 ; encoding: [0xee,0x00,0x00,0x81]
// GFX9: s_add_i32 s0, src_private_limit, s0 ; encoding: [0xee,0x00,0x00,0x81]
-// NOSICI: :[[@LINE-4]]:15: error: src_private_limit register not available on this GPU
-// NOVI: :[[@LINE-5]]:15: error: src_private_limit register not available on this GPU
+// NOGFX1250: :[[@LINE-4]]:15: error: src_private_limit register not available on this GPU
+// NOSICI: :[[@LINE-5]]:15: error: src_private_limit register not available on this GPU
+// NOVI: :[[@LINE-6]]:15: error: src_private_limit register not available on this GPU
s_add_i32 s0, src_pops_exiting_wave_id, s0
// GFX9: s_add_i32 s0, src_pops_exiting_wave_id, s0 ; encoding: [0xef,0x00,0x00,0x81]
@@ -1447,17 +1449,19 @@ s_and_b64 s[0:1], s[0:1], src_shared_limit
s_and_b64 s[0:1], s[0:1], src_private_base
// GFX11: s_and_b64 s[0:1], s[0:1], src_private_base ; encoding: [0x00,0xed,0x80,0x8b]
-// GFX12XX: s_and_b64 s[0:1], s[0:1], src_private_base ; encoding: [0x00,0xed,0x80,0x8b]
+// GFX12: s_and_b64 s[0:1], s[0:1], src_private_base ; encoding: [0x00,0xed,0x80,0x8b]
// GFX9: s_and_b64 s[0:1], s[0:1], src_private_base ; encoding: [0x00,0xed,0x80,0x86]
-// NOSICI: :[[@LINE-4]]:27: error: src_private_base register not available on this GPU
-// NOVI: :[[@LINE-5]]:27: error: src_private_base register not available on this GPU
+// NOGFX1250: :[[@LINE-4]]:27: error: src_private_base register not available on this GPU
+// NOSICI: :[[@LINE-5]]:27: error: src_private_base register not available on this GPU
+// NOVI: :[[@LINE-6]]:27: error: src_private_base register not available on this GPU
s_and_b64 s[0:1], s[0:1], src_private_limit
// GFX11: s_and_b64 s[0:1], s[0:1], src_private_limit ; encoding: [0x00,0xee,0x80,0x8b]
-// GFX12XX: s_and_b64 s[0:1], s[0:1], src_private_limit ; encoding: [0x00,0xee,0x80,0x8b]
+// GFX12: s_and_b64 s[0:1], s[0:1], src_private_limit ; encoding: [0x00,0xee,0x80,0x8b]
// GFX9: s_and_b64 s[0:1], s[0:1], src_private_limit ; encoding: [0x00,0xee,0x80,0x86]
-// NOSICI: :[[@LINE-4]]:27: error: src_private_limit register not available on this GPU
-// NOVI: :[[@LINE-5]]:27: error: src_private_limit register not available on this GPU
+// NOGFX1250: :[[@LINE-4]]:27: error: src_private_limit register not available on this GPU
+// NOSICI: :[[@LINE-5]]:27: error: src_private_limit register not available on this GPU
+// NOVI: :[[@LINE-6]]:27: error: src_private_limit register not available on this GPU
s_and_b64 s[0:1], s[0:1], src_pops_exiting_wave_id
// GFX9: s_and_b64 s[0:1], s[0:1], src_pops_exiting_wave_id ; encoding: [0x00,0xef,0x80,0x86]
@@ -1679,11 +1683,12 @@ v_ceil_f32_sdwa v5, |src_shared_base| dst_sel:DWORD src0_sel:DWORD
v_add_u32 v0, private_base, s0
// GFX11: v_add_nc_u32_e64 v0, src_private_base, s0 ; encoding: [0x00,0x00,0x25,0xd5,0xed,0x00,0x00,0x02]
-// GFX12XX: v_add_nc_u32_e64 v0, src_private_base, s0 ; encoding: [0x00,0x00,0x25,0xd5,0xed,0x00,0x00,0x02]
+// GFX12: v_add_nc_u32_e64 v0, src_private_base, s0 ; encoding: [0x00,0x00,0x25,0xd5,0xed,0x00,0x00,0x02]
// NOCI: :[[@LINE-3]]:1: error: instruction not supported on this GPU (gfx704): v_add_u32
-// NOGFX9: :[[@LINE-4]]:29: error: invalid operand (violates constant bus restrictions)
-// NOSI: :[[@LINE-5]]:1: error: instruction not supported on this GPU (gfx600): v_add_u32
-// NOVI: :[[@LINE-6]]:15: error: src_private_base register not available on this GPU
+// NOGFX1250: :[[@LINE-4]]:15: error: src_private_base register not available on this GPU
+// NOGFX9: :[[@LINE-5]]:29: error: invalid operand (violates constant bus restrictions)
+// NOSI: :[[@LINE-6]]:1: error: instruction not supported on this GPU (gfx600): v_add_u32
+// NOVI: :[[@LINE-7]]:15: error: src_private_base register not available on this GPU
// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU
v_add_u32 v0, scc, s0
@@ -1714,10 +1719,11 @@ v_div_fmas_f32 v0, v0, shared_limit, v1
// v_div_fmas implicitly reads VCC
v_div_fmas_f32 v0, v0, v1, private_limit
// GFX11: v_div_fmas_f32 v0, v0, v1, src_private_limit ; encoding: [0x00,0x00,0x37,0xd6,0x00,0x03,0xba,0x03]
-// GFX12XX: v_div_fmas_f32 v0, v0, v1, src_private_limit ; encoding: [0x00,0x00,0x37,0xd6,0x00,0x03,0xba,0x03]
-// NOGFX9: :[[@LINE-3]]:28: error: invalid operand (violates constant bus restrictions)
-// NOSICI: :[[@LINE-4]]:28: error: src_private_limit register not available on this GPU
-// NOVI: :[[@LINE-5]]:28: error: src_private_limit register not available on this GPU
+// GFX12: v_div_fmas_f32 v0, v0, v1, src_private_limit ; encoding: [0x00,0x00,0x37,0xd6,0x00,0x03,0xba,0x03]
+// NOGFX1250: :[[@LINE-3]]:28: error: src_private_limit register not available on this GPU
+// NOGFX9: :[[@LINE-4]]:28: error: invalid operand (violates constant bus restrictions)
+// NOSICI: :[[@LINE-5]]:28: error: src_private_limit register not available on this GPU
+// NOVI: :[[@LINE-6]]:28: error: src_private_limit register not available on this GPU
// v_div_fmas implicitly reads VCC
v_div_fmas_f32 v0, execz, v0, v1
@@ -1835,7 +1841,7 @@ v_madmk_f16 v0, 0xff32, 1, v0
v_cmp_eq_f32 s[0:1], private_base, private_limit
// NOGFX11: :[[@LINE-1]]:14: error: invalid operand for instruction
// NOGFX12: :[[@LINE-2]]:14: error: invalid operand for instruction
-// NOGFX1250: :[[@LINE-3]]:14: error: invalid operand for instruction
+// NOGFX1250: :[[@LINE-3]]:22: error: src_private_base register not available on this GPU
// NOGFX9: :[[@LINE-4]]:36: error: invalid operand (violates constant bus restrictions)
// NOSICI: :[[@LINE-5]]:22: error: src_private_base register not available on this GPU
// NOVI: :[[@LINE-6]]:22: error: src_private_base register not available on this GPU
@@ -1843,7 +1849,7 @@ v_cmp_eq_f32 s[0:1], private_base, private_limit
v_cmp_eq_f32 s[0:1], private_base, s0
// NOGFX11: :[[@LINE-1]]:14: error: invalid operand for instruction
// NOGFX12: :[[@LINE-2]]:14: error: invalid operand for instruction
-// NOGFX1250: :[[@LINE-3]]:14: error: invalid operand for instruction
+// NOGFX1250: :[[@LINE-3]]:22: error: src_private_base register not available on this GPU
// NOGFX9: :[[@LINE-4]]:36: error: invalid operand (violates constant bus restrictions)
// NOSICI: :[[@LINE-5]]:22: error: src_private_base register not available on this GPU
// NOVI: :[[@LINE-6]]:22: error: src_private_base register not available on this GPU
@@ -1857,11 +1863,12 @@ v_cmp_eq_f32 s[0:1], execz, s0
v_pk_add_f16 v255, private_base, private_limit
// GFX11: v_pk_add_f16 v255, src_private_base, src_private_limit ; encoding: [0xff,0x40,0x0f,0xcc,0xed,0xdc,0x01,0x1a]
-// GFX12XX: v_pk_add_f16 v255, src_private_base, src_private_limit ; encoding: [0xff,0x40,0x0f,0xcc,0xed,0xdc,0x01,0x1a]
+// GFX12: v_pk_add_f16 v255, src_private_base, src_private_limit ; encoding: [0xff,0x40,0x0f,0xcc,0xed,0xdc,0x01,0x1a]
// NOCI: :[[@LINE-3]]:1: error: instruction not supported on this GPU (gfx704): v_pk_add_f16
-// NOGFX9: :[[@LINE-4]]:34: error: invalid operand (violates constant bus restrictions)
-// NOSI: :[[@LINE-5]]:1: error: instruction not supported on this GPU (gfx600): v_pk_add_f16
-// NOVI: :[[@LINE-6]]:1: error: instruction not supported on this GPU (gfx802): v_pk_add_f16
+// NOGFX1250: :[[@LINE-4]]:20: error: src_private_base register not available on this GPU
+// NOGFX9: :[[@LINE-5]]:34: error: invalid operand (violates constant bus restrictions)
+// NOSI: :[[@LINE-6]]:1: error: instruction not supported on this GPU (gfx600): v_pk_add_f16
+// NOVI: :[[@LINE-7]]:1: error: instruction not supported on this GPU (gfx802): v_pk_add_f16
// NOSICIVI: :[[@LINE-1]]:1: error: instruction not supported on this GPU
v_pk_add_f16 v255, vccz, execz
diff --git a/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt b/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
index 6855d2e687951..5b8d61764ac10 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
@@ -21,6 +21,36 @@
# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
0xff,0x4e,0x80,0xbe,0xbe,0x00,0x00,0x00
+# src_private_base (237) and src_private_limit (238) are reserved on targets
+# with globally addressable scratch. Both the 32-bit and the 64-bit operand
+# forms are covered here.
+# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
+0xed,0x0e,0x80,0xbe
+
+# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
+0xed,0x01,0xfe,0xbe
+
+# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
+0xee,0x0e,0x80,0xbe
+
+# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
+0xee,0x01,0xfe,0xbe
+
+# src_pops_exiting_wave_id (239) is only available on targets that support
+# POPS.
+# GFX12-ERR: [[@LINE+2]]:1: warning: invalid instruction encoding
+# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
+0x00,0xef,0x0c,0xbf
+
+# src_vccz (251) and src_execz (252) are reserved on GFX11+.
+# GFX12-ERR: [[@LINE+2]]:1: warning: invalid instruction encoding
+# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
+0xfb,0x0e,0x80,0xbe
+
+# GFX12-ERR: [[@LINE+2]]:1: warning: invalid instruction encoding
+# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
+0xfc,0x0e,0x80,0xbe
+
# W32: v_dual_add_f32 v5, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, v3, v1, 0xaf123456 ; encoding: [0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf]
# W64: [[@LINE+1]]:1: warning: invalid instruction encoding
0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf
More information about the llvm-commits
mailing list