[llvm] [CodeGen] Don't inflate the register pressure set limit by live-thru pressure (PR #214957)
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Sat Aug 8 04:26:02 PDT 2026
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<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
@llvm/pr-subscribers-llvm-regalloc
Author: Nazar Mokrynskyi (nazar-pc)
<details>
<summary>Changes</summary>
I was originally looking into https://github.com/llvm/llvm-project/issues/212375 with LLM's help. Along the way I ran into what looks like a straightforward bug in how the machine scheduler decides whether a region is over its register budget, and that is what this PR fixes.
I'm not an LLVM developer, but I cross-checked and believe this is a legitimate issue worth fixing.
<details>
<summary>LLM-generated description and additional details</summary>
## The problem
Before the register allocator runs, the machine scheduler reorders instructions. To avoid reordering into something the allocator cannot handle, it tracks *register pressure* — how many values are live at once — and compares it against a limit, which is essentially "how many registers of this kind does this CPU actually have".
Some values are live across the *entire* region being scheduled — for example loop-invariant constants that are computed before the loop and used on every iteration. LLVM calls this **live-thru** pressure and describes it in `initLiveThru()` as pressure the tracker "can never drop below".
Both places that compute excess pressure were *adding* live-thru pressure to the limit:
```c++
unsigned Limit = RCI->getRegPressureSetLimit(PSetID);
if (!LiveThruPressure.empty())
Limit += LiveThruPressure[PSetID];
```
That is backwards. Live-thru values sit in real registers just like anything else, and they are already included in the pressure counters (`CurrSetPressure`, `MaxSetPressure`) that get compared against this limit. Adding them to the limit as well hides exactly that much genuine excess pressure, so the scheduler's "am I over budget?" check goes quiet precisely in the regions that are most starved of registers.
`ScheduleDAGMILive::initRegPressure()` already compares against the *unadjusted* limit when it builds `RegionCriticalPSets`, so the two computations also disagreed with each other.
## Concrete example
For the inner loop of the BLAKE3 AVX-512 kernel at `-mcpu=znver4`, `llc -debug-only=machine-scheduler` reports:
```
Live Thru: FR16X=7 ... GR16=41
FR16X Limit 32 Actual 40
GR16 Limit 30 Actual 44
```
(`FR16X` is the pressure set covering the `xmm`/`ymm`/`zmm` register file — pressure sets are named after a representative register class, so the name is misleading; `GR16` likewise covers the general-purpose registers.)
So with the old code the scheduler's effective budgets were:
* vector: `32 + 7 = 39`, on a machine with **32** `zmm` registers
* general purpose: `30 + 41 = 71`, on a machine with **30** units of GPR
The GPR case is the clearest: measured pressure was 44 against a real limit of 30, and the scheduler was told the budget was 71, so it saw no problem at all.
## Effect on generated code
Reduced BLAKE3 AVX-512 kernel from #<!-- -->212375, `-mcpu=znver4`:
| | before | after |
| --- | --- | --- |
| `zmm` spill stores | 20 | **16** |
| `zmm` reloads | 24 | **18** |
| stack frame | 1224 B | **968 B** |
On BLAKE3's actual `blake3_avx512.c` at `-mcpu=znver4`, spill/reload references drop by 28.
Compiling every test in `llvm/test/CodeGen/X86` with `llc -O3` and counting spill/reload instructions:
| configuration | files | spill/reloads before → after | files better | files worse |
| --- | --- | --- | --- | --- |
| default arch | 4465 | 137846 → 137824 | 5 | 1 |
| `-mcpu=znver4` | 4759 | 33812 → 33808 | 1 | 0 |
Small, but net negative in both, and no configuration I measured came out worse in aggregate.
Caveat on the `-mcpu=znver4` row: fewer files move than in the default-arch row because most X86 tests pin their own `-mtriple`/`-mattr` or carry `target-features` function attributes that override `-mcpu`, so the forced CPU only reaches the subset that does not.
## Other targets
This file is generic `llvm/lib/CodeGen` code, not X86-specific. The two functions changed are used by `MachineScheduler` (every backend) and by `MachinePipeliner` (the software pipeliner), so X86-only testing would not have been enough.
I built with `LLVM_TARGETS_TO_BUILD=all` plus `llvm-test-depends`, and ran the **entire `llvm/test` suite (64,849 tests)** twice — once with the patch and once with only `RegisterPressure.cpp` reverted to its pre-patch state, everything else identical:
* **with the patch: 0 failures**
* without the patch: 14 failures — precisely the 14 tests whose check lines this PR regenerates, and nothing else
So no test fails as a result of this change, on any target, and exactly 14 tests move. **9 on X86 and 5 elsewhere:**
| test | spill/reloads | instructions | |
| --- | --- | --- | --- |
| PowerPC/more-dq-form-prepare.ll | 117 → 110 | 291 → 282 | better (frame 592 → 576) |
| PowerPC/common-chain.ll | 68 → 65 | 417 → 415 | better |
| RISCV/rvv/pr165232.ll | 16 → 15 | 164 → 163 | better |
| AArch64/ragreedy-local-interval-cost.ll | 22 → 22 | 151 → 155 | worse |
| Thumb2/LowOverheadLoops/spillingmove.ll | 8 → 16 | 158 → 167 | **worse** |
Net across those five: −3 spill/reloads, +1 instruction.
**AMDGPU is completely unaffected** — 0 of 4964 tests changed. That is the result I was most worried about, since AMDGPU is the only target that overrides `getRegPressureSetLimit()` (occupancy-dependent) and forces `ShouldTrackPressure = true`, and register usage there controls occupancy rather than just spill counts.
The Thumb2 MVE case is a genuine regression and I want to flag it rather than bury it: vector spills double, 8 → 16. The low-overhead loop structure survives (`dls`/`le`/`letp` counts are unchanged), so nothing functional is lost, but that test is specifically about spilling in MVE loops. It is the same phenomenon described below — once the scheduler can see the real excess pressure it starts reordering, and the greedy heuristic reacting to that information sometimes makes things worse. I do not think that argues for keeping a wrong limit, but a reviewer may disagree.
Backends beyond those five are unaffected. That includes the `MachinePipeliner` users (Hexagon, SystemZ), which call the same code and which I expected to move — they did not.
## Test changes
All 14 affected tests are autogenerated; their check lines were regenerated with `update_llc_test_checks.py` / `update_mir_test_checks.py`. No hand-written test asserting a specific optimisation had to be touched.
The diffs look large because those scripts rewrite whole function bodies, but the content barely moves. On X86, summed over all 25 `llc` RUN lines in the affected tests, the change is **−7 spill/reloads and −2 instructions**, with no single RUN line moving by more than 4 spills or 4 instructions. 8 of the 9 affected X86 RUN lines are 32-bit `i686`, which is what you would expect: with only ~6 allocatable general-purpose registers, the inflated limit was masking the most excess there.
</details>
---
Patch is 119.71 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/214957.diff
15 Files Affected:
- (modified) llvm/lib/CodeGen/RegisterPressure.cpp (+3-10)
- (modified) llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll (+59-55)
- (modified) llvm/test/CodeGen/PowerPC/common-chain.ll (+106-108)
- (modified) llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll (+215-224)
- (modified) llvm/test/CodeGen/RISCV/rvv/pr165232.ll (+41-42)
- (modified) llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.ll (+31-22)
- (modified) llvm/test/CodeGen/X86/AMX/amx-greedy-ra-spill-shape.ll (+71-60)
- (modified) llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll (+11-11)
- (modified) llvm/test/CodeGen/X86/i128-mul.ll (+45-50)
- (modified) llvm/test/CodeGen/X86/i128-udiv.ll (+83-82)
- (modified) llvm/test/CodeGen/X86/mmx-arith.ll (+5-4)
- (modified) llvm/test/CodeGen/X86/pr38539.ll (+4-3)
- (modified) llvm/test/CodeGen/X86/sdiv_fix.ll (+25-23)
- (modified) llvm/test/CodeGen/X86/sdiv_fix_sat.ll (+50-48)
- (modified) llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll (+47-51)
``````````diff
diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp
index dd7468a1309de..b00cf0b14b9c8 100644
--- a/llvm/lib/CodeGen/RegisterPressure.cpp
+++ b/llvm/lib/CodeGen/RegisterPressure.cpp
@@ -948,8 +948,7 @@ void RegPressureTracker::advance() {
static void computeExcessPressureDelta(ArrayRef<unsigned> OldPressureVec,
ArrayRef<unsigned> NewPressureVec,
RegPressureDelta &Delta,
- const RegisterClassInfo *RCI,
- ArrayRef<unsigned> LiveThruPressureVec) {
+ const RegisterClassInfo *RCI) {
Delta.Excess = PressureChange();
for (unsigned i = 0, e = OldPressureVec.size(); i < e; ++i) {
unsigned POld = OldPressureVec[i];
@@ -959,8 +958,6 @@ static void computeExcessPressureDelta(ArrayRef<unsigned> OldPressureVec,
continue;
// Only consider change beyond the limit.
unsigned Limit = RCI->getRegPressureSetLimit(i);
- if (!LiveThruPressureVec.empty())
- Limit += LiveThruPressureVec[i];
if (Limit > POld) {
if (Limit > PNew)
@@ -1093,8 +1090,7 @@ getMaxUpwardPressureDelta(const MachineInstr *MI, PressureDiff *PDiff,
bumpUpwardPressure(MI);
- computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI,
- LiveThruPressure);
+ computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI);
computeMaxPressureDelta(SavedMaxPressure, P.MaxSetPressure, CriticalPSets,
MaxPressureLimit, Delta);
assert(Delta.CriticalMax.getUnitInc() >= 0 &&
@@ -1160,8 +1156,6 @@ getUpwardPressureDelta(const MachineInstr *MI, /*const*/ PressureDiff &PDiff,
unsigned PSetID = PDiffI->getPSet();
unsigned Limit = RCI->getRegPressureSetLimit(PSetID);
- if (!LiveThruPressure.empty())
- Limit += LiveThruPressure[PSetID];
unsigned POld = CurrSetPressure[PSetID];
unsigned MOld = P.MaxSetPressure[PSetID];
@@ -1342,8 +1336,7 @@ getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta,
bumpDownwardPressure(MI);
- computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI,
- LiveThruPressure);
+ computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI);
computeMaxPressureDelta(SavedMaxPressure, P.MaxSetPressure, CriticalPSets,
MaxPressureLimit, Delta);
assert(Delta.CriticalMax.getUnitInc() >= 0 &&
diff --git a/llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll b/llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
index 9f513a940015e..8ee47f36bdf5c 100644
--- a/llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
+++ b/llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
@@ -25,7 +25,7 @@ define dso_local void @run_test() local_unnamed_addr uwtable {
; CHECK-NEXT: .cfi_offset b13, -64
; CHECK-NEXT: .cfi_offset b14, -72
; CHECK-NEXT: .cfi_offset b15, -80
-; CHECK-NEXT: movi v7.2d, #0000000000000000
+; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: adrp x14, B+48
; CHECK-NEXT: add x14, x14, :lo12:B+48
; CHECK-NEXT: // implicit-def: $q18
@@ -43,15 +43,15 @@ define dso_local void @run_test() local_unnamed_addr uwtable {
; CHECK-NEXT: // implicit-def: $q3
; CHECK-NEXT: // implicit-def: $q4
; CHECK-NEXT: // implicit-def: $q5
-; CHECK-NEXT: // implicit-def: $q1
+; CHECK-NEXT: // implicit-def: $q6
; CHECK-NEXT: // implicit-def: $q16
; CHECK-NEXT: // implicit-def: $q17
-; CHECK-NEXT: // implicit-def: $q6
+; CHECK-NEXT: // implicit-def: $q7
; CHECK-NEXT: // implicit-def: $q19
; CHECK-NEXT: // implicit-def: $q20
; CHECK-NEXT: // implicit-def: $q21
; CHECK-NEXT: // implicit-def: $q22
-; CHECK-NEXT: // implicit-def: $q12
+; CHECK-NEXT: // implicit-def: $q24
; CHECK-NEXT: // implicit-def: $q23
; CHECK-NEXT: // implicit-def: $q25
; CHECK-NEXT: // implicit-def: $q26
@@ -59,7 +59,7 @@ define dso_local void @run_test() local_unnamed_addr uwtable {
; CHECK-NEXT: // implicit-def: $q30
; CHECK-NEXT: // implicit-def: $q8
; CHECK-NEXT: // implicit-def: $q11
-; CHECK-NEXT: // implicit-def: $q28
+; CHECK-NEXT: // implicit-def: $q12
; CHECK-NEXT: // implicit-def: $q29
; CHECK-NEXT: // implicit-def: $q13
; CHECK-NEXT: // implicit-def: $q10
@@ -76,100 +76,104 @@ define dso_local void @run_test() local_unnamed_addr uwtable {
; CHECK-NEXT: stp q15, q4, [sp] // 32-byte Folded Spill
; CHECK-NEXT: add x5, x10, x11
; CHECK-NEXT: mul x1, x18, x15
-; CHECK-NEXT: ldr x2, [x13], #64
-; CHECK-NEXT: stp q6, q23, [sp, #32] // 32-byte Folded Spill
-; CHECK-NEXT: ldr q23, [sp, #80] // 16-byte Reload
; CHECK-NEXT: ldr x14, [x14, #8]
-; CHECK-NEXT: mul x0, x18, x18
; CHECK-NEXT: ldr x5, [x5, #128]
+; CHECK-NEXT: ldr x2, [x13], #64
+; CHECK-NEXT: stp q7, q23, [sp, #32] // 32-byte Folded Spill
+; CHECK-NEXT: mul x0, x18, x18
+; CHECK-NEXT: ldr q23, [sp, #80] // 16-byte Reload
; CHECK-NEXT: mov v9.16b, v30.16b
; CHECK-NEXT: mov v30.16b, v25.16b
; CHECK-NEXT: mov v25.16b, v20.16b
-; CHECK-NEXT: mov v20.16b, v1.16b
+; CHECK-NEXT: mov v20.16b, v6.16b
; CHECK-NEXT: mul x17, x16, x18
+; CHECK-NEXT: mov v6.16b, v1.16b
+; CHECK-NEXT: mov v28.16b, v24.16b
+; CHECK-NEXT: fmov d14, x1
+; CHECK-NEXT: mov v24.16b, v19.16b
+; CHECK-NEXT: mov v19.16b, v5.16b
+; CHECK-NEXT: mul x3, x14, x18
; CHECK-NEXT: mov v31.16b, v26.16b
; CHECK-NEXT: mov v26.16b, v21.16b
-; CHECK-NEXT: fmov d14, x1
+; CHECK-NEXT: fmov d15, x0
; CHECK-NEXT: mov v21.16b, v16.16b
; CHECK-NEXT: mov v16.16b, v2.16b
+; CHECK-NEXT: mov v0.16b, v14.16b
; CHECK-NEXT: mul x4, x2, x18
-; CHECK-NEXT: mov v6.16b, v10.16b
+; CHECK-NEXT: mov v7.16b, v10.16b
; CHECK-NEXT: mov v10.16b, v17.16b
-; CHECK-NEXT: fmov d15, x0
; CHECK-NEXT: mov v17.16b, v3.16b
-; CHECK-NEXT: mov v24.16b, v19.16b
-; CHECK-NEXT: mov v0.16b, v14.16b
-; CHECK-NEXT: mul x3, x14, x18
-; CHECK-NEXT: mov v19.16b, v5.16b
; CHECK-NEXT: add x11, x11, #8
-; CHECK-NEXT: add x12, x12, #1
; CHECK-NEXT: mov v15.d[1], x17
-; CHECK-NEXT: mul x6, x15, x15
+; CHECK-NEXT: mul x7, x15, x5
; CHECK-NEXT: cmp x11, #64
; CHECK-NEXT: mov v0.d[1], x1
+; CHECK-NEXT: add x12, x12, #1
+; CHECK-NEXT: mul x19, x16, x5
; CHECK-NEXT: fmov d1, x4
-; CHECK-NEXT: mul x7, x15, x5
; CHECK-NEXT: mul x18, x18, x5
-; CHECK-NEXT: mov v1.d[1], x3
; CHECK-NEXT: add v23.2d, v23.2d, v0.2d
; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Reload
-; CHECK-NEXT: fmov d4, x6
-; CHECK-NEXT: mul x20, x2, x5
-; CHECK-NEXT: add v0.2d, v0.2d, v15.2d
; CHECK-NEXT: fmov d3, x7
-; CHECK-NEXT: mul x19, x16, x5
-; CHECK-NEXT: mov v4.d[1], x6
+; CHECK-NEXT: mul x20, x14, x5
+; CHECK-NEXT: mov v1.d[1], x3
+; CHECK-NEXT: add v0.2d, v0.2d, v15.2d
+; CHECK-NEXT: mul x5, x2, x5
+; CHECK-NEXT: mov v3.d[1], x7
; CHECK-NEXT: fmov d2, x18
-; CHECK-NEXT: mul x0, x14, x5
+; CHECK-NEXT: mul x6, x15, x15
; CHECK-NEXT: stp q0, q23, [sp, #64] // 32-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #96] // 16-byte Reload
-; CHECK-NEXT: fmov d5, x20
-; CHECK-NEXT: mov v3.d[1], x7
; CHECK-NEXT: ldr q23, [sp, #48] // 16-byte Reload
; CHECK-NEXT: mul x17, x2, x15
; CHECK-NEXT: add v0.2d, v0.2d, v15.2d
; CHECK-NEXT: ldr q15, [sp] // 16-byte Reload
+; CHECK-NEXT: fmov d5, x5
; CHECK-NEXT: mov v2.d[1], x19
-; CHECK-NEXT: add v13.2d, v13.2d, v4.2d
-; CHECK-NEXT: add v12.2d, v12.2d, v4.2d
+; CHECK-NEXT: add v11.2d, v11.2d, v3.2d
; CHECK-NEXT: mul x16, x16, x15
; CHECK-NEXT: add v15.2d, v15.2d, v1.2d
-; CHECK-NEXT: mov v1.16b, v20.16b
-; CHECK-NEXT: mov v5.d[1], x0
+; CHECK-NEXT: mov v1.16b, v6.16b
+; CHECK-NEXT: fmov d4, x6
; CHECK-NEXT: str q0, [sp, #96] // 16-byte Spill
-; CHECK-NEXT: mov v20.16b, v25.16b
+; CHECK-NEXT: mov v6.16b, v20.16b
+; CHECK-NEXT: mov v5.d[1], x20
; CHECK-NEXT: mul x14, x14, x15
-; CHECK-NEXT: mov v25.16b, v30.16b
-; CHECK-NEXT: add v11.2d, v11.2d, v3.2d
+; CHECK-NEXT: mov v20.16b, v25.16b
; CHECK-NEXT: fmov d0, x17
+; CHECK-NEXT: mov v25.16b, v30.16b
; CHECK-NEXT: mov v3.16b, v17.16b
+; CHECK-NEXT: mov v4.d[1], x6
; CHECK-NEXT: mov v17.16b, v10.16b
-; CHECK-NEXT: mov v10.16b, v6.16b
+; CHECK-NEXT: mov v10.16b, v7.16b
+; CHECK-NEXT: mov v14.d[1], x16
; CHECK-NEXT: add v8.2d, v8.2d, v2.2d
; CHECK-NEXT: mov v2.16b, v16.16b
-; CHECK-NEXT: mov v14.d[1], x16
-; CHECK-NEXT: mov v16.16b, v21.16b
-; CHECK-NEXT: mov v21.16b, v26.16b
; CHECK-NEXT: add v30.2d, v9.2d, v5.2d
; CHECK-NEXT: mov v5.16b, v19.16b
-; CHECK-NEXT: add v26.2d, v31.2d, v4.2d
+; CHECK-NEXT: mov v19.16b, v24.16b
; CHECK-NEXT: mov v0.d[1], x14
-; CHECK-NEXT: add v19.2d, v24.2d, v4.2d
+; CHECK-NEXT: mov v16.16b, v21.16b
+; CHECK-NEXT: mov v21.16b, v26.16b
+; CHECK-NEXT: add v13.2d, v13.2d, v4.2d
+; CHECK-NEXT: add v26.2d, v31.2d, v4.2d
+; CHECK-NEXT: add v24.2d, v28.2d, v4.2d
+; CHECK-NEXT: add v19.2d, v19.2d, v4.2d
+; CHECK-NEXT: add v6.2d, v6.2d, v4.2d
; CHECK-NEXT: add v1.2d, v1.2d, v4.2d
-; CHECK-NEXT: add v7.2d, v7.2d, v4.2d
-; CHECK-NEXT: ldp q4, q6, [sp, #16] // 32-byte Folded Reload
+; CHECK-NEXT: ldp q4, q7, [sp, #16] // 32-byte Folded Reload
; CHECK-NEXT: add v10.2d, v10.2d, v14.2d
; CHECK-NEXT: add v29.2d, v29.2d, v14.2d
; CHECK-NEXT: add v27.2d, v27.2d, v14.2d
; CHECK-NEXT: add v23.2d, v23.2d, v14.2d
; CHECK-NEXT: add v22.2d, v22.2d, v14.2d
; CHECK-NEXT: add v20.2d, v20.2d, v14.2d
-; CHECK-NEXT: add v6.2d, v6.2d, v14.2d
; CHECK-NEXT: add v16.2d, v16.2d, v14.2d
+; CHECK-NEXT: add v7.2d, v7.2d, v14.2d
; CHECK-NEXT: add v5.2d, v5.2d, v14.2d
; CHECK-NEXT: add v3.2d, v3.2d, v14.2d
; CHECK-NEXT: add v2.2d, v2.2d, v14.2d
-; CHECK-NEXT: add v28.2d, v28.2d, v0.2d
+; CHECK-NEXT: add v12.2d, v12.2d, v0.2d
; CHECK-NEXT: add v25.2d, v25.2d, v0.2d
; CHECK-NEXT: add v21.2d, v21.2d, v0.2d
; CHECK-NEXT: add v17.2d, v17.2d, v0.2d
@@ -178,30 +182,30 @@ define dso_local void @run_test() local_unnamed_addr uwtable {
; CHECK-NEXT: mov x14, x13
; CHECK-NEXT: b.ne .LBB0_1
; CHECK-NEXT: // %bb.2: // %for.cond.cleanup
-; CHECK-NEXT: ldp q24, q18, [sp, #64] // 32-byte Folded Reload
+; CHECK-NEXT: ldp q28, q18, [sp, #64] // 32-byte Folded Reload
; CHECK-NEXT: adrp x8, C
; CHECK-NEXT: add x8, x8, :lo12:C
; CHECK-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload
; CHECK-NEXT: stp q10, q13, [x8, #64]
-; CHECK-NEXT: stp q24, q18, [x8]
+; CHECK-NEXT: stp q28, q18, [x8]
; CHECK-NEXT: ldr q18, [sp, #96] // 16-byte Reload
-; CHECK-NEXT: stp q29, q28, [x8, #96]
+; CHECK-NEXT: stp q29, q12, [x8, #96]
+; CHECK-NEXT: ldp d13, d12, [sp, #128] // 16-byte Folded Reload
; CHECK-NEXT: stp q18, q15, [x8, #32]
; CHECK-NEXT: ldp d15, d14, [sp, #112] // 16-byte Folded Reload
; CHECK-NEXT: stp q11, q8, [x8, #144]
; CHECK-NEXT: ldp d9, d8, [sp, #160] // 16-byte Folded Reload
-; CHECK-NEXT: stp q12, q22, [x8, #272]
-; CHECK-NEXT: ldp d11, d10, [sp, #144] // 16-byte Folded Reload
-; CHECK-NEXT: ldp d13, d12, [sp, #128] // 16-byte Folded Reload
; CHECK-NEXT: stp q30, q27, [x8, #176]
+; CHECK-NEXT: ldp d11, d10, [sp, #144] // 16-byte Folded Reload
; CHECK-NEXT: str q26, [x8, #208]
; CHECK-NEXT: stp q25, q23, [x8, #240]
+; CHECK-NEXT: stp q24, q22, [x8, #272]
; CHECK-NEXT: stp q21, q20, [x8, #304]
-; CHECK-NEXT: stp q19, q6, [x8, #336]
+; CHECK-NEXT: stp q19, q7, [x8, #336]
; CHECK-NEXT: stp q17, q16, [x8, #368]
-; CHECK-NEXT: stp q1, q5, [x8, #400]
+; CHECK-NEXT: stp q6, q5, [x8, #400]
; CHECK-NEXT: stp q4, q3, [x8, #432]
-; CHECK-NEXT: stp q7, q2, [x8, #464]
+; CHECK-NEXT: stp q1, q2, [x8, #464]
; CHECK-NEXT: str q0, [x8, #496]
; CHECK-NEXT: add sp, sp, #192
; CHECK-NEXT: .cfi_def_cfa_offset 0
diff --git a/llvm/test/CodeGen/PowerPC/common-chain.ll b/llvm/test/CodeGen/PowerPC/common-chain.ll
index 8283e7bac3457..c7c80637a0f87 100644
--- a/llvm/test/CodeGen/PowerPC/common-chain.ll
+++ b/llvm/test/CodeGen/PowerPC/common-chain.ll
@@ -753,176 +753,174 @@ define signext i32 @spill_reduce_succ(ptr %input1, ptr %input2, ptr %output, i64
; CHECK-NEXT: blt cr0, .LBB7_5
; CHECK-NEXT: # %bb.2: # %for.body.preheader.new
; CHECK-NEXT: rldicl r11, r11, 62, 2
-; CHECK-NEXT: sldi r20, r8, 3
-; CHECK-NEXT: mr r14, r7
-; CHECK-NEXT: sldi r7, r7, 3
-; CHECK-NEXT: sldi r21, r9, 3
-; CHECK-NEXT: std r3, -160(r1) # 8-byte Folded Spill
-; CHECK-NEXT: std r9, -208(r1) # 8-byte Folded Spill
-; CHECK-NEXT: std r8, -184(r1) # 8-byte Folded Spill
-; CHECK-NEXT: std r5, -200(r1) # 8-byte Folded Spill
-; CHECK-NEXT: std r4, -168(r1) # 8-byte Folded Spill
-; CHECK-NEXT: std r11, -192(r1) # 8-byte Folded Spill
+; CHECK-NEXT: sldi r31, r8, 3
+; CHECK-NEXT: mr r28, r4
+; CHECK-NEXT: add r14, r10, r7
+; CHECK-NEXT: add r16, r10, r9
+; CHECK-NEXT: add r15, r10, r8
+; CHECK-NEXT: mulli r24, r10, 24
+; CHECK-NEXT: add r25, r24, r31
+; CHECK-NEXT: std r11, -168(r1) # 8-byte Folded Spill
; CHECK-NEXT: sldi r11, r10, 5
-; CHECK-NEXT: add r0, r11, r20
-; CHECK-NEXT: add r12, r11, r21
+; CHECK-NEXT: sldi r2, r9, 3
+; CHECK-NEXT: add r0, r11, r31
+; CHECK-NEXT: add r12, r11, r2
+; CHECK-NEXT: sldi r19, r10, 4
+; CHECK-NEXT: std r3, -160(r1) # 8-byte Folded Spill
+; CHECK-NEXT: add r26, r24, r2
+; CHECK-NEXT: add r21, r19, r2
+; CHECK-NEXT: add r20, r19, r31
+; CHECK-NEXT: std r7, -176(r1) # 8-byte Folded Spill
+; CHECK-NEXT: add r21, r5, r21
+; CHECK-NEXT: add r20, r5, r20
; CHECK-NEXT: add r30, r5, r0
-; CHECK-NEXT: add r0, r11, r7
-; CHECK-NEXT: std r21, -216(r1) # 8-byte Folded Spill
-; CHECK-NEXT: std r20, -224(r1) # 8-byte Folded Spill
-; CHECK-NEXT: add r12, r5, r12
-; CHECK-NEXT: add r29, r5, r0
-; CHECK-NEXT: add r28, r4, r0
-; CHECK-NEXT: add r27, r3, r0
-; CHECK-NEXT: mulli r0, r10, 24
-; CHECK-NEXT: std r14, -176(r1) # 8-byte Folded Spill
-; CHECK-NEXT: add r26, r0, r21
-; CHECK-NEXT: add r25, r0, r20
-; CHECK-NEXT: add r0, r0, r7
-; CHECK-NEXT: add r24, r5, r0
-; CHECK-NEXT: add r23, r4, r0
-; CHECK-NEXT: add r22, r3, r0
-; CHECK-NEXT: sldi r0, r10, 4
+; CHECK-NEXT: sldi r0, r7, 3
+; CHECK-NEXT: add r4, r5, r12
+; CHECK-NEXT: mr r12, r28
; CHECK-NEXT: add r26, r5, r26
+; CHECK-NEXT: std r9, -208(r1) # 8-byte Folded Spill
; CHECK-NEXT: add r25, r5, r25
-; CHECK-NEXT: add r21, r0, r21
-; CHECK-NEXT: add r20, r0, r20
-; CHECK-NEXT: add r0, r0, r7
-; CHECK-NEXT: add r19, r5, r0
-; CHECK-NEXT: add r18, r4, r0
-; CHECK-NEXT: add r17, r3, r0
-; CHECK-NEXT: add r0, r10, r9
-; CHECK-NEXT: add r21, r5, r21
-; CHECK-NEXT: add r20, r5, r20
-; CHECK-NEXT: sldi r0, r0, 3
-; CHECK-NEXT: add r16, r5, r0
-; CHECK-NEXT: add r0, r10, r8
-; CHECK-NEXT: sldi r0, r0, 3
-; CHECK-NEXT: add r15, r5, r0
-; CHECK-NEXT: add r0, r10, r14
-; CHECK-NEXT: sldi r0, r0, 3
-; CHECK-NEXT: add r2, r3, r0
-; CHECK-NEXT: ld r3, -224(r1) # 8-byte Folded Reload
-; CHECK-NEXT: add r14, r5, r0
-; CHECK-NEXT: add r31, r4, r0
-; CHECK-NEXT: sub r0, r3, r7
-; CHECK-NEXT: ld r3, -192(r1) # 8-byte Folded Reload
-; CHECK-NEXT: rldicl r9, r3, 2, 1
-; CHECK-NEXT: ld r3, -216(r1) # 8-byte Folded Reload
-; CHECK-NEXT: addi r8, r9, -4
-; CHECK-NEXT: rldicl r8, r8, 62, 2
-; CHECK-NEXT: sub r7, r3, r7
-; CHECK-NEXT: ori r3, r9, 1
-; CHECK-NEXT: addi r8, r8, 1
+; CHECK-NEXT: add r27, r11, r0
+; CHECK-NEXT: add r22, r24, r0
+; CHECK-NEXT: add r17, r19, r0
+; CHECK-NEXT: sldi r16, r16, 3
+; CHECK-NEXT: add r16, r5, r16
+; CHECK-NEXT: sub r31, r31, r0
+; CHECK-NEXT: sub r2, r2, r0
+; CHECK-NEXT: li r0, 0
+; CHECK-NEXT: add r29, r5, r27
+; CHECK-NEXT: add r28, r28, r27
+; CHECK-NEXT: add r27, r3, r27
+; CHECK-NEXT: add r24, r5, r22
+; CHECK-NEXT: add r23, r12, r22
+; CHECK-NEXT: add r22, r3, r22
+; CHECK-NEXT: add r19, r5, r17
+; CHECK-NEXT: add r18, r12, r17
+; CHECK-NEXT: add r17, r3, r17
+; CHECK-NEXT: ld r3, -168(r1) # 8-byte Folded Reload
+; CHECK-NEXT: std r8, -184(r1) # 8-byte Folded Spill
+; CHECK-NEXT: sldi r15, r15, 3
+; CHECK-NEXT: add r15, r5, r15
+; CHECK-NEXT: sldi r8, r14, 3
+; CHECK-NEXT: add r14, r5, r8
+; CHECK-NEXT: std r5, -192(r1) # 8-byte Folded Spill
+; CHECK-NEXT: rldicl r3, r3, 2, 1
+; CHECK-NEXT: addi r7, r3, -4
+; CHECK-NEXT: ori r3, r3, 1
+; CHECK-NEXT: rldicl r7, r7, 62, 2
; CHECK-NEXT: mulld r3, r10, r3
-; CHECK-NEXT: mtctr r8
-; CHECK-NEXT: li r8, 0
-; CHECK-NEXT: std r10, -192(r1) # 8-byte Folded Spill
+; CHECK-NEXT: addi r7, r7, 1
+; CHECK-NEXT: mtctr r7
+; CHECK-NEXT: std r12, -168(r1) # 8-byte Folded Spill
+; CHECK-NEXT: add r12, r12, r8
+; CHECK-NEXT: std r10, -200(r1) # 8-byte Folded Spill
+; CHECK-NEXT: ld r5, -160(r1) # 8-byte Folded Reload
; CHECK-NEXT: std r3, -216(r1) # 8-byte Folded Spill
+; CHECK-NEXT: add r7, r5, r8
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB7_3: # %for.body
; CHECK-NEXT: #
-; CHECK-NEXT: lfd f0, 0(r2)
-; CHECK-NEXT: lfd f1, 0(r31)
+; CHECK-NEXT: lfd f0, 0(r7)
+; CHECK-NEXT: lfd f1, 0(r12)
; CHECK-NEXT: xsmuldp f0, f0, f1
; CHECK-NEXT: lfd f1, 0(r14)
; CHECK-NEXT: xsadddp f0, f1, f0
; CHECK-NEXT: stfd f0, 0(r14)
; CHECK-NEXT: add r14, r14, r11
-; CHECK-NEXT: lfdx f0, r2, r0
-; CHECK-NEXT: lfdx f1, r31, r0
+; CHECK-NEXT: lfdx f0, r7, r31
+; CHECK-NEXT: lfdx f1, r12, r31
; CHECK-NEXT: xsmuldp f0, f0, f1
-; CHECK-NEXT: lfdx f1, r15, r8
+; CHECK-NEXT: lfdx f1, r15, r0
; CHECK-NEXT: xsadddp f0, f1, f0
-; CHECK-NEXT: stfdx f0, r15, r8
-; CHECK-NEXT: lfdx f0, r2, r7
-; CHECK-NEXT: lfdx f1, r31, r7
-; CHECK-NEXT: add r2, r2, r11
-; CHECK-NEXT: add r31, r31, r11
+; CHECK-NEXT: stfdx f0, r15, r0
+; CHECK-NEXT: lfdx f0, r7, r2
+; CHECK-NEXT: lfdx f1, r12, r2
+; CHECK-NEXT: add r7, r7, r11
+; CHECK-NEXT: add r12, r12, r11
; CHECK-NEXT: xsmuldp f0, f0, f1
-; CHECK-NEXT: lfdx f1, r16, r8
+; CHECK-NEXT: lfdx f1, r16, r0
; CHECK-NEXT: xsadddp f0, f1, f0
-; CHECK-NEXT: stfdx f0, r16, r8
+; CHECK-NEXT: stfdx f0, r16, r0
; CHECK-NEXT: lfd f0, 0(r17)
; CHECK-NEXT: lfd f1, 0(r18)
; CHECK-NEXT: xsmuldp f0, f0, f1
-; CHECK-NEXT: lfdx f1, r19, r8
+; CHECK-NEXT: lfdx f1, r19, r0
; CHECK-NEXT: xsadddp f0, f1, f0
-; CHECK-NEXT: stfdx f0, r19, r8
-; CHECK-NEXT: lfdx f0, r17, r0
-; CHECK-NEXT: lfdx f1, r18, r0
+; CHECK-NEXT: stfdx f0, r19, r0
+; CHECK-NEXT: lfdx f0, r17, r31
+; CHECK-NEXT: lfdx f1, r18, r31
; CHECK-NEXT: xsmuldp f0, f0, f1
-; CHECK-NEXT: lfdx f1, r20, r8
+; CHECK-NEXT: lfdx f1, r20, r0
; CHECK-NEXT: xsadddp f0, f1, f0
-; CHECK-NEXT: stfdx f0, r20, r8
-; CHECK-NEXT: lfdx f0, r17, r7
-; CHECK-NEXT: lfdx f1, r18, r7
+; CHECK-NEXT: stfdx f0, r20, r0
+; CHECK-NEXT: lfdx f0, r17, r2
+; CHECK-NEXT: lfdx f1, r18, r2
; CHECK-NEXT: add r17, r17, r11
; CHECK-NEXT: add r18, r18, r11
; CHECK-NEXT: xsmuldp f0, f0, f1
-; CHECK-NEXT: lfdx f1, r21, r8
+; CHECK-NEXT: lfdx f1, r21, r0
; CHECK-NEXT: xsadddp f0, f1, f0
-; CHECK-NEXT: stfdx f0, r21, r8
+; CHECK-NEXT: stfdx f0, r21, r0
; CHECK-NEXT: lfd f0, 0(r22)
; CHECK-NEXT: lfd f1, 0(r23)
; CHECK-NEXT: xsmuldp f0, f0, f1
-; CHECK-NEXT: lfdx f1, r24, r8
+; CHECK-NEXT: lfdx f1, r24, r0
; CHECK-NEXT: xsadddp f0, f1, f0
-; CHECK-NEXT: stfdx f0, r24, r8
-; CHECK-NEXT: lfdx f0, r22, r0
-; CHECK-NEXT: lfdx f1, r23, r0
+; CHECK-NEXT: stfdx f0, r24, r0
+; CHECK-NEXT: lfdx f0, r22, r31
+; CHECK-NEXT: lfdx f1, r23, r31
; CHECK-NEXT: xsmuldp f0, f0, f1
-; CHECK-NEXT: lfdx f1, r25, r8
+; CHECK-NEXT: lfdx f1, r25, r0
; CHECK-NEXT: xsadddp f0, f1, f0
-; CHECK-NEXT: stfdx f0, r25, r8
-; CHECK-NEXT: lfdx f0, r22, r7
-; CHE...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/214957
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