[llvm] [DAGCombiner] Fold extract of signbit + srl to srl. (PR #214913)

[Craig Topper via llvm-commits]

================

----------------
topperc wrote:

This should use DAG.getShiftAmountConstant. The expected VT for a shift amount operand does not always match the result VT. For example, X86 prefers i8 shift amounts.

https://github.com/llvm/llvm-project/pull/214913