[llvm] [X86] Optimize (a & 0xff) | ((b & 0xff) << 8) into high-byte register insertions (PR #214645)

[via llvm-commits]

AZero13 wrote:

> We try to not use high-byte registers in codegen on 64-bit. One is APX doesn't support it. Another is there are penalties on recent targets, see #210321

TableGen couldn't express the conditional MOVZX32rr8 barrier we needed just for 64-bit mode (to prevent the register coalescer from assigning %esi and crashing when trying to emit movb %cl, %sh).

https://github.com/llvm/llvm-project/pull/214645