[llvm] 1613ee7 - [AMDGPU][GISel] RegBankLegalize rules for QSAD intrinsics (#214328)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 7 09:14:47 PDT 2026
Author: Chinmay Deshpande
Date: 2026-08-07T09:14:42-07:00
New Revision: 1613ee7645120b6ad8efa66c7631346836115a46
URL: https://github.com/llvm/llvm-project/commit/1613ee7645120b6ad8efa66c7631346836115a46
DIFF: https://github.com/llvm/llvm-project/commit/1613ee7645120b6ad8efa66c7631346836115a46.diff
LOG: [AMDGPU][GISel] RegBankLegalize rules for QSAD intrinsics (#214328)
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 0141902cf4f89..197b0ef5f6b7e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1963,6 +1963,15 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}})
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}});
+ addRulesForIOpcs({amdgcn_mqsad_pk_u16_u8, amdgcn_qsad_pk_u16_u8}, Standard)
+ .Uni(S64, {{UniInVgprS64}, {IntrId, Vgpr64, Vgpr32, Vgpr64}})
+ .Div(S64, {{Vgpr64}, {IntrId, Vgpr64, Vgpr32, Vgpr64}});
+
+ addRulesForIOpcs({amdgcn_mqsad_u32_u8})
+ .Any(
+ {{UniV4S32}, {{UniInVgprV4S32}, {IntrId, Vgpr64, Vgpr32, VgprV4S32}}})
+ .Any({{DivV4S32}, {{VgprV4S32}, {IntrId, Vgpr64, Vgpr32, VgprV4S32}}});
+
addRulesForIOpcs({amdgcn_lerp}, Standard)
.Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}})
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}});
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
index 374eb2d1043d6..ffc2e2d0bcb91 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
@@ -1,18 +1,105 @@
-; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GCN,GFX600 %s
-; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GCN,GFX803 %s
-; RUN: llc -mtriple=amdgpu13.10 < %s | FileCheck -check-prefixes=GCN,GFX13 %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=SI,SI-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=SI,SI-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=VI,VI-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=VI,VI-GISEL %s
declare i64 @llvm.amdgcn.mqsad.pk.u16.u8(i64, i32, i64) #0
-; GCN-LABEL: {{^}}v_mqsad_pk_u16_u8:
-; GFX600: v_mqsad_pk_u16_u8 v[0:1], v[4:5], s{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
-; GFX600-DAG: v_mov_b32_e32 v5, v1
-; GFX600-DAG: v_mov_b32_e32 v4, v0
-; GFX803: v_mqsad_pk_u16_u8 v[0:1], v[4:5], s{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
-; GFX803-DAG: v_mov_b32_e32 v5, v1
-; GFX803-DAG: v_mov_b32_e32 v4, v0
-; GFX13: v_mqsad_pk_u16_u8 v[0:1], v[4:5], 0x64, 0x64
define amdgpu_kernel void @v_mqsad_pk_u16_u8(ptr addrspace(1) %out, i64 %src) {
+; SI-SDAG-LABEL: v_mqsad_pk_u16_u8:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x64
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s6, -1
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, s0
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; SI-SDAG-NEXT: s_movk_i32 s0, 0x64
+; SI-SDAG-NEXT: s_mov_b32 s5, s1
+; SI-SDAG-NEXT: ;;#ASMSTART
+; SI-SDAG-NEXT: v_lsrlrev_b64 v[4:5], v[0:1], 1
+; SI-SDAG-NEXT: ;;#ASMEND
+; SI-SDAG-NEXT: v_mqsad_pk_u16_u8 v[0:1], v[4:5], s0, v[2:3]
+; SI-SDAG-NEXT: v_mov_b32_e32 v5, v1
+; SI-SDAG-NEXT: v_mov_b32_e32 v4, v0
+; SI-SDAG-NEXT: ;;#ASMSTART
+; SI-SDAG-NEXT: ;; force constraint
+; SI-SDAG-NEXT: ;;#ASMEND
+; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: v_mqsad_pk_u16_u8:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x64
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x64
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; SI-GISEL-NEXT: ;;#ASMSTART
+; SI-GISEL-NEXT: v_lsrlrev_b64 v[4:5], v[0:1], 1
+; SI-GISEL-NEXT: ;;#ASMEND
+; SI-GISEL-NEXT: v_mqsad_pk_u16_u8 v[0:1], v[4:5], v6, v[2:3]
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, v0
+; SI-GISEL-NEXT: ;;#ASMSTART
+; SI-GISEL-NEXT: ;; force constraint
+; SI-GISEL-NEXT: ;;#ASMEND
+; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: v_mqsad_pk_u16_u8:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-SDAG-NEXT: s_movk_i32 s4, 0x64
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0x64
+; VI-SDAG-NEXT: v_mov_b32_e32 v7, 0
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
+; VI-SDAG-NEXT: ;;#ASMSTART
+; VI-SDAG-NEXT: v_lsrlrev_b64 v[4:5], v[0:1], 1
+; VI-SDAG-NEXT: ;;#ASMEND
+; VI-SDAG-NEXT: v_mqsad_pk_u16_u8 v[0:1], v[4:5], s4, v[6:7]
+; VI-SDAG-NEXT: v_mov_b32_e32 v5, v1
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, v0
+; VI-SDAG-NEXT: ;;#ASMSTART
+; VI-SDAG-NEXT: ;; force constraint
+; VI-SDAG-NEXT: ;;#ASMEND
+; VI-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: v_mqsad_pk_u16_u8:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x64
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x64
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: ;;#ASMSTART
+; VI-GISEL-NEXT: v_lsrlrev_b64 v[4:5], v[0:1], 1
+; VI-GISEL-NEXT: ;;#ASMEND
+; VI-GISEL-NEXT: v_mqsad_pk_u16_u8 v[0:1], v[4:5], v6, v[2:3]
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, v0
+; VI-GISEL-NEXT: ;;#ASMSTART
+; VI-GISEL-NEXT: ;; force constraint
+; VI-GISEL-NEXT: ;;#ASMEND
+; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-GISEL-NEXT: s_endpgm
%tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[4:5]},v"(i64 %src) #0
%tmp1 = call i64 @llvm.amdgcn.mqsad.pk.u16.u8(i64 %tmp, i32 100, i64 100) #0
%tmp2 = call i64 asm ";; force constraint", "=v,{v[4:5]}"(i64 %tmp1) #0
@@ -20,13 +107,132 @@ define amdgpu_kernel void @v_mqsad_pk_u16_u8(ptr addrspace(1) %out, i64 %src) {
ret void
}
-; GCN-LABEL: {{^}}v_mqsad_pk_u16_u8_non_immediate:
-; GCN: v_mqsad_pk_u16_u8 v[0:1], v[2:3], v4, v[6:7]
-; GFX600-DAG: v_mov_b32_e32 v3, v1
-; GFX600-DAG: v_mov_b32_e32 v2, v0
-; GFX803-DAG: v_mov_b32_e32 v3, v1
-; GFX803-DAG: v_mov_b32_e32 v2, v0
define amdgpu_kernel void @v_mqsad_pk_u16_u8_non_immediate(ptr addrspace(1) %out, i64 %src, i32 %a, i64 %b) {
+; SI-SDAG-LABEL: v_mqsad_pk_u16_u8_non_immediate:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-SDAG-NEXT: s_load_dword s10, s[4:5], 0xd
+; SI-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xf
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s6, -1
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; SI-SDAG-NEXT: ;;#ASMSTART
+; SI-SDAG-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; SI-SDAG-NEXT: ;;#ASMEND
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, s10
+; SI-SDAG-NEXT: ;;#ASMSTART
+; SI-SDAG-NEXT: v_mov_b32 v4, v0
+; SI-SDAG-NEXT: ;;#ASMEND
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, s8
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s9
+; SI-SDAG-NEXT: s_mov_b32 s4, s0
+; SI-SDAG-NEXT: s_mov_b32 s5, s1
+; SI-SDAG-NEXT: ;;#ASMSTART
+; SI-SDAG-NEXT: v_lshlrev_b64 v[6:7], v[0:1], 1
+; SI-SDAG-NEXT: ;;#ASMEND
+; SI-SDAG-NEXT: v_mqsad_pk_u16_u8 v[0:1], v[2:3], v4, v[6:7]
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, v1
+; SI-SDAG-NEXT: v_mov_b32_e32 v2, v0
+; SI-SDAG-NEXT: ;;#ASMSTART
+; SI-SDAG-NEXT: ;; force constraint
+; SI-SDAG-NEXT: ;;#ASMEND
+; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: v_mqsad_pk_u16_u8_non_immediate:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-GISEL-NEXT: s_load_dword s6, s[4:5], 0xd
+; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xf
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, s6
+; SI-GISEL-NEXT: ;;#ASMSTART
+; SI-GISEL-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; SI-GISEL-NEXT: ;;#ASMEND
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; SI-GISEL-NEXT: ;;#ASMSTART
+; SI-GISEL-NEXT: v_mov_b32 v4, v4
+; SI-GISEL-NEXT: ;;#ASMEND
+; SI-GISEL-NEXT: ;;#ASMSTART
+; SI-GISEL-NEXT: v_lshlrev_b64 v[6:7], v[0:1], 1
+; SI-GISEL-NEXT: ;;#ASMEND
+; SI-GISEL-NEXT: v_mqsad_pk_u16_u8 v[0:1], v[2:3], v4, v[6:7]
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, v0
+; SI-GISEL-NEXT: ;;#ASMSTART
+; SI-GISEL-NEXT: ;; force constraint
+; SI-GISEL-NEXT: ;;#ASMEND
+; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: v_mqsad_pk_u16_u8_non_immediate:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-SDAG-NEXT: s_load_dword s6, s[4:5], 0x34
+; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x3c
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; VI-SDAG-NEXT: ;;#ASMSTART
+; VI-SDAG-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; VI-SDAG-NEXT: ;;#ASMEND
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, s6
+; VI-SDAG-NEXT: ;;#ASMSTART
+; VI-SDAG-NEXT: v_mov_b32 v4, v0
+; VI-SDAG-NEXT: ;;#ASMEND
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, s4
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s5
+; VI-SDAG-NEXT: v_mov_b32_e32 v8, s0
+; VI-SDAG-NEXT: v_mov_b32_e32 v9, s1
+; VI-SDAG-NEXT: ;;#ASMSTART
+; VI-SDAG-NEXT: v_lshlrev_b64 v[6:7], v[0:1], 1
+; VI-SDAG-NEXT: ;;#ASMEND
+; VI-SDAG-NEXT: v_mqsad_pk_u16_u8 v[0:1], v[2:3], v4, v[6:7]
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, v1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, v0
+; VI-SDAG-NEXT: ;;#ASMSTART
+; VI-SDAG-NEXT: ;; force constraint
+; VI-SDAG-NEXT: ;;#ASMEND
+; VI-SDAG-NEXT: flat_store_dwordx2 v[8:9], v[0:1]
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: v_mqsad_pk_u16_u8_non_immediate:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-GISEL-NEXT: s_load_dword s6, s[4:5], 0x34
+; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x3c
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s6
+; VI-GISEL-NEXT: ;;#ASMSTART
+; VI-GISEL-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; VI-GISEL-NEXT: ;;#ASMEND
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; VI-GISEL-NEXT: ;;#ASMSTART
+; VI-GISEL-NEXT: v_mov_b32 v4, v4
+; VI-GISEL-NEXT: ;;#ASMEND
+; VI-GISEL-NEXT: ;;#ASMSTART
+; VI-GISEL-NEXT: v_lshlrev_b64 v[6:7], v[0:1], 1
+; VI-GISEL-NEXT: ;;#ASMEND
+; VI-GISEL-NEXT: v_mqsad_pk_u16_u8 v[0:1], v[2:3], v4, v[6:7]
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, v0
+; VI-GISEL-NEXT: ;;#ASMSTART
+; VI-GISEL-NEXT: ;; force constraint
+; VI-GISEL-NEXT: ;;#ASMEND
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-GISEL-NEXT: s_endpgm
%tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0
%tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
%tmp2 = call i64 asm "v_lshlrev_b64 $0, $1, 1", "={v[6:7]},v"(i64 %b) #0
@@ -37,3 +243,6 @@ define amdgpu_kernel void @v_mqsad_pk_u16_u8_non_immediate(ptr addrspace(1) %out
}
attributes #0 = { nounwind readnone }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; SI: {{.*}}
+; VI: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll
index 41ba33f089d24..1d19e9225e56b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll
@@ -1,17 +1,200 @@
-; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GCN,GFX600 %s
-; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GCN,GFX803 %s
-; RUN: llc -mtriple=amdgpu13.10 < %s | FileCheck -check-prefixes=GCN,GFX13 %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GFX600,GFX600-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GFX600,GFX600-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GFX803,GFX803-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GFX803,GFX803-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu13.10 < %s | FileCheck -check-prefixes=GFX13,GFX13-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu13.10 < %s | FileCheck -check-prefixes=GFX13,GFX13-GISEL %s
declare <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64, i32, <4 x i32>) #0
-; GCN-LABEL: {{^}}v_mqsad_u32_u8_inline_integer_immediate:
-; GFX600-DAG: v_mov_b32_e32 v0, v2
-; GFX600-DAG: v_mov_b32_e32 v1, v3
-; GFX803-DAG: v_mov_b32_e32 v0, v2
-; GFX803-DAG: v_mov_b32_e32 v1, v3
-; GFX13-NOT: v_mov_b32_e32
-; GCN: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[{{[0-9]+:[0-9]+}}]
define amdgpu_kernel void @v_mqsad_u32_u8_inline_integer_immediate(ptr addrspace(1) %out, i64 %src, i32 %a) {
+; GFX600-SDAG-LABEL: v_mqsad_u32_u8_inline_integer_immediate:
+; GFX600-SDAG: ; %bb.0:
+; GFX600-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX600-SDAG-NEXT: s_load_dword s4, s[4:5], 0xd
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v7, 10
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v8, 20
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v9, 30
+; GFX600-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v4, s4
+; GFX600-SDAG-NEXT: ;;#ASMSTART
+; GFX600-SDAG-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX600-SDAG-NEXT: ;;#ASMEND
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v0, v2
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v1, v3
+; GFX600-SDAG-NEXT: ;;#ASMSTART
+; GFX600-SDAG-NEXT: v_mov_b32 v4, v4
+; GFX600-SDAG-NEXT: ;;#ASMEND
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v6, v4
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v10, 40
+; GFX600-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX600-SDAG-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX600-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX600-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX600-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX600-SDAG-NEXT: ;;#ASMSTART
+; GFX600-SDAG-NEXT: ;; force constraint
+; GFX600-SDAG-NEXT: ;;#ASMEND
+; GFX600-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX600-SDAG-NEXT: s_endpgm
+;
+; GFX600-GISEL-LABEL: v_mqsad_u32_u8_inline_integer_immediate:
+; GFX600-GISEL: ; %bb.0:
+; GFX600-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
+; GFX600-GISEL-NEXT: s_load_dword s4, s[4:5], 0xd
+; GFX600-GISEL-NEXT: s_mov_b32 s3, 40
+; GFX600-GISEL-NEXT: s_mov_b32 s2, 30
+; GFX600-GISEL-NEXT: s_mov_b32 s1, 20
+; GFX600-GISEL-NEXT: s_mov_b32 s0, 10
+; GFX600-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v1, s11
+; GFX600-GISEL-NEXT: ;;#ASMSTART
+; GFX600-GISEL-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX600-GISEL-NEXT: ;;#ASMEND
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v0, v2
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v1, v3
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX600-GISEL-NEXT: ;;#ASMSTART
+; GFX600-GISEL-NEXT: v_mov_b32 v4, v2
+; GFX600-GISEL-NEXT: ;;#ASMEND
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v6, v4
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v10, s3
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v9, s2
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v8, s1
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v7, s0
+; GFX600-GISEL-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX600-GISEL-NEXT: s_mov_b32 s10, -1
+; GFX600-GISEL-NEXT: s_mov_b32 s11, 0xf000
+; GFX600-GISEL-NEXT: ;;#ASMSTART
+; GFX600-GISEL-NEXT: ;; force constraint
+; GFX600-GISEL-NEXT: ;;#ASMEND
+; GFX600-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX600-GISEL-NEXT: s_endpgm
+;
+; GFX803-SDAG-LABEL: v_mqsad_u32_u8_inline_integer_immediate:
+; GFX803-SDAG: ; %bb.0:
+; GFX803-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX803-SDAG-NEXT: s_load_dword s4, s[4:5], 0x34
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v7, 10
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v8, 20
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v9, 30
+; GFX803-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v4, s4
+; GFX803-SDAG-NEXT: ;;#ASMSTART
+; GFX803-SDAG-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX803-SDAG-NEXT: ;;#ASMEND
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v0, v2
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v1, v3
+; GFX803-SDAG-NEXT: ;;#ASMSTART
+; GFX803-SDAG-NEXT: v_mov_b32 v4, v4
+; GFX803-SDAG-NEXT: ;;#ASMEND
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v6, v4
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v10, 40
+; GFX803-SDAG-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v6, s0
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v7, s1
+; GFX803-SDAG-NEXT: ;;#ASMSTART
+; GFX803-SDAG-NEXT: ;; force constraint
+; GFX803-SDAG-NEXT: ;;#ASMEND
+; GFX803-SDAG-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; GFX803-SDAG-NEXT: s_endpgm
+;
+; GFX803-GISEL-LABEL: v_mqsad_u32_u8_inline_integer_immediate:
+; GFX803-GISEL: ; %bb.0:
+; GFX803-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
+; GFX803-GISEL-NEXT: s_load_dword s4, s[4:5], 0x34
+; GFX803-GISEL-NEXT: s_mov_b32 s3, 40
+; GFX803-GISEL-NEXT: s_mov_b32 s2, 30
+; GFX803-GISEL-NEXT: s_mov_b32 s1, 20
+; GFX803-GISEL-NEXT: s_mov_b32 s0, 10
+; GFX803-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v1, s11
+; GFX803-GISEL-NEXT: ;;#ASMSTART
+; GFX803-GISEL-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX803-GISEL-NEXT: ;;#ASMEND
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v0, v2
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v1, v3
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX803-GISEL-NEXT: ;;#ASMSTART
+; GFX803-GISEL-NEXT: v_mov_b32 v4, v2
+; GFX803-GISEL-NEXT: ;;#ASMEND
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v6, v4
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v10, s3
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v9, s2
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v8, s1
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v7, s0
+; GFX803-GISEL-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX803-GISEL-NEXT: ;;#ASMSTART
+; GFX803-GISEL-NEXT: ;; force constraint
+; GFX803-GISEL-NEXT: ;;#ASMEND
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v5, s9
+; GFX803-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX803-GISEL-NEXT: s_endpgm
+;
+; GFX13-SDAG-LABEL: v_mqsad_u32_u8_inline_integer_immediate:
+; GFX13-SDAG: ; %bb.0:
+; GFX13-SDAG-NEXT: s_clause 0x1
+; GFX13-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX13-SDAG-NEXT: s_load_b32 s4, s[4:5], 0x34 nv
+; GFX13-SDAG-NEXT: v_dual_mov_b32 v7, 10 :: v_dual_mov_b32 v8, 20
+; GFX13-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX13-SDAG-NEXT: v_dual_mov_b32 v9, 30 :: v_dual_mov_b32 v0, s2
+; GFX13-SDAG-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v4, s4
+; GFX13-SDAG-NEXT: ;;#ASMSTART
+; GFX13-SDAG-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX13-SDAG-NEXT: ;;#ASMEND
+; GFX13-SDAG-NEXT: v_dual_mov_b32 v10, 40 :: v_dual_mov_b32 v0, v2
+; GFX13-SDAG-NEXT: ;;#ASMSTART
+; GFX13-SDAG-NEXT: v_mov_b32 v4, v4
+; GFX13-SDAG-NEXT: ;;#ASMEND
+; GFX13-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13-SDAG-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v6, v4
+; GFX13-SDAG-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX13-SDAG-NEXT: v_mov_b32_e32 v6, 0
+; GFX13-SDAG-NEXT: ;;#ASMSTART
+; GFX13-SDAG-NEXT: ;; force constraint
+; GFX13-SDAG-NEXT: ;;#ASMEND
+; GFX13-SDAG-NEXT: global_store_b128 v6, v[0:3], s[0:1]
+; GFX13-SDAG-NEXT: s_endpgm
+;
+; GFX13-GISEL-LABEL: v_mqsad_u32_u8_inline_integer_immediate:
+; GFX13-GISEL: ; %bb.0:
+; GFX13-GISEL-NEXT: s_clause 0x1
+; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX13-GISEL-NEXT: s_load_b32 s4, s[4:5], 0x34 nv
+; GFX13-GISEL-NEXT: s_mov_b32 s7, 40
+; GFX13-GISEL-NEXT: s_mov_b32 s6, 30
+; GFX13-GISEL-NEXT: s_mov_b32 s5, 20
+; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX13-GISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX13-GISEL-NEXT: s_mov_b32 s4, 10
+; GFX13-GISEL-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
+; GFX13-GISEL-NEXT: v_mov_b32_e32 v8, s5
+; GFX13-GISEL-NEXT: ;;#ASMSTART
+; GFX13-GISEL-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX13-GISEL-NEXT: ;;#ASMEND
+; GFX13-GISEL-NEXT: v_dual_mov_b32 v7, s4 :: v_dual_mov_b32 v0, v2
+; GFX13-GISEL-NEXT: ;;#ASMSTART
+; GFX13-GISEL-NEXT: v_mov_b32 v4, v4
+; GFX13-GISEL-NEXT: ;;#ASMEND
+; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v6, v4
+; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13-GISEL-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX13-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; GFX13-GISEL-NEXT: ;;#ASMSTART
+; GFX13-GISEL-NEXT: ;; force constraint
+; GFX13-GISEL-NEXT: ;;#ASMEND
+; GFX13-GISEL-NEXT: global_store_b128 v6, v[0:3], s[0:1]
+; GFX13-GISEL-NEXT: s_endpgm
%tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0
%tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
%tmp2 = call <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64 %tmp, i32 %tmp1, <4 x i32> <i32 10, i32 20, i32 30, i32 40>) #0
@@ -20,14 +203,159 @@ define amdgpu_kernel void @v_mqsad_u32_u8_inline_integer_immediate(ptr addrspace
ret void
}
-; GCN-LABEL: {{^}}v_mqsad_u32_u8_non_immediate:
-; GFX600-DAG: v_mov_b32_e32 v0, v2
-; GFX600-DAG: v_mov_b32_e32 v1, v3
-; GFX803-DAG: v_mov_b32_e32 v0, v2
-; GFX803-DAG: v_mov_b32_e32 v1, v3
-; GFX13-NOT: v_mov_b32_e32
-; GCN: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[{{[0-9]+:[0-9]+}}]
define amdgpu_kernel void @v_mqsad_u32_u8_non_immediate(ptr addrspace(1) %out, i64 %src, i32 %a, <4 x i32> %b) {
+; GFX600-SDAG-LABEL: v_mqsad_u32_u8_non_immediate:
+; GFX600-SDAG: ; %bb.0:
+; GFX600-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX600-SDAG-NEXT: s_load_dword s6, s[4:5], 0xd
+; GFX600-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x11
+; GFX600-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX600-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX600-SDAG-NEXT: ;;#ASMSTART
+; GFX600-SDAG-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX600-SDAG-NEXT: ;;#ASMEND
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v0, v2
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v1, v3
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v2, s6
+; GFX600-SDAG-NEXT: ;;#ASMSTART
+; GFX600-SDAG-NEXT: v_mov_b32 v4, v2
+; GFX600-SDAG-NEXT: ;;#ASMEND
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v6, v4
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v7, s8
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v8, s9
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v9, s10
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v10, s11
+; GFX600-SDAG-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX600-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX600-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX600-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX600-SDAG-NEXT: ;;#ASMSTART
+; GFX600-SDAG-NEXT: ;; force constraint
+; GFX600-SDAG-NEXT: ;;#ASMEND
+; GFX600-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX600-SDAG-NEXT: s_endpgm
+;
+; GFX600-GISEL-LABEL: v_mqsad_u32_u8_non_immediate:
+; GFX600-GISEL: ; %bb.0:
+; GFX600-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX600-GISEL-NEXT: s_load_dword s8, s[4:5], 0xd
+; GFX600-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x11
+; GFX600-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX600-GISEL-NEXT: ;;#ASMSTART
+; GFX600-GISEL-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX600-GISEL-NEXT: ;;#ASMEND
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v0, v2
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v1, v3
+; GFX600-GISEL-NEXT: ;;#ASMSTART
+; GFX600-GISEL-NEXT: v_mov_b32 v4, v4
+; GFX600-GISEL-NEXT: ;;#ASMEND
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v6, v4
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v10, s7
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v9, s6
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v8, s5
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v7, s4
+; GFX600-GISEL-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX600-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX600-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX600-GISEL-NEXT: ;;#ASMSTART
+; GFX600-GISEL-NEXT: ;; force constraint
+; GFX600-GISEL-NEXT: ;;#ASMEND
+; GFX600-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX600-GISEL-NEXT: s_endpgm
+;
+; GFX803-SDAG-LABEL: v_mqsad_u32_u8_non_immediate:
+; GFX803-SDAG: ; %bb.0:
+; GFX803-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX803-SDAG-NEXT: s_load_dword s8, s[4:5], 0x34
+; GFX803-SDAG-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x44
+; GFX803-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v4, s8
+; GFX803-SDAG-NEXT: ;;#ASMSTART
+; GFX803-SDAG-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX803-SDAG-NEXT: ;;#ASMEND
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v0, v2
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v1, v3
+; GFX803-SDAG-NEXT: ;;#ASMSTART
+; GFX803-SDAG-NEXT: v_mov_b32 v4, v4
+; GFX803-SDAG-NEXT: ;;#ASMEND
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v6, v4
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v10, s7
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v9, s6
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v8, s5
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v7, s4
+; GFX803-SDAG-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v6, s0
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v7, s1
+; GFX803-SDAG-NEXT: ;;#ASMSTART
+; GFX803-SDAG-NEXT: ;; force constraint
+; GFX803-SDAG-NEXT: ;;#ASMEND
+; GFX803-SDAG-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; GFX803-SDAG-NEXT: s_endpgm
+;
+; GFX803-GISEL-LABEL: v_mqsad_u32_u8_non_immediate:
+; GFX803-GISEL: ; %bb.0:
+; GFX803-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX803-GISEL-NEXT: s_load_dword s8, s[4:5], 0x34
+; GFX803-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x44
+; GFX803-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX803-GISEL-NEXT: ;;#ASMSTART
+; GFX803-GISEL-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX803-GISEL-NEXT: ;;#ASMEND
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v0, v2
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v1, v3
+; GFX803-GISEL-NEXT: ;;#ASMSTART
+; GFX803-GISEL-NEXT: v_mov_b32 v4, v4
+; GFX803-GISEL-NEXT: ;;#ASMEND
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v6, v4
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v10, s7
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v9, s6
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v8, s5
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v7, s4
+; GFX803-GISEL-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX803-GISEL-NEXT: ;;#ASMSTART
+; GFX803-GISEL-NEXT: ;; force constraint
+; GFX803-GISEL-NEXT: ;;#ASMEND
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v5, s1
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v4, s0
+; GFX803-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX803-GISEL-NEXT: s_endpgm
+;
+; GFX13-LABEL: v_mqsad_u32_u8_non_immediate:
+; GFX13: ; %bb.0:
+; GFX13-NEXT: s_clause 0x2
+; GFX13-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX13-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX13-NEXT: s_load_b128 s[4:7], s[4:5], 0x44 nv
+; GFX13-NEXT: s_wait_kmcnt 0x0
+; GFX13-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX13-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v10, s7
+; GFX13-NEXT: v_dual_mov_b32 v9, s6 :: v_dual_mov_b32 v8, s5
+; GFX13-NEXT: ;;#ASMSTART
+; GFX13-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX13-NEXT: ;;#ASMEND
+; GFX13-NEXT: v_dual_mov_b32 v7, s4 :: v_dual_mov_b32 v0, v2
+; GFX13-NEXT: ;;#ASMSTART
+; GFX13-NEXT: v_mov_b32 v4, v4
+; GFX13-NEXT: ;;#ASMEND
+; GFX13-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v6, v4
+; GFX13-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX13-NEXT: v_mov_b32_e32 v6, 0
+; GFX13-NEXT: ;;#ASMSTART
+; GFX13-NEXT: ;; force constraint
+; GFX13-NEXT: ;;#ASMEND
+; GFX13-NEXT: global_store_b128 v6, v[0:3], s[0:1]
+; GFX13-NEXT: s_endpgm
%tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0
%tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
%tmp2 = call <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64 %tmp, i32 %tmp1, <4 x i32> %b) #0
@@ -36,14 +364,192 @@ define amdgpu_kernel void @v_mqsad_u32_u8_non_immediate(ptr addrspace(1) %out, i
ret void
}
-; GCN-LABEL: {{^}}v_mqsad_u32_u8_inline_fp_immediate:
-; GFX600-DAG: v_mov_b32_e32 v0, v2
-; GFX600-DAG: v_mov_b32_e32 v1, v3
-; GFX803-DAG: v_mov_b32_e32 v0, v2
-; GFX803-DAG: v_mov_b32_e32 v1, v3
-; GFX13-NOT: v_mov_b32_e32
-; GCN: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[{{[0-9]+:[0-9]+}}]
define amdgpu_kernel void @v_mqsad_u32_u8_inline_fp_immediate(ptr addrspace(1) %out, i64 %src, i32 %a) {
+; GFX600-SDAG-LABEL: v_mqsad_u32_u8_inline_fp_immediate:
+; GFX600-SDAG: ; %bb.0:
+; GFX600-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX600-SDAG-NEXT: s_load_dword s4, s[4:5], 0xd
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v8, 0
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v7, 1.0
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v9, v8
+; GFX600-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v4, s4
+; GFX600-SDAG-NEXT: ;;#ASMSTART
+; GFX600-SDAG-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX600-SDAG-NEXT: ;;#ASMEND
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v0, v2
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v1, v3
+; GFX600-SDAG-NEXT: ;;#ASMSTART
+; GFX600-SDAG-NEXT: v_mov_b32 v4, v4
+; GFX600-SDAG-NEXT: ;;#ASMEND
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v6, v4
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v10, v8
+; GFX600-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX600-SDAG-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX600-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX600-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX600-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX600-SDAG-NEXT: ;;#ASMSTART
+; GFX600-SDAG-NEXT: ;; force constraint
+; GFX600-SDAG-NEXT: ;;#ASMEND
+; GFX600-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX600-SDAG-NEXT: s_endpgm
+;
+; GFX600-GISEL-LABEL: v_mqsad_u32_u8_inline_fp_immediate:
+; GFX600-GISEL: ; %bb.0:
+; GFX600-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
+; GFX600-GISEL-NEXT: s_load_dword s4, s[4:5], 0xd
+; GFX600-GISEL-NEXT: s_mov_b32 s1, 0
+; GFX600-GISEL-NEXT: s_mov_b32 s0, 1.0
+; GFX600-GISEL-NEXT: s_mov_b32 s2, s1
+; GFX600-GISEL-NEXT: s_mov_b32 s3, s1
+; GFX600-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v1, s11
+; GFX600-GISEL-NEXT: ;;#ASMSTART
+; GFX600-GISEL-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX600-GISEL-NEXT: ;;#ASMEND
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v0, v2
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v1, v3
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX600-GISEL-NEXT: ;;#ASMSTART
+; GFX600-GISEL-NEXT: v_mov_b32 v4, v2
+; GFX600-GISEL-NEXT: ;;#ASMEND
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v6, v4
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v10, s3
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v9, s2
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v8, s1
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v7, s0
+; GFX600-GISEL-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX600-GISEL-NEXT: s_mov_b32 s10, -1
+; GFX600-GISEL-NEXT: s_mov_b32 s11, 0xf000
+; GFX600-GISEL-NEXT: ;;#ASMSTART
+; GFX600-GISEL-NEXT: ;; force constraint
+; GFX600-GISEL-NEXT: ;;#ASMEND
+; GFX600-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX600-GISEL-NEXT: s_endpgm
+;
+; GFX803-SDAG-LABEL: v_mqsad_u32_u8_inline_fp_immediate:
+; GFX803-SDAG: ; %bb.0:
+; GFX803-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX803-SDAG-NEXT: s_load_dword s4, s[4:5], 0x34
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v8, 0
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v7, 1.0
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v9, v8
+; GFX803-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v4, s4
+; GFX803-SDAG-NEXT: ;;#ASMSTART
+; GFX803-SDAG-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX803-SDAG-NEXT: ;;#ASMEND
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v0, v2
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v1, v3
+; GFX803-SDAG-NEXT: ;;#ASMSTART
+; GFX803-SDAG-NEXT: v_mov_b32 v4, v4
+; GFX803-SDAG-NEXT: ;;#ASMEND
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v6, v4
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v10, v8
+; GFX803-SDAG-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v6, s0
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v7, s1
+; GFX803-SDAG-NEXT: ;;#ASMSTART
+; GFX803-SDAG-NEXT: ;; force constraint
+; GFX803-SDAG-NEXT: ;;#ASMEND
+; GFX803-SDAG-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; GFX803-SDAG-NEXT: s_endpgm
+;
+; GFX803-GISEL-LABEL: v_mqsad_u32_u8_inline_fp_immediate:
+; GFX803-GISEL: ; %bb.0:
+; GFX803-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
+; GFX803-GISEL-NEXT: s_load_dword s4, s[4:5], 0x34
+; GFX803-GISEL-NEXT: s_mov_b32 s1, 0
+; GFX803-GISEL-NEXT: s_mov_b32 s0, 1.0
+; GFX803-GISEL-NEXT: s_mov_b32 s2, s1
+; GFX803-GISEL-NEXT: s_mov_b32 s3, s1
+; GFX803-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v1, s11
+; GFX803-GISEL-NEXT: ;;#ASMSTART
+; GFX803-GISEL-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX803-GISEL-NEXT: ;;#ASMEND
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v0, v2
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v1, v3
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX803-GISEL-NEXT: ;;#ASMSTART
+; GFX803-GISEL-NEXT: v_mov_b32 v4, v2
+; GFX803-GISEL-NEXT: ;;#ASMEND
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v6, v4
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v10, s3
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v9, s2
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v8, s1
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v7, s0
+; GFX803-GISEL-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX803-GISEL-NEXT: ;;#ASMSTART
+; GFX803-GISEL-NEXT: ;; force constraint
+; GFX803-GISEL-NEXT: ;;#ASMEND
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v5, s9
+; GFX803-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX803-GISEL-NEXT: s_endpgm
+;
+; GFX13-SDAG-LABEL: v_mqsad_u32_u8_inline_fp_immediate:
+; GFX13-SDAG: ; %bb.0:
+; GFX13-SDAG-NEXT: s_clause 0x1
+; GFX13-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX13-SDAG-NEXT: s_load_b32 s4, s[4:5], 0x34 nv
+; GFX13-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX13-SDAG-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v0, s2
+; GFX13-SDAG-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v4, s4
+; GFX13-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX13-SDAG-NEXT: v_dual_mov_b32 v7, 1.0 :: v_dual_mov_b32 v9, v8
+; GFX13-SDAG-NEXT: ;;#ASMSTART
+; GFX13-SDAG-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX13-SDAG-NEXT: ;;#ASMEND
+; GFX13-SDAG-NEXT: v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v0, v2
+; GFX13-SDAG-NEXT: ;;#ASMSTART
+; GFX13-SDAG-NEXT: v_mov_b32 v4, v4
+; GFX13-SDAG-NEXT: ;;#ASMEND
+; GFX13-SDAG-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v6, v4
+; GFX13-SDAG-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX13-SDAG-NEXT: ;;#ASMSTART
+; GFX13-SDAG-NEXT: ;; force constraint
+; GFX13-SDAG-NEXT: ;;#ASMEND
+; GFX13-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1]
+; GFX13-SDAG-NEXT: s_endpgm
+;
+; GFX13-GISEL-LABEL: v_mqsad_u32_u8_inline_fp_immediate:
+; GFX13-GISEL: ; %bb.0:
+; GFX13-GISEL-NEXT: s_clause 0x1
+; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX13-GISEL-NEXT: s_load_b32 s7, s[4:5], 0x34 nv
+; GFX13-GISEL-NEXT: s_mov_b32 s5, 0
+; GFX13-GISEL-NEXT: s_mov_b32 s4, 1.0
+; GFX13-GISEL-NEXT: s_mov_b32 s6, s5
+; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX13-GISEL-NEXT: v_mov_b32_e32 v4, s7
+; GFX13-GISEL-NEXT: s_mov_b32 s7, s5
+; GFX13-GISEL-NEXT: v_dual_mov_b32 v9, s6 :: v_dual_mov_b32 v8, s5
+; GFX13-GISEL-NEXT: v_mov_b32_e32 v10, s7
+; GFX13-GISEL-NEXT: ;;#ASMSTART
+; GFX13-GISEL-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX13-GISEL-NEXT: ;;#ASMEND
+; GFX13-GISEL-NEXT: v_dual_mov_b32 v7, s4 :: v_dual_mov_b32 v0, v2
+; GFX13-GISEL-NEXT: ;;#ASMSTART
+; GFX13-GISEL-NEXT: v_mov_b32 v4, v4
+; GFX13-GISEL-NEXT: ;;#ASMEND
+; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v6, v4
+; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13-GISEL-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX13-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; GFX13-GISEL-NEXT: ;;#ASMSTART
+; GFX13-GISEL-NEXT: ;; force constraint
+; GFX13-GISEL-NEXT: ;;#ASMEND
+; GFX13-GISEL-NEXT: global_store_b128 v6, v[0:3], s[0:1]
+; GFX13-GISEL-NEXT: s_endpgm
%tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0
%tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
%tmp2 = call <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64 %tmp, i32 %tmp1, <4 x i32> <i32 1065353216, i32 0, i32 0, i32 0>) #0
@@ -52,14 +558,169 @@ define amdgpu_kernel void @v_mqsad_u32_u8_inline_fp_immediate(ptr addrspace(1) %
ret void
}
-; GCN-LABEL: {{^}}v_mqsad_u32_u8_use_sgpr_vgpr:
-; GFX600-DAG: v_mov_b32_e32 v0, v2
-; GFX600-DAG: v_mov_b32_e32 v1, v3
-; GFX803-DAG: v_mov_b32_e32 v0, v2
-; GFX803-DAG: v_mov_b32_e32 v1, v3
-; GFX13-NOT: v_mov_b32_e32
-; GCN: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[{{[0-9]+:[0-9]+}}]
define amdgpu_kernel void @v_mqsad_u32_u8_use_sgpr_vgpr(ptr addrspace(1) %out, i64 %src, i32 %a, ptr addrspace(1) %input) {
+; GFX600-SDAG-LABEL: v_mqsad_u32_u8_use_sgpr_vgpr:
+; GFX600-SDAG: ; %bb.0:
+; GFX600-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX600-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xf
+; GFX600-SDAG-NEXT: s_load_dword s4, s[4:5], 0xd
+; GFX600-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GFX600-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX600-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX600-SDAG-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x0
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v4, s4
+; GFX600-SDAG-NEXT: ;;#ASMSTART
+; GFX600-SDAG-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX600-SDAG-NEXT: ;;#ASMEND
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v0, v2
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v1, v3
+; GFX600-SDAG-NEXT: ;;#ASMSTART
+; GFX600-SDAG-NEXT: v_mov_b32 v4, v4
+; GFX600-SDAG-NEXT: ;;#ASMEND
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v6, v4
+; GFX600-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v7, s8
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v8, s9
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v9, s10
+; GFX600-SDAG-NEXT: v_mov_b32_e32 v10, s11
+; GFX600-SDAG-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX600-SDAG-NEXT: s_mov_b32 s4, s0
+; GFX600-SDAG-NEXT: s_mov_b32 s5, s1
+; GFX600-SDAG-NEXT: ;;#ASMSTART
+; GFX600-SDAG-NEXT: ;; force constraint
+; GFX600-SDAG-NEXT: ;;#ASMEND
+; GFX600-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX600-SDAG-NEXT: s_endpgm
+;
+; GFX600-GISEL-LABEL: v_mqsad_u32_u8_use_sgpr_vgpr:
+; GFX600-GISEL: ; %bb.0:
+; GFX600-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xf
+; GFX600-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX600-GISEL-NEXT: s_load_dword s8, s[4:5], 0xd
+; GFX600-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX600-GISEL-NEXT: s_load_dwordx4 s[4:7], s[6:7], 0x0
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX600-GISEL-NEXT: ;;#ASMSTART
+; GFX600-GISEL-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX600-GISEL-NEXT: ;;#ASMEND
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v0, v2
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v1, v3
+; GFX600-GISEL-NEXT: ;;#ASMSTART
+; GFX600-GISEL-NEXT: v_mov_b32 v4, v4
+; GFX600-GISEL-NEXT: ;;#ASMEND
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v6, v4
+; GFX600-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v10, s7
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v9, s6
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v8, s5
+; GFX600-GISEL-NEXT: v_mov_b32_e32 v7, s4
+; GFX600-GISEL-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX600-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX600-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX600-GISEL-NEXT: ;;#ASMSTART
+; GFX600-GISEL-NEXT: ;; force constraint
+; GFX600-GISEL-NEXT: ;;#ASMEND
+; GFX600-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX600-GISEL-NEXT: s_endpgm
+;
+; GFX803-SDAG-LABEL: v_mqsad_u32_u8_use_sgpr_vgpr:
+; GFX803-SDAG: ; %bb.0:
+; GFX803-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX803-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x3c
+; GFX803-SDAG-NEXT: s_load_dword s8, s[4:5], 0x34
+; GFX803-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX803-SDAG-NEXT: s_load_dwordx4 s[4:7], s[6:7], 0x0
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v4, s8
+; GFX803-SDAG-NEXT: ;;#ASMSTART
+; GFX803-SDAG-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX803-SDAG-NEXT: ;;#ASMEND
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v0, v2
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v1, v3
+; GFX803-SDAG-NEXT: ;;#ASMSTART
+; GFX803-SDAG-NEXT: v_mov_b32 v4, v4
+; GFX803-SDAG-NEXT: ;;#ASMEND
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v6, v4
+; GFX803-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v10, s7
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v9, s6
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v8, s5
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v7, s4
+; GFX803-SDAG-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v6, s0
+; GFX803-SDAG-NEXT: v_mov_b32_e32 v7, s1
+; GFX803-SDAG-NEXT: ;;#ASMSTART
+; GFX803-SDAG-NEXT: ;; force constraint
+; GFX803-SDAG-NEXT: ;;#ASMEND
+; GFX803-SDAG-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; GFX803-SDAG-NEXT: s_endpgm
+;
+; GFX803-GISEL-LABEL: v_mqsad_u32_u8_use_sgpr_vgpr:
+; GFX803-GISEL: ; %bb.0:
+; GFX803-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x3c
+; GFX803-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX803-GISEL-NEXT: s_load_dword s8, s[4:5], 0x34
+; GFX803-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-GISEL-NEXT: s_load_dwordx4 s[4:7], s[6:7], 0x0
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX803-GISEL-NEXT: ;;#ASMSTART
+; GFX803-GISEL-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX803-GISEL-NEXT: ;;#ASMEND
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v0, v2
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v1, v3
+; GFX803-GISEL-NEXT: ;;#ASMSTART
+; GFX803-GISEL-NEXT: v_mov_b32 v4, v4
+; GFX803-GISEL-NEXT: ;;#ASMEND
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v6, v4
+; GFX803-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v10, s7
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v9, s6
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v8, s5
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v7, s4
+; GFX803-GISEL-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX803-GISEL-NEXT: ;;#ASMSTART
+; GFX803-GISEL-NEXT: ;; force constraint
+; GFX803-GISEL-NEXT: ;;#ASMEND
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v5, s1
+; GFX803-GISEL-NEXT: v_mov_b32_e32 v4, s0
+; GFX803-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX803-GISEL-NEXT: s_endpgm
+;
+; GFX13-LABEL: v_mqsad_u32_u8_use_sgpr_vgpr:
+; GFX13: ; %bb.0:
+; GFX13-NEXT: s_clause 0x2
+; GFX13-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c nv
+; GFX13-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX13-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX13-NEXT: s_wait_kmcnt 0x0
+; GFX13-NEXT: s_load_b128 s[4:7], s[6:7], 0x0
+; GFX13-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX13-NEXT: ;;#ASMSTART
+; GFX13-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; GFX13-NEXT: ;;#ASMEND
+; GFX13-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v0, v2
+; GFX13-NEXT: ;;#ASMSTART
+; GFX13-NEXT: v_mov_b32 v4, v4
+; GFX13-NEXT: ;;#ASMEND
+; GFX13-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX13-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v6, v4
+; GFX13-NEXT: s_wait_kmcnt 0x0
+; GFX13-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
+; GFX13-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
+; GFX13-NEXT: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[7:10]
+; GFX13-NEXT: v_mov_b32_e32 v6, 0
+; GFX13-NEXT: ;;#ASMSTART
+; GFX13-NEXT: ;; force constraint
+; GFX13-NEXT: ;;#ASMEND
+; GFX13-NEXT: global_store_b128 v6, v[0:3], s[0:1]
+; GFX13-NEXT: s_endpgm
%in = load <4 x i32>, ptr addrspace(1) %input
%tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0
%tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
@@ -70,3 +731,6 @@ define amdgpu_kernel void @v_mqsad_u32_u8_use_sgpr_vgpr(ptr addrspace(1) %out, i
}
attributes #0 = { nounwind readnone }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX600: {{.*}}
+; GFX803: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
index cdee887df1607..0efb9fd245fd6 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
@@ -1,13 +1,105 @@
-; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefix=GCN %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=SI,SI-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=SI,SI-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=VI,VI-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=VI,VI-GISEL %s
declare i64 @llvm.amdgcn.qsad.pk.u16.u8(i64, i32, i64) #0
-; GCN-LABEL: {{^}}v_qsad_pk_u16_u8:
-; GCN: v_qsad_pk_u16_u8 v[0:1], v[4:5], s{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
-; GCN-DAG: v_mov_b32_e32 v5, v1
-; GCN-DAG: v_mov_b32_e32 v4, v0
define amdgpu_kernel void @v_qsad_pk_u16_u8(ptr addrspace(1) %out, i64 %src) {
+; SI-SDAG-LABEL: v_qsad_pk_u16_u8:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-SDAG-NEXT: s_movk_i32 s4, 0x64
+; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x64
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; SI-SDAG-NEXT: ;;#ASMSTART
+; SI-SDAG-NEXT: v_lsrlrev_b64 v[4:5], v[0:1], 1
+; SI-SDAG-NEXT: ;;#ASMEND
+; SI-SDAG-NEXT: v_qsad_pk_u16_u8 v[0:1], v[4:5], s4, v[2:3]
+; SI-SDAG-NEXT: s_mov_b32 s6, -1
+; SI-SDAG-NEXT: s_mov_b32 s4, s0
+; SI-SDAG-NEXT: s_mov_b32 s5, s1
+; SI-SDAG-NEXT: v_mov_b32_e32 v5, v1
+; SI-SDAG-NEXT: v_mov_b32_e32 v4, v0
+; SI-SDAG-NEXT: ;;#ASMSTART
+; SI-SDAG-NEXT: ;; force constraint
+; SI-SDAG-NEXT: ;;#ASMEND
+; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: v_qsad_pk_u16_u8:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x64
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x64
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; SI-GISEL-NEXT: ;;#ASMSTART
+; SI-GISEL-NEXT: v_lsrlrev_b64 v[4:5], v[0:1], 1
+; SI-GISEL-NEXT: ;;#ASMEND
+; SI-GISEL-NEXT: v_qsad_pk_u16_u8 v[0:1], v[4:5], v6, v[2:3]
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, v0
+; SI-GISEL-NEXT: ;;#ASMSTART
+; SI-GISEL-NEXT: ;; force constraint
+; SI-GISEL-NEXT: ;;#ASMEND
+; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: v_qsad_pk_u16_u8:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-SDAG-NEXT: s_movk_i32 s4, 0x64
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x64
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; VI-SDAG-NEXT: ;;#ASMSTART
+; VI-SDAG-NEXT: v_lsrlrev_b64 v[4:5], v[0:1], 1
+; VI-SDAG-NEXT: ;;#ASMEND
+; VI-SDAG-NEXT: v_qsad_pk_u16_u8 v[0:1], v[4:5], s4, v[2:3]
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v5, v1
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, v0
+; VI-SDAG-NEXT: ;;#ASMSTART
+; VI-SDAG-NEXT: ;; force constraint
+; VI-SDAG-NEXT: ;;#ASMEND
+; VI-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: v_qsad_pk_u16_u8:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x64
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x64
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: ;;#ASMSTART
+; VI-GISEL-NEXT: v_lsrlrev_b64 v[4:5], v[0:1], 1
+; VI-GISEL-NEXT: ;;#ASMEND
+; VI-GISEL-NEXT: v_qsad_pk_u16_u8 v[0:1], v[4:5], v6, v[2:3]
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, v0
+; VI-GISEL-NEXT: ;;#ASMSTART
+; VI-GISEL-NEXT: ;; force constraint
+; VI-GISEL-NEXT: ;;#ASMEND
+; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-GISEL-NEXT: s_endpgm
%tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[4:5]},v"(i64 %src) #0
%tmp1 = call i64 @llvm.amdgcn.qsad.pk.u16.u8(i64 %tmp, i32 100, i64 100) #0
%tmp2 = call i64 asm ";; force constraint", "=v,{v[4:5]}"(i64 %tmp1) #0
@@ -15,11 +107,132 @@ define amdgpu_kernel void @v_qsad_pk_u16_u8(ptr addrspace(1) %out, i64 %src) {
ret void
}
-; GCN-LABEL: {{^}}v_qsad_pk_u16_u8_non_immediate:
-; GCN: v_qsad_pk_u16_u8 v[0:1], v[2:3], v4, v[6:7]
-; GCN-DAG: v_mov_b32_e32 v3, v1
-; GCN-DAG: v_mov_b32_e32 v2, v0
define amdgpu_kernel void @v_qsad_pk_u16_u8_non_immediate(ptr addrspace(1) %out, i64 %src, i32 %a, i64 %b) {
+; SI-SDAG-LABEL: v_qsad_pk_u16_u8_non_immediate:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xd
+; SI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xf
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; SI-SDAG-NEXT: ;;#ASMSTART
+; SI-SDAG-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; SI-SDAG-NEXT: ;;#ASMEND
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, s6
+; SI-SDAG-NEXT: ;;#ASMSTART
+; SI-SDAG-NEXT: v_mov_b32 v4, v0
+; SI-SDAG-NEXT: ;;#ASMEND
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, s4
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s5
+; SI-SDAG-NEXT: ;;#ASMSTART
+; SI-SDAG-NEXT: v_lshlrev_b64 v[6:7], v[0:1], 1
+; SI-SDAG-NEXT: ;;#ASMEND
+; SI-SDAG-NEXT: v_qsad_pk_u16_u8 v[0:1], v[2:3], v4, v[6:7]
+; SI-SDAG-NEXT: s_mov_b32 s6, -1
+; SI-SDAG-NEXT: s_mov_b32 s4, s0
+; SI-SDAG-NEXT: s_mov_b32 s5, s1
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, v1
+; SI-SDAG-NEXT: v_mov_b32_e32 v2, v0
+; SI-SDAG-NEXT: ;;#ASMSTART
+; SI-SDAG-NEXT: ;; force constraint
+; SI-SDAG-NEXT: ;;#ASMEND
+; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: v_qsad_pk_u16_u8_non_immediate:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-GISEL-NEXT: s_load_dword s6, s[4:5], 0xd
+; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xf
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, s6
+; SI-GISEL-NEXT: ;;#ASMSTART
+; SI-GISEL-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; SI-GISEL-NEXT: ;;#ASMEND
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; SI-GISEL-NEXT: ;;#ASMSTART
+; SI-GISEL-NEXT: v_mov_b32 v4, v4
+; SI-GISEL-NEXT: ;;#ASMEND
+; SI-GISEL-NEXT: ;;#ASMSTART
+; SI-GISEL-NEXT: v_lshlrev_b64 v[6:7], v[0:1], 1
+; SI-GISEL-NEXT: ;;#ASMEND
+; SI-GISEL-NEXT: v_qsad_pk_u16_u8 v[0:1], v[2:3], v4, v[6:7]
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, v0
+; SI-GISEL-NEXT: ;;#ASMSTART
+; SI-GISEL-NEXT: ;; force constraint
+; SI-GISEL-NEXT: ;;#ASMEND
+; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: v_qsad_pk_u16_u8_non_immediate:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-SDAG-NEXT: s_load_dword s6, s[4:5], 0x34
+; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x3c
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, s6
+; VI-SDAG-NEXT: ;;#ASMSTART
+; VI-SDAG-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; VI-SDAG-NEXT: ;;#ASMEND
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, s4
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s5
+; VI-SDAG-NEXT: ;;#ASMSTART
+; VI-SDAG-NEXT: v_mov_b32 v4, v4
+; VI-SDAG-NEXT: ;;#ASMEND
+; VI-SDAG-NEXT: ;;#ASMSTART
+; VI-SDAG-NEXT: v_lshlrev_b64 v[6:7], v[0:1], 1
+; VI-SDAG-NEXT: ;;#ASMEND
+; VI-SDAG-NEXT: v_qsad_pk_u16_u8 v[0:1], v[2:3], v4, v[6:7]
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, s0
+; VI-SDAG-NEXT: v_mov_b32_e32 v5, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, v1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, v0
+; VI-SDAG-NEXT: ;;#ASMSTART
+; VI-SDAG-NEXT: ;; force constraint
+; VI-SDAG-NEXT: ;;#ASMEND
+; VI-SDAG-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: v_qsad_pk_u16_u8_non_immediate:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-GISEL-NEXT: s_load_dword s6, s[4:5], 0x34
+; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x3c
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s6
+; VI-GISEL-NEXT: ;;#ASMSTART
+; VI-GISEL-NEXT: v_lsrlrev_b64 v[2:3], v[0:1], 1
+; VI-GISEL-NEXT: ;;#ASMEND
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; VI-GISEL-NEXT: ;;#ASMSTART
+; VI-GISEL-NEXT: v_mov_b32 v4, v4
+; VI-GISEL-NEXT: ;;#ASMEND
+; VI-GISEL-NEXT: ;;#ASMSTART
+; VI-GISEL-NEXT: v_lshlrev_b64 v[6:7], v[0:1], 1
+; VI-GISEL-NEXT: ;;#ASMEND
+; VI-GISEL-NEXT: v_qsad_pk_u16_u8 v[0:1], v[2:3], v4, v[6:7]
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, v0
+; VI-GISEL-NEXT: ;;#ASMSTART
+; VI-GISEL-NEXT: ;; force constraint
+; VI-GISEL-NEXT: ;;#ASMEND
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-GISEL-NEXT: s_endpgm
%tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0
%tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
%tmp2 = call i64 asm "v_lshlrev_b64 $0, $1, 1", "={v[6:7]},v"(i64 %b) #0
@@ -30,3 +243,6 @@ define amdgpu_kernel void @v_qsad_pk_u16_u8_non_immediate(ptr addrspace(1) %out,
}
attributes #0 = { nounwind readnone }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; SI: {{.*}}
+; VI: {{.*}}
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