[llvm] [CodeGen][AArch64] Use vector parts for internal non-power-of-two vectors (PR #213982)

[Hari Limaye via llvm-commits]

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@@ -1879,10 +1894,11 @@ class LLVM_ABI TargetLoweringBase {
   ///
   /// RegisterVT may be passed as a way to override the default settings, for
   /// instance with i128 inline assembly operands on SystemZ.
-  virtual unsigned
-  getNumRegisters(LLVMContext &Context, EVT VT,
-                  std::optional<MVT> RegisterVT = std::nullopt) const {
-    if (VT.isSimple()) {
+  virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT,
+                                   std::optional<MVT> RegisterVT = std::nullopt,
+                                   bool ForCallingConv = false) const {
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hazzlim wrote:

Refactored to use this *Impl approach. 

https://github.com/llvm/llvm-project/pull/213982