[llvm] [AArch64][GlobalISel] Match SelectionDAG lowering for vshll_n and vshll_high_n intrinsics (PR #214449)
Kieran B via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 7 08:32:17 PDT 2026
https://github.com/kieroxide updated https://github.com/llvm/llvm-project/pull/214449
>From 08f6e58c63369ce53f42a609df22cccabc76606d Mon Sep 17 00:00:00 2001
From: Kieran Bailey <kieran.bailey at arm.com>
Date: Thu, 6 Aug 2026 09:53:04 +0000
Subject: [PATCH 1/3] [AArch64][GlobalISel] Match SelectionDAG lowering for
vshll_n and vshll_high_n intrinsics
Currently, SelectionDAG lowers correctly for vshll_n and vshll_high_n but not in GlobalIsel. Add patterns for GlobalIsel to correctly lower to ACLE specified instruction for vshll_n and vshll_high_n.
The corresponding tests for C to IR are in arm_neon_instrinsics.c.
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 33 +++
llvm/test/CodeGen/AArch64/arm64-vshift.ll | 46 +---
.../CodeGen/AArch64/highextractbitcast.ll | 14 +-
.../CodeGen/AArch64/neon-shift-left-long.ll | 252 +++++-------------
llvm/test/CodeGen/AArch64/shuffles.ll | 14 +-
5 files changed, 127 insertions(+), 232 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 53c7af890b6e5..e7375fcb97751 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -9567,6 +9567,39 @@ def : Pat<(shl (v4i32 (sext (v4i16 V64:$Rm))), (v4i32 (AArch64dup (i32 imm32_0_1
def : Pat<(shl (v2i64 (sext (v2i32 V64:$Rm))), (v2i64 (AArch64dup (i64 imm0_31:$size)))),
(SSHLLv2i32_shift V64:$Rm, (trunc_imm imm0_31:$size))>;
+def : Pat<(shl (v8i16 (zext (extract_high_v16i8 (v16i8 V128:$Rn)))), (v8i16 (AArch64dup (i32 imm32_0_7:$size)))),
+ (USHLLv16i8_shift V128:$Rn, (i32 imm32_0_7:$size))>;
+def : Pat<(shl (v4i32 (zext (extract_high_v8i16 (v8i16 V128:$Rn)))), (v4i32 (AArch64dup (i32 imm32_0_15:$size)))),
+ (USHLLv8i16_shift V128:$Rn, (i32 imm32_0_15:$size))>;
+def : Pat<(shl (v2i64 (zext (extract_high_v4i32 (v4i32 V128:$Rn)))), (v2i64 (AArch64dup (i64 imm0_31:$size)))),
+ (USHLLv4i32_shift V128:$Rn, (trunc_imm imm0_31:$size))>;
+
+def : Pat<(shl (v8i16 (sext (extract_high_v16i8 (v16i8 V128:$Rn)))), (v8i16 (AArch64dup (i32 imm32_0_7:$size)))),
+ (SSHLLv16i8_shift V128:$Rn, (i32 imm32_0_7:$size))>;
+def : Pat<(shl (v4i32 (sext (extract_high_v8i16 (v8i16 V128:$Rn)))), (v4i32 (AArch64dup (i32 imm32_0_15:$size)))),
+ (SSHLLv8i16_shift V128:$Rn, (i32 imm32_0_15:$size))>;
+def : Pat<(shl (v2i64 (sext (extract_high_v4i32 (v4i32 V128:$Rn)))), (v2i64 (AArch64dup (i64 imm0_31:$size)))),
+ (SSHLLv4i32_shift V128:$Rn, (trunc_imm imm0_31:$size))>;
+
+multiclass WidenShiftLongPats<SDPatternOperator ext> {
+ def : Pat<(shl (v8i16 (ext (v8i8 V64:$Rm))), (v8i16 (AArch64dup (i32 8)))),
+ (SHLLv8i8 V64:$Rm)>;
+ def : Pat<(shl (v4i32 (ext (v4i16 V64:$Rm))), (v4i32 (AArch64dup (i32 16)))),
+ (SHLLv4i16 V64:$Rm)>;
+ def : Pat<(shl (v2i64 (ext (v2i32 V64:$Rm))), (v2i64 (AArch64dup (i64 32)))),
+ (SHLLv2i32 V64:$Rm)>;
+ def : Pat<(shl (v8i16 (ext (extract_high_v16i8 (v16i8 V128:$Rn)))), (v8i16 (AArch64dup (i32 8)))),
+ (SHLLv16i8 V128:$Rn)>;
+ def : Pat<(shl (v4i32 (ext (extract_high_v8i16 (v8i16 V128:$Rn)))), (v4i32 (AArch64dup (i32 16)))),
+ (SHLLv8i16 V128:$Rn)>;
+ def : Pat<(shl (v2i64 (ext (extract_high_v4i32 (v4i32 V128:$Rn)))), (v2i64 (AArch64dup (i64 32)))),
+ (SHLLv4i32 V128:$Rn)>;
+}
+
+defm : WidenShiftLongPats<zext>;
+defm : WidenShiftLongPats<sext>;
+defm : WidenShiftLongPats<anyext>;
+
// Vector sign and zero extensions are implemented with SSHLL and USSHLL.
// Anyexts are implemented as zexts.
def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
diff --git a/llvm/test/CodeGen/AArch64/arm64-vshift.ll b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
index 8d17836a2b761..7a196f585a78b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vshift.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
@@ -2252,8 +2252,7 @@ define <8 x i16> @ushll2_8h(ptr %A) nounwind {
; CHECK-GI-LABEL: ushll2_8h:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldr q0, [x0]
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #1
+; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #1
; CHECK-GI-NEXT: ret
%load1 = load <16 x i8>, ptr %A
%tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -2272,8 +2271,7 @@ define <4 x i32> @ushll2_4s(ptr %A) nounwind {
; CHECK-GI-LABEL: ushll2_4s:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldr q0, [x0]
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #1
+; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #1
; CHECK-GI-NEXT: ret
%load1 = load <8 x i16>, ptr %A
%tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -2292,8 +2290,7 @@ define <2 x i64> @ushll2_2d(ptr %A) nounwind {
; CHECK-GI-LABEL: ushll2_2d:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldr q0, [x0]
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #1
+; CHECK-GI-NEXT: ushll2 v0.2d, v0.4s, #1
; CHECK-GI-NEXT: ret
%load1 = load <4 x i32>, ptr %A
%tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -2892,8 +2889,7 @@ define <8 x i16> @sshll2_8h(ptr %A) nounwind {
; CHECK-GI-LABEL: sshll2_8h:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldr q0, [x0]
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #1
+; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #1
; CHECK-GI-NEXT: ret
%load1 = load <16 x i8>, ptr %A
%tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -2912,8 +2908,7 @@ define <4 x i32> @sshll2_4s(ptr %A) nounwind {
; CHECK-GI-LABEL: sshll2_4s:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldr q0, [x0]
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #1
+; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #1
; CHECK-GI-NEXT: ret
%load1 = load <8 x i16>, ptr %A
%tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -2932,8 +2927,7 @@ define <2 x i64> @sshll2_2d(ptr %A) nounwind {
; CHECK-GI-LABEL: sshll2_2d:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldr q0, [x0]
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #1
+; CHECK-GI-NEXT: sshll2 v0.2d, v0.4s, #1
; CHECK-GI-NEXT: ret
%load1 = load <4 x i32>, ptr %A
%tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -4119,32 +4113,20 @@ define <2 x i64> @shl_orr2d(ptr %A, ptr %B) nounwind {
}
define <8 x i16> @shll(<8 x i8> %in) {
-; CHECK-SD-LABEL: shll:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: shll v0.8h, v0.8b, #8
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: shll:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: shl v0.8h, v0.8h, #8
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: shll:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shll v0.8h, v0.8b, #8
+; CHECK-NEXT: ret
%ext = zext <8 x i8> %in to <8 x i16>
%res = shl <8 x i16> %ext, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
ret <8 x i16> %res
}
define <4 x i32> @shll_high(<8 x i16> %in) {
-; CHECK-SD-LABEL: shll_high:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: shll2 v0.4s, v0.8h, #16
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: shll_high:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0
-; CHECK-GI-NEXT: shl v0.4s, v0.4s, #16
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: shll_high:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shll2 v0.4s, v0.8h, #16
+; CHECK-NEXT: ret
%extract = shufflevector <8 x i16> %in, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%ext = zext <4 x i16> %extract to <4 x i32>
%res = shl <4 x i32> %ext, <i32 16, i32 16, i32 16, i32 16>
diff --git a/llvm/test/CodeGen/AArch64/highextractbitcast.ll b/llvm/test/CodeGen/AArch64/highextractbitcast.ll
index df5801b9af938..8d8a96c8819d1 100644
--- a/llvm/test/CodeGen/AArch64/highextractbitcast.ll
+++ b/llvm/test/CodeGen/AArch64/highextractbitcast.ll
@@ -596,10 +596,10 @@ define <8 x i16> @foov8i16(<16 x i8> %a1, <2 x i64> %b1) {
}
define <2 x i64> @hadd32_zext_asr(<16 x i8> %src1a) {
-; CHECK-LE-LABEL: hadd32_zext_asr:
-; CHECK-LE: // %bb.0:
-; CHECK-LE-NEXT: ushll2 v0.2d, v0.4s, #1
-; CHECK-LE-NEXT: ret
+; CHECK-LABEL: hadd32_zext_asr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll2 v0.2d, v0.4s, #1
+; CHECK-NEXT: ret
;
; CHECK-BE-LABEL: hadd32_zext_asr:
; CHECK-BE: // %bb.0:
@@ -608,12 +608,6 @@ define <2 x i64> @hadd32_zext_asr(<16 x i8> %src1a) {
; CHECK-BE-NEXT: ushll2 v0.2d, v0.4s, #1
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: ret
-;
-; CHECK-GI-LABEL: hadd32_zext_asr:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #1
-; CHECK-GI-NEXT: ret
%src1 = bitcast <16 x i8> %src1a to <4 x i32>
%s1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%zextsrc1 = zext <2 x i32> %s1 to <2 x i64>
diff --git a/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll b/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll
index 88e49950d0114..776283f1167af 100644
--- a/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll
+++ b/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll
@@ -13,16 +13,10 @@ define <8 x i16> @test_sshll_v8i8(<8 x i8> %a) {
}
define <8 x i16> @test_sshll_v8i8_eltsize(<8 x i8> %a) {
-; CHECK-SD-LABEL: test_sshll_v8i8_eltsize:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: shll v0.8h, v0.8b, #8
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_sshll_v8i8_eltsize:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: shl v0.8h, v0.8h, #8
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_sshll_v8i8_eltsize:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shll v0.8h, v0.8b, #8
+; CHECK-NEXT: ret
%1 = sext <8 x i8> %a to <8 x i16>
%tmp = shl <8 x i16> %1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
ret <8 x i16> %tmp
@@ -56,16 +50,10 @@ define <4 x i32> @test_sshll_v4i16(<4 x i16> %a) {
}
define <4 x i32> @test_sshll_v4i16_eltsize(<4 x i16> %a) {
-; CHECK-SD-LABEL: test_sshll_v4i16_eltsize:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_sshll_v4i16_eltsize:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #0
-; CHECK-GI-NEXT: shl v0.4s, v0.4s, #16
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_sshll_v4i16_eltsize:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-NEXT: ret
%1 = sext <4 x i16> %a to <4 x i32>
%tmp = shl <4 x i32> %1, <i32 16, i32 16, i32 16, i32 16>
ret <4 x i32> %tmp
@@ -99,16 +87,10 @@ define <2 x i64> @test_sshll_v2i32(<2 x i32> %a) {
}
define <2 x i64> @test_sshll_v2i32_eltsize(<2 x i32> %a) {
-; CHECK-SD-LABEL: test_sshll_v2i32_eltsize:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: shll v0.2d, v0.2s, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_sshll_v2i32_eltsize:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #0
-; CHECK-GI-NEXT: shl v0.2d, v0.2d, #32
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_sshll_v2i32_eltsize:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shll v0.2d, v0.2s, #32
+; CHECK-NEXT: ret
%1 = sext <2 x i32> %a to <2 x i64>
%tmp = shl <2 x i64> %1, <i64 32, i64 32>
ret <2 x i64> %tmp
@@ -142,16 +124,10 @@ define <8 x i16> @test_ushll_v8i8(<8 x i8> %a) {
}
define <8 x i16> @test_ushll_v8i8_eltsize(<8 x i8> %a) {
-; CHECK-SD-LABEL: test_ushll_v8i8_eltsize:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: shll v0.8h, v0.8b, #8
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_ushll_v8i8_eltsize:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: shl v0.8h, v0.8h, #8
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_ushll_v8i8_eltsize:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shll v0.8h, v0.8b, #8
+; CHECK-NEXT: ret
%1 = zext <8 x i8> %a to <8 x i16>
%tmp = shl <8 x i16> %1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
ret <8 x i16> %tmp
@@ -179,16 +155,10 @@ define <4 x i32> @test_ushll_v4i16(<4 x i16> %a) {
}
define <4 x i32> @test_ushll_v4i16_eltsize(<4 x i16> %a) {
-; CHECK-SD-LABEL: test_ushll_v4i16_eltsize:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_ushll_v4i16_eltsize:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-GI-NEXT: shl v0.4s, v0.4s, #16
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_ushll_v4i16_eltsize:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-NEXT: ret
%1 = zext <4 x i16> %a to <4 x i32>
%tmp = shl <4 x i32> %1, <i32 16, i32 16, i32 16, i32 16>
ret <4 x i32> %tmp
@@ -216,16 +186,10 @@ define <2 x i64> @test_ushll_v2i32(<2 x i32> %a) {
}
define <2 x i64> @test_ushll_v2i32_eltsize(<2 x i32> %a) {
-; CHECK-SD-LABEL: test_ushll_v2i32_eltsize:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: shll v0.2d, v0.2s, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_ushll_v2i32_eltsize:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0
-; CHECK-GI-NEXT: shl v0.2d, v0.2d, #32
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_ushll_v2i32_eltsize:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shll v0.2d, v0.2s, #32
+; CHECK-NEXT: ret
%1 = zext <2 x i32> %a to <2 x i64>
%tmp = shl <2 x i64> %1, <i64 32, i64 32>
ret <2 x i64> %tmp
@@ -243,16 +207,10 @@ define <2 x i64> @test_ushll_v2i32_big(<2 x i32> %a) {
}
define <8 x i16> @test_sshll2_v16i8(<16 x i8> %a) {
-; CHECK-SD-LABEL: test_sshll2_v16i8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sshll2 v0.8h, v0.16b, #3
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_sshll2_v16i8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #3
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_sshll2_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sshll2 v0.8h, v0.16b, #3
+; CHECK-NEXT: ret
%1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%2 = sext <8 x i8> %1 to <8 x i16>
%tmp = shl <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
@@ -260,16 +218,10 @@ define <8 x i16> @test_sshll2_v16i8(<16 x i8> %a) {
}
define <8 x i16> @test_sshll2_v16i8_eltsize(<16 x i8> %a) {
-; CHECK-SD-LABEL: test_sshll2_v16i8_eltsize:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: shll2 v0.8h, v0.16b, #8
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_sshll2_v16i8_eltsize:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #0
-; CHECK-GI-NEXT: shl v0.8h, v0.8h, #8
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_sshll2_v16i8_eltsize:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shll2 v0.8h, v0.16b, #8
+; CHECK-NEXT: ret
%1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%2 = sext <8 x i8> %1 to <8 x i16>
%tmp = shl <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
@@ -295,16 +247,10 @@ define <8 x i16> @test_sshll2_v16i8_big(<16 x i8> %a) {
}
define <4 x i32> @test_sshll2_v8i16(<8 x i16> %a) {
-; CHECK-SD-LABEL: test_sshll2_v8i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sshll2 v0.4s, v0.8h, #9
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_sshll2_v8i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #9
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_sshll2_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sshll2 v0.4s, v0.8h, #9
+; CHECK-NEXT: ret
%1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%2 = sext <4 x i16> %1 to <4 x i32>
%tmp = shl <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9>
@@ -312,16 +258,10 @@ define <4 x i32> @test_sshll2_v8i16(<8 x i16> %a) {
}
define <4 x i32> @test_sshll2_v8i16_eltsize(<8 x i16> %a) {
-; CHECK-SD-LABEL: test_sshll2_v8i16_eltsize:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: shll2 v0.4s, v0.8h, #16
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_sshll2_v8i16_eltsize:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0
-; CHECK-GI-NEXT: shl v0.4s, v0.4s, #16
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_sshll2_v8i16_eltsize:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shll2 v0.4s, v0.8h, #16
+; CHECK-NEXT: ret
%1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%2 = sext <4 x i16> %1 to <4 x i32>
%tmp = shl <4 x i32> %2, <i32 16, i32 16, i32 16, i32 16>
@@ -347,16 +287,10 @@ define <4 x i32> @test_sshll2_v8i16_big(<8 x i16> %a) {
}
define <2 x i64> @test_sshll2_v4i32(<4 x i32> %a) {
-; CHECK-SD-LABEL: test_sshll2_v4i32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sshll2 v0.2d, v0.4s, #19
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_sshll2_v4i32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #19
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_sshll2_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sshll2 v0.2d, v0.4s, #19
+; CHECK-NEXT: ret
%1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3>
%2 = sext <2 x i32> %1 to <2 x i64>
%tmp = shl <2 x i64> %2, <i64 19, i64 19>
@@ -364,16 +298,10 @@ define <2 x i64> @test_sshll2_v4i32(<4 x i32> %a) {
}
define <2 x i64> @test_sshll2_v4i32_eltsize(<4 x i32> %a) {
-; CHECK-SD-LABEL: test_sshll2_v4i32_eltsize:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: shll2 v0.2d, v0.4s, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_sshll2_v4i32_eltsize:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll2 v0.2d, v0.4s, #0
-; CHECK-GI-NEXT: shl v0.2d, v0.2d, #32
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_sshll2_v4i32_eltsize:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shll2 v0.2d, v0.4s, #32
+; CHECK-NEXT: ret
%1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3>
%2 = sext <2 x i32> %1 to <2 x i64>
%tmp = shl <2 x i64> %2, <i64 32, i64 32>
@@ -399,16 +327,10 @@ define <2 x i64> @test_sshll2_v4i32_big(<4 x i32> %a) {
}
define <8 x i16> @test_ushll2_v16i8(<16 x i8> %a) {
-; CHECK-SD-LABEL: test_ushll2_v16i8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ushll2 v0.8h, v0.16b, #3
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_ushll2_v16i8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #3
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_ushll2_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll2 v0.8h, v0.16b, #3
+; CHECK-NEXT: ret
%1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%2 = zext <8 x i8> %1 to <8 x i16>
%tmp = shl <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
@@ -416,16 +338,10 @@ define <8 x i16> @test_ushll2_v16i8(<16 x i8> %a) {
}
define <8 x i16> @test_ushll2_v16i8_eltsize(<16 x i8> %a) {
-; CHECK-SD-LABEL: test_ushll2_v16i8_eltsize:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: shll2 v0.8h, v0.16b, #8
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_ushll2_v16i8_eltsize:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0
-; CHECK-GI-NEXT: shl v0.8h, v0.8h, #8
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_ushll2_v16i8_eltsize:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shll2 v0.8h, v0.16b, #8
+; CHECK-NEXT: ret
%1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%2 = zext <8 x i8> %1 to <8 x i16>
%tmp = shl <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
@@ -446,16 +362,10 @@ define <8 x i16> @test_ushll2_v16i8_big(<16 x i8> %a) {
}
define <4 x i32> @test_ushll2_v8i16(<8 x i16> %a) {
-; CHECK-SD-LABEL: test_ushll2_v8i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ushll2 v0.4s, v0.8h, #9
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_ushll2_v8i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #9
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_ushll2_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll2 v0.4s, v0.8h, #9
+; CHECK-NEXT: ret
%1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%2 = zext <4 x i16> %1 to <4 x i32>
%tmp = shl <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9>
@@ -463,16 +373,10 @@ define <4 x i32> @test_ushll2_v8i16(<8 x i16> %a) {
}
define <4 x i32> @test_ushll2_v8i16_eltsize(<8 x i16> %a) {
-; CHECK-SD-LABEL: test_ushll2_v8i16_eltsize:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: shll2 v0.4s, v0.8h, #16
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_ushll2_v8i16_eltsize:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0
-; CHECK-GI-NEXT: shl v0.4s, v0.4s, #16
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_ushll2_v8i16_eltsize:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shll2 v0.4s, v0.8h, #16
+; CHECK-NEXT: ret
%1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%2 = zext <4 x i16> %1 to <4 x i32>
%tmp = shl <4 x i32> %2, <i32 16, i32 16, i32 16, i32 16>
@@ -492,16 +396,10 @@ define <4 x i32> @test_ushll2_v8i16_big(<8 x i16> %a) {
}
define <2 x i64> @test_ushll2_v4i32(<4 x i32> %a) {
-; CHECK-SD-LABEL: test_ushll2_v4i32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ushll2 v0.2d, v0.4s, #19
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_ushll2_v4i32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #19
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_ushll2_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll2 v0.2d, v0.4s, #19
+; CHECK-NEXT: ret
%1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3>
%2 = zext <2 x i32> %1 to <2 x i64>
%tmp = shl <2 x i64> %2, <i64 19, i64 19>
@@ -509,16 +407,10 @@ define <2 x i64> @test_ushll2_v4i32(<4 x i32> %a) {
}
define <2 x i64> @test_ushll2_v4i32_eltsize(<4 x i32> %a) {
-; CHECK-SD-LABEL: test_ushll2_v4i32_eltsize:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: shll2 v0.2d, v0.4s, #32
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_ushll2_v4i32_eltsize:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll2 v0.2d, v0.4s, #0
-; CHECK-GI-NEXT: shl v0.2d, v0.2d, #32
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_ushll2_v4i32_eltsize:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shll2 v0.2d, v0.4s, #32
+; CHECK-NEXT: ret
%1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3>
%2 = zext <2 x i32> %1 to <2 x i64>
%tmp = shl <2 x i64> %2, <i64 32, i64 32>
diff --git a/llvm/test/CodeGen/AArch64/shuffles.ll b/llvm/test/CodeGen/AArch64/shuffles.ll
index fec7cdfacba74..2debe1976ae5a 100644
--- a/llvm/test/CodeGen/AArch64/shuffles.ll
+++ b/llvm/test/CodeGen/AArch64/shuffles.ll
@@ -743,16 +743,10 @@ define <8 x half> @test_shuf15(<8 x half> %a, <8 x half> %b)
}
define <4 x i32> @extract_shuffle(<8 x i16> %j, <4 x i16> %k) {
-; CHECK-SD-LABEL: extract_shuffle:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ushll2 v0.4s, v0.8h, #3
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: extract_shuffle:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #3
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: extract_shuffle:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll2 v0.4s, v0.8h, #3
+; CHECK-NEXT: ret
;
; CHECKBE-LABEL: extract_shuffle:
; CHECKBE: // %bb.0:
>From a94f04032914804880c55199b69c578b44ecb817 Mon Sep 17 00:00:00 2001
From: Kieran Bailey <kieran.bailey at arm.com>
Date: Thu, 6 Aug 2026 16:22:24 +0000
Subject: [PATCH 2/3] Refactored the new and existing patterns into multiclass
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 55 +++++++++------------
1 file changed, 22 insertions(+), 33 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index e7375fcb97751..0adb4b1cc3c42 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -9553,35 +9553,25 @@ def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
(SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
V128:$Rn, vecshiftR32Narrow:$imm)>;
-def : Pat<(shl (v8i16 (zext (v8i8 V64:$Rm))), (v8i16 (AArch64dup (i32 imm32_0_7:$size)))),
- (USHLLv8i8_shift V64:$Rm, (i32 imm32_0_7:$size))>;
-def : Pat<(shl (v4i32 (zext (v4i16 V64:$Rm))), (v4i32 (AArch64dup (i32 imm32_0_15:$size)))),
- (USHLLv4i16_shift V64:$Rm, (i32 imm32_0_15:$size))>;
-def : Pat<(shl (v2i64 (zext (v2i32 V64:$Rm))), (v2i64 (AArch64dup (i64 imm0_31:$size)))),
- (USHLLv2i32_shift V64:$Rm, (trunc_imm imm0_31:$size))>;
-
-def : Pat<(shl (v8i16 (sext (v8i8 V64:$Rm))), (v8i16 (AArch64dup (i32 imm32_0_7:$size)))),
- (SSHLLv8i8_shift V64:$Rm, (i32 imm32_0_7:$size))>;
-def : Pat<(shl (v4i32 (sext (v4i16 V64:$Rm))), (v4i32 (AArch64dup (i32 imm32_0_15:$size)))),
- (SSHLLv4i16_shift V64:$Rm, (i32 imm32_0_15:$size))>;
-def : Pat<(shl (v2i64 (sext (v2i32 V64:$Rm))), (v2i64 (AArch64dup (i64 imm0_31:$size)))),
- (SSHLLv2i32_shift V64:$Rm, (trunc_imm imm0_31:$size))>;
-
-def : Pat<(shl (v8i16 (zext (extract_high_v16i8 (v16i8 V128:$Rn)))), (v8i16 (AArch64dup (i32 imm32_0_7:$size)))),
- (USHLLv16i8_shift V128:$Rn, (i32 imm32_0_7:$size))>;
-def : Pat<(shl (v4i32 (zext (extract_high_v8i16 (v8i16 V128:$Rn)))), (v4i32 (AArch64dup (i32 imm32_0_15:$size)))),
- (USHLLv8i16_shift V128:$Rn, (i32 imm32_0_15:$size))>;
-def : Pat<(shl (v2i64 (zext (extract_high_v4i32 (v4i32 V128:$Rn)))), (v2i64 (AArch64dup (i64 imm0_31:$size)))),
- (USHLLv4i32_shift V128:$Rn, (trunc_imm imm0_31:$size))>;
-
-def : Pat<(shl (v8i16 (sext (extract_high_v16i8 (v16i8 V128:$Rn)))), (v8i16 (AArch64dup (i32 imm32_0_7:$size)))),
- (SSHLLv16i8_shift V128:$Rn, (i32 imm32_0_7:$size))>;
-def : Pat<(shl (v4i32 (sext (extract_high_v8i16 (v8i16 V128:$Rn)))), (v4i32 (AArch64dup (i32 imm32_0_15:$size)))),
- (SSHLLv8i16_shift V128:$Rn, (i32 imm32_0_15:$size))>;
-def : Pat<(shl (v2i64 (sext (extract_high_v4i32 (v4i32 V128:$Rn)))), (v2i64 (AArch64dup (i64 imm0_31:$size)))),
- (SSHLLv4i32_shift V128:$Rn, (trunc_imm imm0_31:$size))>;
-
-multiclass WidenShiftLongPats<SDPatternOperator ext> {
+multiclass WidenShiftImmPats<string inst, SDPatternOperator ext> {
+ def : Pat<(shl (v8i16 (ext (v8i8 V64:$Rm))), (v8i16 (AArch64dup (i32 imm32_0_7:$size)))),
+ (!cast<Instruction>(inst#"v8i8_shift") V64:$Rm, (i32 imm32_0_7:$size))>;
+ def : Pat<(shl (v4i32 (ext (v4i16 V64:$Rm))), (v4i32 (AArch64dup (i32 imm32_0_15:$size)))),
+ (!cast<Instruction>(inst#"v4i16_shift") V64:$Rm, (i32 imm32_0_15:$size))>;
+ def : Pat<(shl (v2i64 (ext (v2i32 V64:$Rm))), (v2i64 (AArch64dup (i64 imm0_31:$size)))),
+ (!cast<Instruction>(inst#"v2i32_shift") V64:$Rm, (trunc_imm imm0_31:$size))>;
+
+ def : Pat<(shl (v8i16 (ext (extract_high_v16i8 (v16i8 V128:$Rn)))), (v8i16 (AArch64dup (i32 imm32_0_7:$size)))),
+ (!cast<Instruction>(inst#"v16i8_shift") V128:$Rn, (i32 imm32_0_7:$size))>;
+ def : Pat<(shl (v4i32 (ext (extract_high_v8i16 (v8i16 V128:$Rn)))), (v4i32 (AArch64dup (i32 imm32_0_15:$size)))),
+ (!cast<Instruction>(inst#"v8i16_shift") V128:$Rn, (i32 imm32_0_15:$size))>;
+ def : Pat<(shl (v2i64 (ext (extract_high_v4i32 (v4i32 V128:$Rn)))), (v2i64 (AArch64dup (i64 imm0_31:$size)))),
+ (!cast<Instruction>(inst#"v4i32_shift") V128:$Rn, (trunc_imm imm0_31:$size))>;
+}
+defm : WidenShiftImmPats<"SSHLL", sext>;
+defm : WidenShiftImmPats<"USHLL", zext>;
+
+multiclass WidenShiftFullWidthPats<SDPatternOperator ext> {
def : Pat<(shl (v8i16 (ext (v8i8 V64:$Rm))), (v8i16 (AArch64dup (i32 8)))),
(SHLLv8i8 V64:$Rm)>;
def : Pat<(shl (v4i32 (ext (v4i16 V64:$Rm))), (v4i32 (AArch64dup (i32 16)))),
@@ -9595,10 +9585,9 @@ multiclass WidenShiftLongPats<SDPatternOperator ext> {
def : Pat<(shl (v2i64 (ext (extract_high_v4i32 (v4i32 V128:$Rn)))), (v2i64 (AArch64dup (i64 32)))),
(SHLLv4i32 V128:$Rn)>;
}
-
-defm : WidenShiftLongPats<zext>;
-defm : WidenShiftLongPats<sext>;
-defm : WidenShiftLongPats<anyext>;
+defm : WidenShiftFullWidthPats<zext>;
+defm : WidenShiftFullWidthPats<sext>;
+defm : WidenShiftFullWidthPats<anyext>;
// Vector sign and zero extensions are implemented with SSHLL and USSHLL.
// Anyexts are implemented as zexts.
>From eeb78df121a5868008da0b849e8eb8cbd3349f68 Mon Sep 17 00:00:00 2001
From: Kieran Bailey <kieran.bailey at arm.com>
Date: Fri, 7 Aug 2026 15:27:29 +0000
Subject: [PATCH 3/3] Add anyext to WidenShiftImmPats
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 0adb4b1cc3c42..6ab14fe0d5add 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -9570,6 +9570,7 @@ multiclass WidenShiftImmPats<string inst, SDPatternOperator ext> {
}
defm : WidenShiftImmPats<"SSHLL", sext>;
defm : WidenShiftImmPats<"USHLL", zext>;
+defm : WidenShiftImmPats<"USHLL", anyext>;
multiclass WidenShiftFullWidthPats<SDPatternOperator ext> {
def : Pat<(shl (v8i16 (ext (v8i8 V64:$Rm))), (v8i16 (AArch64dup (i32 8)))),
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