[llvm] [X86] Optimize (a & 0xff) | ((b & 0xff) << 8) into high-byte register insertions (PR #214645)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp --diff_from_common_commit
``````````

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 796a4cd50..9a14086fb 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -5437,11 +5437,13 @@ bool X86DAGToDAGISel::tryMatchHRegisterInsert(SDNode *N) {
         LoBase = V.getOperand(0);
         return true;
       }
-    } else if (V.getOpcode() == ISD::ZERO_EXTEND && V.getOperand(0).getValueType() == MVT::i8) {
+    } else if (V.getOpcode() == ISD::ZERO_EXTEND &&
+               V.getOperand(0).getValueType() == MVT::i8) {
       ZeroExtendLo = false;
       LoBase = V;
       return true;
-    } else if (V.getOpcode() == ISD::ANY_EXTEND && V.getOperand(0).getValueType() == MVT::i8) {
+    } else if (V.getOpcode() == ISD::ANY_EXTEND &&
+               V.getOperand(0).getValueType() == MVT::i8) {
       ZeroExtendLo = true;
       LoBase = V.getOperand(0);
       return true;
@@ -5462,7 +5464,8 @@ bool X86DAGToDAGISel::tryMatchHRegisterInsert(SDNode *N) {
         if (Mask->getZExtValue() == 255)
           Src = Src.getOperand(0);
       }
-    } else if (Src.getOpcode() == ISD::ZERO_EXTEND || Src.getOpcode() == ISD::ANY_EXTEND) {
+    } else if (Src.getOpcode() == ISD::ZERO_EXTEND ||
+               Src.getOpcode() == ISD::ANY_EXTEND) {
       if (Src.getOperand(0).getValueType() == MVT::i8)
         Src = Src.getOperand(0);
     }
@@ -5483,7 +5486,8 @@ bool X86DAGToDAGISel::tryMatchHRegisterInsert(SDNode *N) {
   SDValue Sub8 = CurDAG->getTargetConstant(X86::sub_8bit, dl, MVT::i32);
 
   SDValue DestBase;
-  unsigned ABCDRegClass = (VT == MVT::i32) ? X86::GR32_ABCDRegClassID : X86::GR16_ABCDRegClassID;
+  unsigned ABCDRegClass =
+      (VT == MVT::i32) ? X86::GR32_ABCDRegClassID : X86::GR16_ABCDRegClassID;
   SDValue RC_ABCD = CurDAG->getTargetConstant(ABCDRegClass, dl, MVT::i32);
 
   if (ZeroExtendLo) {
@@ -5492,7 +5496,8 @@ bool X86DAGToDAGISel::tryMatchHRegisterInsert(SDNode *N) {
       LoExtr = LoBase;
     } else {
       LoExtr = SDValue(CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
-                                              MVT::i8, LoBase, Sub8), 0);
+                                              MVT::i8, LoBase, Sub8),
+                       0);
     }
     DestBase = SDValue(
         CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, LoExtr), 0);
@@ -5518,8 +5523,9 @@ bool X86DAGToDAGISel::tryMatchHRegisterInsert(SDNode *N) {
   if (HiBase.getValueType() == MVT::i8) {
     HiExtr1 = HiBase;
   } else {
-    HiExtr1 = SDValue(CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
-                                             dl, MVT::i8, HiBase, Sub8), 0);
+    HiExtr1 = SDValue(CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
+                                             MVT::i8, HiBase, Sub8),
+                      0);
   }
 
   SDValue Sub8Hi = CurDAG->getTargetConstant(X86::sub_8bit_hi, dl, MVT::i32);

``````````

</details>


https://github.com/llvm/llvm-project/pull/214645