[llvm] [PowerPC] Add PPC cost model support for partial reductions (PR #214760)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 7 07:48:20 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
Author: RolandF77
<details>
<summary>Changes</summary>
PPC has some multiply-add partial reduction instructions, for i8 and i16 elements. Provide cost info so the vectorizers can make use of them.
---
Patch is 181.17 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/214760.diff
4 Files Affected:
- (modified) llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp (+38)
- (modified) llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h (+1-3)
- (added) llvm/test/Transforms/LoopVectorize/PowerPC/cost-partial-red.ll (+157)
- (added) llvm/test/Transforms/LoopVectorize/PowerPC/partial-red.ll (+2003)
``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index b3a54fd4c1ef4..ea4539e08c672 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -1160,3 +1160,41 @@ PPCTTIImpl::getMemIntrinsicInstrCost(const MemIntrinsicCostAttributes &MICA,
Cost += 1; // need shift for length
return Cost;
}
+
+InstructionCost PPCTTIImpl::getPartialReductionCost(
+ unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
+ ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
+ TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
+ TTI::TargetCostKind CostKind,
+ std::optional<FastMathFlags> FMF) const {
+ InstructionCost Invalid = InstructionCost::getInvalid();
+
+ if (Opcode != Instruction::Add)
+ return Invalid;
+ if (BinOp && BinOp.value() != Instruction::Mul)
+ return Invalid;
+
+ EVT AccVT = TLI->getValueType(DL, AccumType, true);
+ if (AccVT != MVT::i32)
+ return Invalid;
+ if (InputTypeA != InputTypeB)
+ return Invalid;
+
+ Type *ATy = VectorType::get(InputTypeA, VF);
+ EVT AVT = TLI->getValueType(DL, ATy, true);
+ if (AVT != MVT::v16i8 && AVT != MVT::v8i16)
+ return Invalid;
+
+ // For v16i8 PPC has vmsumubm zext/zext and vmsummbm sext/zext
+ // For v8i16 PPC has vmsumuhm zext/zext and vmsumshm sext/sext
+ if (OpAExtend != TTI::PR_SignExtend && OpAExtend != TTI::PR_ZeroExtend)
+ return Invalid;
+ if (OpAExtend != OpBExtend) {
+ if (AVT != MVT::v16i8 || OpBExtend != TTI::PR_ZeroExtend)
+ return Invalid;
+ } else if (AVT == MVT::v16i8 && OpAExtend == TTI::PR_SignExtend) {
+ return Invalid;
+ }
+
+ return vectorCostAdjustmentFactor(Instruction::Add, ATy, nullptr);
+}
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
index c8ec1960b17dd..c4673cd2fe856 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
@@ -173,9 +173,7 @@ class PPCTTIImpl final : public BasicTTIImplBase<PPCTTIImpl> {
ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
TTI::TargetCostKind CostKind,
- std::optional<FastMathFlags> FMF) const override {
- return InstructionCost::getInvalid();
- }
+ std::optional<FastMathFlags> FMF) const override;
private:
// The following constant is used for estimating costs on power9.
diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/cost-partial-red.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/cost-partial-red.ll
new file mode 100644
index 0000000000000..e5e34da03dbef
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/PowerPC/cost-partial-red.ll
@@ -0,0 +1,157 @@
+; RUN: opt -vectorizer-maximize-bandwidth -mcpu=pwr8 -S -passes=loop-vectorize -disable-output -debug-only=loop-vectorize < %s 2>&1 | FileCheck --check-prefix=P8COST %s
+; RUN: opt -vectorizer-maximize-bandwidth -mcpu=pwr9 -S -passes=loop-vectorize -disable-output -debug-only=loop-vectorize < %s 2>&1 | FileCheck --check-prefix=P9COST %s
+; RUN: opt -vectorizer-maximize-bandwidth -mcpu=pwr10 -S -passes=loop-vectorize -disable-output -debug-only=loop-vectorize < %s 2>&1 | FileCheck --check-prefix=P8COST %s
+
+target datalayout = "e-m:e-Fn32-i64:64-i128:128-n32:64-S128-v256:256:256-v512:512:512"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+; Function Attrs: nofree norecurse nosync nounwind memory(argmem: read) uwtable
+define dso_local signext i32 @dotu8(ptr noundef readonly captures(none) %a, ptr noundef readonly captures(none) %b, i64 noundef %n) local_unnamed_addr {
+; P8COST,P9COST: LV: Checking a loop in 'dotu8'
+; P8COST: Cost of 1 for VF 16: EXPRESSION vp<%8> = ir<%sum.08> + partial.reduce.add (mul nuw nsw (ir<%1> zext to i32), (ir<%0> zext to i32))
+; P8COST: Cost for VF 16: 5 (Estimated cost per lane: 0.313)
+; P9COST: Cost of 2 for VF 16: EXPRESSION vp<%8> = ir<%sum.08> + partial.reduce.add (mul nuw nsw (ir<%1> zext to i32), (ir<%0> zext to i32))
+; P9COST: Cost for VF 16: 8 (Estimated cost per lane: 0.5)
+entry:
+ %cmp7 = icmp sgt i64 %n, 0
+ br i1 %cmp7, label %for.body.preheader, label %for.cond.cleanup
+
+for.body.preheader: ; preds = %entry
+ br label %for.body
+
+for.cond.cleanup.loopexit: ; preds = %for.body
+ %add.lcssa = phi i32 [ %add, %for.body ]
+ br label %for.cond.cleanup
+
+for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry
+ %sum.0.lcssa = phi i32 [ 0, %entry ], [ %add.lcssa, %for.cond.cleanup.loopexit ]
+ ret i32 %sum.0.lcssa
+
+for.body: ; preds = %for.body.preheader, %for.body
+ %i.09 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ]
+ %sum.08 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
+ %arrayidx = getelementptr inbounds nuw i8, ptr %a, i64 %i.09
+ %0 = load i8, ptr %arrayidx, align 1, !tbaa !8
+ %conv = zext i8 %0 to i32
+ %arrayidx1 = getelementptr inbounds nuw i8, ptr %b, i64 %i.09
+ %1 = load i8, ptr %arrayidx1, align 1, !tbaa !8
+ %conv2 = zext i8 %1 to i32
+ %mul = mul nuw nsw i32 %conv2, %conv
+ %add = add nuw nsw i32 %mul, %sum.08
+ %inc = add nuw nsw i64 %i.09, 1
+ %exitcond.not = icmp eq i64 %inc, %n
+ br i1 %exitcond.not, label %for.cond.cleanup.loopexit, label %for.body, !llvm.loop !9
+}
+
+; Function Attrs: nofree norecurse nosync nounwind memory(argmem: read) uwtable
+define dso_local signext i32 @dots8(ptr noundef readonly captures(none) %a, ptr noundef readonly captures(none) %b, i64 noundef %n) local_unnamed_addr {
+; P8COST,P9COST: LV: Checking a loop in 'dots8'
+; P8COST: Cost for VF 16: 26 (Estimated cost per lane: 1.63)
+; P9COST: Cost for VF 16: 36 (Estimated cost per lane: 2.25)
+entry:
+ %cmp7 = icmp sgt i64 %n, 0
+ br i1 %cmp7, label %for.body, label %for.cond.cleanup
+
+for.cond.cleanup: ; preds = %for.body, %entry
+ %sum.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
+ ret i32 %sum.0.lcssa
+
+for.body: ; preds = %entry, %for.body
+ %i.09 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
+ %sum.08 = phi i32 [ %add, %for.body ], [ 0, %entry ]
+ %arrayidx = getelementptr inbounds nuw i8, ptr %a, i64 %i.09
+ %0 = load i8, ptr %arrayidx, align 1, !tbaa !8
+ %conv = sext i8 %0 to i32
+ %arrayidx1 = getelementptr inbounds nuw i8, ptr %b, i64 %i.09
+ %1 = load i8, ptr %arrayidx1, align 1, !tbaa !8
+ %conv2 = sext i8 %1 to i32
+ %mul = mul nsw i32 %conv2, %conv
+ %add = add nsw i32 %mul, %sum.08
+ %inc = add nuw nsw i64 %i.09, 1
+ %exitcond.not = icmp eq i64 %inc, %n
+ br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !11
+}
+
+; Function Attrs: nofree norecurse nosync nounwind memory(argmem: read) uwtable
+define dso_local signext range(i32 0, -2147483648) i32 @dotu16(ptr noundef readonly captures(none) %a, ptr noundef readonly captures(none) %b, i64 noundef %n) local_unnamed_addr {
+; P8COST,P9COST: LV: Checking a loop in 'dotu16'
+; P8COST: Cost of 1 for VF 8: EXPRESSION vp<%8> = ir<%sum.08> + partial.reduce.add (mul nuw nsw (ir<%1> zext to i32), (ir<%0> zext to i32))
+; P8COST: Cost for VF 8: 5 (Estimated cost per lane: 0.625)
+; P9COST: Cost of 2 for VF 8: EXPRESSION vp<%8> = ir<%sum.08> + partial.reduce.add (mul nuw nsw (ir<%1> zext to i32), (ir<%0> zext to i32))
+; P9COST: Cost for VF 8: 8 (Estimated cost per lane: 1)
+entry:
+ %cmp7 = icmp sgt i64 %n, 0
+ br i1 %cmp7, label %for.body, label %for.cond.cleanup
+
+for.cond.cleanup: ; preds = %for.body, %entry
+ %sum.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
+ ret i32 %sum.0.lcssa
+
+for.body: ; preds = %entry, %for.body
+ %i.09 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
+ %sum.08 = phi i32 [ %add, %for.body ], [ 0, %entry ]
+ %arrayidx = getelementptr inbounds nuw [2 x i8], ptr %a, i64 %i.09
+ %0 = load i16, ptr %arrayidx, align 2, !tbaa !12
+ %conv = zext i16 %0 to i32
+ %arrayidx1 = getelementptr inbounds nuw [2 x i8], ptr %b, i64 %i.09
+ %1 = load i16, ptr %arrayidx1, align 2, !tbaa !12
+ %conv2 = zext i16 %1 to i32
+ %mul = mul nuw nsw i32 %conv2, %conv
+ %add = add nuw nsw i32 %mul, %sum.08
+ %inc = add nuw nsw i64 %i.09, 1
+ %exitcond.not = icmp eq i64 %inc, %n
+ br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !14
+}
+
+; Function Attrs: nofree norecurse nosync nounwind memory(argmem: read) uwtable
+define dso_local signext i32 @dots16(ptr noundef readonly captures(none) %a, ptr noundef readonly captures(none) %b, i64 noundef %n) local_unnamed_addr {
+; P8COST,P9COST: LV: Checking a loop in 'dots16'
+; P8COST: Cost of 1 for VF 8: EXPRESSION vp<%8> = ir<%sum.08> + partial.reduce.add (mul nsw (ir<%1> sext to i32), (ir<%0> sext to i32))
+; P8COST: Cost for VF 8: 5 (Estimated cost per lane: 0.625)
+; P9COST: Cost of 2 for VF 8: EXPRESSION vp<%8> = ir<%sum.08> + partial.reduce.add (mul nsw (ir<%1> sext to i32), (ir<%0> sext to i32))
+; P9COST: Cost for VF 8: 8 (Estimated cost per lane: 1)
+entry:
+ %cmp7 = icmp sgt i64 %n, 0
+ br i1 %cmp7, label %for.body, label %for.cond.cleanup
+
+for.cond.cleanup: ; preds = %for.body, %entry
+ %sum.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
+ ret i32 %sum.0.lcssa
+
+for.body: ; preds = %entry, %for.body
+ %i.09 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
+ %sum.08 = phi i32 [ %add, %for.body ], [ 0, %entry ]
+ %arrayidx = getelementptr inbounds nuw [2 x i8], ptr %a, i64 %i.09
+ %0 = load i16, ptr %arrayidx, align 2, !tbaa !12
+ %conv = sext i16 %0 to i32
+ %arrayidx1 = getelementptr inbounds nuw [2 x i8], ptr %b, i64 %i.09
+ %1 = load i16, ptr %arrayidx1, align 2, !tbaa !12
+ %conv2 = sext i16 %1 to i32
+ %mul = mul nsw i32 %conv2, %conv
+ %add = add nsw i32 %mul, %sum.08
+ %inc = add nuw nsw i64 %i.09, 1
+ %exitcond.not = icmp eq i64 %inc, %n
+ br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !15
+}
+
+!llvm.module.flags = !{!0, !1, !2}
+!llvm.ident = !{!3}
+!llvm.errno.tbaa = !{!4}
+
+!0 = !{i32 8, !"PIC Level", i32 2}
+!1 = !{i32 7, !"PIE Level", i32 2}
+!2 = !{i32 7, !"uwtable", i32 2}
+!3 = !{!"clang version 23.0.0git"}
+!4 = !{!5, !5, i64 0}
+!5 = !{!"int", !6, i64 0}
+!6 = !{!"omnipotent char", !7, i64 0}
+!7 = !{!"Simple C/C++ TBAA"}
+!8 = !{!6, !6, i64 0}
+!9 = distinct !{!9, !10}
+!10 = !{!"llvm.loop.mustprogress"}
+!11 = distinct !{!11, !10}
+!12 = !{!13, !13, i64 0}
+!13 = !{!"short", !6, i64 0}
+!14 = distinct !{!14, !10}
+!15 = distinct !{!15, !10}
+;.
diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/partial-red.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/partial-red.ll
new file mode 100644
index 0000000000000..b3922c056ba9d
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/PowerPC/partial-red.ll
@@ -0,0 +1,2003 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -vectorizer-maximize-bandwidth -mcpu=pwr8 -S -passes=loop-vectorize < %s | FileCheck --check-prefix=P8CHECK %s
+; RUN: opt -vectorizer-maximize-bandwidth -mcpu=pwr9 -S -passes=loop-vectorize < %s | FileCheck --check-prefix=P9CHECK %s
+; RUN: opt -vectorizer-maximize-bandwidth -mcpu=pwr10 -S -passes=loop-vectorize < %s | FileCheck --check-prefix=P10CHECK %s
+
+target datalayout = "e-m:e-Fn32-i64:64-i128:128-n32:64-S128-v256:256:256-v512:512:512"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+; Function Attrs: nofree norecurse nosync nounwind memory(argmem: read) uwtable
+define dso_local signext i32 @dotu8(ptr noundef readonly captures(none) %a, ptr noundef readonly captures(none) %b, i64 noundef %n) local_unnamed_addr {
+; P8CHECK-LABEL: define dso_local signext i32 @dotu8(
+; P8CHECK-SAME: ptr noundef readonly captures(none) [[A:%.*]], ptr noundef readonly captures(none) [[B:%.*]], i64 noundef [[N:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; P8CHECK-NEXT: [[ENTRY:.*]]:
+; P8CHECK-NEXT: [[CMP7:%.*]] = icmp sgt i64 [[N]], 0
+; P8CHECK-NEXT: br i1 [[CMP7]], label %[[ITER_CHECK:.*]], label %[[FOR_COND_CLEANUP:.*]]
+; P8CHECK: [[ITER_CHECK]]:
+; P8CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16
+; P8CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
+; P8CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
+; P8CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[N]], 128
+; P8CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
+; P8CHECK: [[VECTOR_PH]]:
+; P8CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 128
+; P8CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; P8CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; P8CHECK: [[VECTOR_BODY]]:
+; P8CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; P8CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
+; P8CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE24:%.*]], %[[VECTOR_BODY]] ]
+; P8CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE25:%.*]], %[[VECTOR_BODY]] ]
+; P8CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE26:%.*]], %[[VECTOR_BODY]] ]
+; P8CHECK-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE27:%.*]], %[[VECTOR_BODY]] ]
+; P8CHECK-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE28:%.*]], %[[VECTOR_BODY]] ]
+; P8CHECK-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE29:%.*]], %[[VECTOR_BODY]] ]
+; P8CHECK-NEXT: [[VEC_PHI8:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE30:%.*]], %[[VECTOR_BODY]] ]
+; P8CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw i8, ptr [[A]], i64 [[INDEX]]
+; P8CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 16
+; P8CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 32
+; P8CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 48
+; P8CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 64
+; P8CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 80
+; P8CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 96
+; P8CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 112
+; P8CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[TMP0]], align 1, !tbaa [[CHAR_TBAA8:![0-9]+]]
+; P8CHECK-NEXT: [[WIDE_LOAD9:%.*]] = load <16 x i8>, ptr [[TMP1]], align 1, !tbaa [[CHAR_TBAA8]]
+; P8CHECK-NEXT: [[WIDE_LOAD10:%.*]] = load <16 x i8>, ptr [[TMP2]], align 1, !tbaa [[CHAR_TBAA8]]
+; P8CHECK-NEXT: [[WIDE_LOAD11:%.*]] = load <16 x i8>, ptr [[TMP3]], align 1, !tbaa [[CHAR_TBAA8]]
+; P8CHECK-NEXT: [[WIDE_LOAD12:%.*]] = load <16 x i8>, ptr [[TMP4]], align 1, !tbaa [[CHAR_TBAA8]]
+; P8CHECK-NEXT: [[WIDE_LOAD13:%.*]] = load <16 x i8>, ptr [[TMP5]], align 1, !tbaa [[CHAR_TBAA8]]
+; P8CHECK-NEXT: [[WIDE_LOAD14:%.*]] = load <16 x i8>, ptr [[TMP6]], align 1, !tbaa [[CHAR_TBAA8]]
+; P8CHECK-NEXT: [[WIDE_LOAD15:%.*]] = load <16 x i8>, ptr [[TMP7]], align 1, !tbaa [[CHAR_TBAA8]]
+; P8CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw i8, ptr [[B]], i64 [[INDEX]]
+; P8CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP8]], i64 16
+; P8CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP8]], i64 32
+; P8CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP8]], i64 48
+; P8CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP8]], i64 64
+; P8CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP8]], i64 80
+; P8CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP8]], i64 96
+; P8CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP8]], i64 112
+; P8CHECK-NEXT: [[WIDE_LOAD16:%.*]] = load <16 x i8>, ptr [[TMP8]], align 1, !tbaa [[CHAR_TBAA8]]
+; P8CHECK-NEXT: [[WIDE_LOAD17:%.*]] = load <16 x i8>, ptr [[TMP9]], align 1, !tbaa [[CHAR_TBAA8]]
+; P8CHECK-NEXT: [[WIDE_LOAD18:%.*]] = load <16 x i8>, ptr [[TMP10]], align 1, !tbaa [[CHAR_TBAA8]]
+; P8CHECK-NEXT: [[WIDE_LOAD19:%.*]] = load <16 x i8>, ptr [[TMP11]], align 1, !tbaa [[CHAR_TBAA8]]
+; P8CHECK-NEXT: [[WIDE_LOAD20:%.*]] = load <16 x i8>, ptr [[TMP12]], align 1, !tbaa [[CHAR_TBAA8]]
+; P8CHECK-NEXT: [[WIDE_LOAD21:%.*]] = load <16 x i8>, ptr [[TMP13]], align 1, !tbaa [[CHAR_TBAA8]]
+; P8CHECK-NEXT: [[WIDE_LOAD22:%.*]] = load <16 x i8>, ptr [[TMP14]], align 1, !tbaa [[CHAR_TBAA8]]
+; P8CHECK-NEXT: [[WIDE_LOAD23:%.*]] = load <16 x i8>, ptr [[TMP15]], align 1, !tbaa [[CHAR_TBAA8]]
+; P8CHECK-NEXT: [[TMP16:%.*]] = zext <16 x i8> [[WIDE_LOAD16]] to <16 x i32>
+; P8CHECK-NEXT: [[TMP17:%.*]] = zext <16 x i8> [[WIDE_LOAD]] to <16 x i32>
+; P8CHECK-NEXT: [[TMP18:%.*]] = mul nuw nsw <16 x i32> [[TMP16]], [[TMP17]]
+; P8CHECK-NEXT: [[PARTIAL_REDUCE]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> [[VEC_PHI]], <16 x i32> [[TMP18]])
+; P8CHECK-NEXT: [[TMP19:%.*]] = zext <16 x i8> [[WIDE_LOAD17]] to <16 x i32>
+; P8CHECK-NEXT: [[TMP20:%.*]] = zext <16 x i8> [[WIDE_LOAD9]] to <16 x i32>
+; P8CHECK-NEXT: [[TMP21:%.*]] = mul nuw nsw <16 x i32> [[TMP19]], [[TMP20]]
+; P8CHECK-NEXT: [[PARTIAL_REDUCE24]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> [[VEC_PHI2]], <16 x i32> [[TMP21]])
+; P8CHECK-NEXT: [[TMP22:%.*]] = zext <16 x i8> [[WIDE_LOAD18]] to <16 x i32>
+; P8CHECK-NEXT: [[TMP23:%.*]] = zext <16 x i8> [[WIDE_LOAD10]] to <16 x i32>
+; P8CHECK-NEXT: [[TMP24:%.*]] = mul nuw nsw <16 x i32> [[TMP22]], [[TMP23]]
+; P8CHECK-NEXT: [[PARTIAL_REDUCE25]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> [[VEC_PHI3]], <16 x i32> [[TMP24]])
+; P8CHECK-NEXT: [[TMP25:%.*]] = zext <16 x i8> [[WIDE_LOAD19]] to <16 x i32>
+; P8CHECK-NEXT: [[TMP26:%.*]] = zext <16 x i8> [[WIDE_LOAD11]] to <16 x i32>
+; P8CHECK-NEXT: [[TMP27:%.*]] = mul nuw nsw <16 x i32> [[TMP25]], [[TMP26]]
+; P8CHECK-NEXT: [[PARTIAL_REDUCE26]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> [[VEC_PHI4]], <16 x i32> [[TMP27]])
+; P8CHECK-NEXT: [[TMP28:%.*]] = zext <16 x i8> [[WIDE_LOAD20]] to <16 x i32>
+; P8CHECK-NEXT: [[TMP29:%.*]] = zext <16 x i8> [[WIDE_LOAD12]] to <16 x i32>
+; P8CHECK-NEXT: [[TMP30:%.*]] = mul nuw nsw <16 x i32> [[TMP28]], [[TMP29]]
+; P8CHECK-NEXT: [[PARTIAL_REDUCE27]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> [[VEC_PHI5]], <16 x i32> [[TMP30]])
+; P8CHECK-NEXT: [[TMP31:%.*]] = zext <16 x i8> [[WIDE_LOAD21]] to <16 x i32>
+; P8CHECK-NEXT: [[TMP32:%.*]] = zext <16 x i8> [[WIDE_LOAD13]] to <16 x i32>
+; P8CHECK-NEXT: [[TMP33:%.*]] = mul nuw nsw <16 x i32> [[TMP31]], [[TMP32]]
+; P8CHECK-NEXT: [[PARTIAL_REDUCE28]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> [[VEC_PHI6]], <16 x i32> [[TMP33]])
+; P8CHECK-NEXT: [[TMP34:%.*]] = zext <16 x i8> [[WIDE_LOAD22]] to <16 x i32>
+; P8CHECK-NEXT: [[TMP35:%.*]] = zext <16 x i8> [[WIDE_LOAD14]] to <16 x i32>
+; P8CHECK-NEXT: [[TMP36:%.*]] = mul nuw nsw <16 x i32> [[TMP34]], [[TMP35]]
+; P8CHECK-NEXT: [[PARTIAL_REDUCE29]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> [[VEC_PHI7]], <16 x i32> [[TMP36]])
+; P8CHECK-NEXT: [[TMP37:%.*]] = zext <16 x i8> [[WIDE_LOAD23]] to <16 x i32>
+; P8CHECK-NEXT: [[TMP38:%.*]] = zext <16 x i8> [[WIDE_LOAD15]] to <16 x i32>
+; P8CHECK-NEXT: [[TMP39:%.*]] = mul nuw nsw <16 x i32> [[TMP37]], [[TMP38]]
+; P8CHECK-NEXT: [[PARTIAL_REDUCE30]] = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> [[...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/214760
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