[llvm] [AMDGPU] Add AGPR pressure tracking (PR #214745)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 7 07:46:56 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Romanov Vlad (romanovvlad)
<details>
<summary>Changes</summary>
Add AGPR pressure tacking in RPDelta.
---
Patch is 349.82 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/214745.diff
14 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp (+4-1)
- (modified) llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp (+54-17)
- (modified) llvm/lib/Target/AMDGPU/GCNSchedStrategy.h (+6-1)
- (modified) llvm/test/CodeGen/AMDGPU/agpr-csr.ll (+181-181)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-no-agprs-violations.ll (+1-1)
- (added) llvm/test/CodeGen/AMDGPU/coexec-sched-agpr-excess.mir (+71)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll (+480-467)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll (+45-60)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll (+556-697)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll (+887-867)
- (modified) llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll (+337-388)
- (modified) llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll (+120-112)
- (modified) llvm/test/CodeGen/AMDGPU/spill-agpr.ll (+69-72)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
index 726be8c7f0982..70fc4960f8ef1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
@@ -523,14 +523,17 @@ void AMDGPUCoExecSchedStrategy::pickNodeFromQueue(
ArrayRef<unsigned> Pressure = RPTracker.getRegSetPressureAtPos();
unsigned SGPRPressure = 0;
unsigned VGPRPressure = 0;
+ unsigned AGPRPressure = 0;
PickedPending = false;
if (DAG->isTrackingPressure()) {
if (!useGCNTrackers()) {
SGPRPressure = Pressure[AMDGPU::RegisterPressureSets::SReg_32];
VGPRPressure = Pressure[AMDGPU::RegisterPressureSets::VGPR_32];
+ AGPRPressure = Pressure[AMDGPU::RegisterPressureSets::AGPR_32];
} else {
SGPRPressure = DownwardTracker.getPressure().getSGPRNum();
VGPRPressure = DownwardTracker.getPressure().getArchVGPRNum();
+ AGPRPressure = DownwardTracker.getPressure().getAGPRNum();
}
}
@@ -538,7 +541,7 @@ void AMDGPUCoExecSchedStrategy::pickNodeFromQueue(
for (SUnit *SU : Q) {
SchedCandidate TryCand(ZonePolicy);
initCandidate(TryCand, SU, Zone.isTop(), RPTracker, SRI, SGPRPressure,
- VGPRPressure, IsBottomUp);
+ VGPRPressure, AGPRPressure, IsBottomUp);
SchedBoundary *ZoneArg = Cand.AtTop == TryCand.AtTop ? &Zone : nullptr;
tryCandidateCoexec(Cand, TryCand, ZoneArg);
if (TryCand.Reason != NoCand) {
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index 6cfdc8717ef64..3e11c0b2aeabd 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -151,6 +151,8 @@ void GCNSchedStrategy::initialize(ScheduleDAGMI *DAG) {
Context->RegClassInfo->getNumAllocatableRegs(&AMDGPU::SGPR_32RegClass);
VGPRExcessLimit =
Context->RegClassInfo->getNumAllocatableRegs(&AMDGPU::VGPR_32RegClass);
+ AGPRExcessLimit =
+ Context->RegClassInfo->getNumAllocatableRegs(&AMDGPU::AGPR_32RegClass);
SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
// Set the initial TargetOccupnacy to the maximum occupancy that we can
@@ -182,6 +184,10 @@ void GCNSchedStrategy::initialize(ScheduleDAGMI *DAG) {
VGPRBudget = std::max(VGPRBudget, Granule);
VGPRCriticalLimit = std::min(VGPRBudget, VGPRExcessLimit);
}
+
+ // Reuse VGPR critical limit
+ AGPRCriticalLimit = std::min(VGPRCriticalLimit, AGPRExcessLimit);
+
// Apply VGPR excess threshold percentage if specified.
if (VGPRThresholdPercentOpt > 0) {
[[maybe_unused]] unsigned OriginalVGPRExcessLimit = VGPRExcessLimit;
@@ -203,8 +209,14 @@ void GCNSchedStrategy::initialize(ScheduleDAGMI *DAG) {
// Subtract error margin and bias from register limits and avoid overflow.
SGPRCriticalLimit -= std::min(SGPRLimitBias + ErrorMargin, SGPRCriticalLimit);
SGPRExcessLimit -= std::min(SGPRLimitBias + ErrorMargin, SGPRExcessLimit);
+
+ AGPRExcessLimit -= std::min(VGPRLimitBias + ErrorMargin, AGPRExcessLimit);
+ AGPRCriticalLimit -= std::min(VGPRLimitBias + ErrorMargin, AGPRCriticalLimit);
+
LLVM_DEBUG(dbgs() << "VGPRCriticalLimit = " << VGPRCriticalLimit
<< ", VGPRExcessLimit = " << VGPRExcessLimit
+ << ", AGPRCriticalLimit = " << AGPRCriticalLimit
+ << ", AGPRExcessLimit = " << AGPRExcessLimit
<< ", SGPRCriticalLimit = " << SGPRCriticalLimit
<< ", SGPRExcessLimit = " << SGPRExcessLimit << "\n\n");
}
@@ -316,7 +328,8 @@ void GCNSchedStrategy::initCandidate(SchedCandidate &Cand, SUnit *SU,
const RegPressureTracker &RPTracker,
const SIRegisterInfo *SRI,
unsigned SGPRPressure,
- unsigned VGPRPressure, bool IsBottomUp) {
+ unsigned VGPRPressure,
+ unsigned AGPRPressure, bool IsBottomUp) {
Cand.SU = SU;
Cand.AtTop = AtTop;
@@ -345,6 +358,7 @@ void GCNSchedStrategy::initCandidate(SchedCandidate &Cand, SUnit *SU,
Pressure.resize(4, 0);
Pressure[AMDGPU::RegisterPressureSets::SReg_32] = SGPRPressure;
Pressure[AMDGPU::RegisterPressureSets::VGPR_32] = VGPRPressure;
+ Pressure[AMDGPU::RegisterPressureSets::AGPR_32] = AGPRPressure;
for (const auto &Diff : DAG->getPressureDiff(SU)) {
if (!Diff.isValid())
@@ -362,7 +376,9 @@ void GCNSchedStrategy::initCandidate(SchedCandidate &Cand, SUnit *SU,
if (Pressure[AMDGPU::RegisterPressureSets::SReg_32] !=
CheckPressure[AMDGPU::RegisterPressureSets::SReg_32] ||
Pressure[AMDGPU::RegisterPressureSets::VGPR_32] !=
- CheckPressure[AMDGPU::RegisterPressureSets::VGPR_32]) {
+ CheckPressure[AMDGPU::RegisterPressureSets::VGPR_32] ||
+ Pressure[AMDGPU::RegisterPressureSets::AGPR_32] !=
+ CheckPressure[AMDGPU::RegisterPressureSets::AGPR_32]) {
errs() << "Register Pressure is inaccurate when calculated through "
"PressureDiff\n"
<< "SGPR got " << Pressure[AMDGPU::RegisterPressureSets::SReg_32]
@@ -370,12 +386,16 @@ void GCNSchedStrategy::initCandidate(SchedCandidate &Cand, SUnit *SU,
<< CheckPressure[AMDGPU::RegisterPressureSets::SReg_32] << "\n"
<< "VGPR got " << Pressure[AMDGPU::RegisterPressureSets::VGPR_32]
<< ", expected "
- << CheckPressure[AMDGPU::RegisterPressureSets::VGPR_32] << "\n";
+ << CheckPressure[AMDGPU::RegisterPressureSets::VGPR_32] << "\n"
+ << "AGPR got " << Pressure[AMDGPU::RegisterPressureSets::AGPR_32]
+ << ", expected "
+ << CheckPressure[AMDGPU::RegisterPressureSets::AGPR_32] << "\n";
report_fatal_error("inaccurate register pressure calculation");
}
#endif
}
+ unsigned NewAGPRPressure = Pressure[AMDGPU::RegisterPressureSets::AGPR_32];
unsigned NewSGPRPressure = Pressure[AMDGPU::RegisterPressureSets::SReg_32];
unsigned NewVGPRPressure = Pressure[AMDGPU::RegisterPressureSets::VGPR_32];
@@ -384,18 +404,19 @@ void GCNSchedStrategy::initCandidate(SchedCandidate &Cand, SUnit *SU,
// instruction that increases the set with the least amount of registers,
// which in our case would be SGPRs. This is rarely what we want, so
// when we report excess/critical register pressure, we do it either
- // only for VGPRs or only for SGPRs.
+ // only for VGPRs, AGPRs or SGPRs. Priority: VGPR > AGPR > SGPR.
// FIXME: Better heuristics to determine whether to prefer SGPRs or VGPRs.
const unsigned MaxVGPRPressureInc = 16;
bool ShouldTrackVGPRs = VGPRPressure + MaxVGPRPressureInc >= VGPRExcessLimit;
- bool ShouldTrackSGPRs = !ShouldTrackVGPRs && SGPRPressure >= SGPRExcessLimit;
-
+ bool ShouldTrackAGPRs = AGPRExcessLimit > 0 && !ShouldTrackVGPRs &&
+ AGPRPressure + MaxVGPRPressureInc >= AGPRExcessLimit;
+ bool ShouldTrackSGPRs =
+ !ShouldTrackVGPRs && !ShouldTrackAGPRs && SGPRPressure >= SGPRExcessLimit;
// FIXME: We have to enter REG-EXCESS before we reach the actual threshold
// to increase the likelihood we don't go over the limits. We should improve
// the analysis to look through dependencies to find the path with the least
// register pressure.
-
// We only need to update the RPDelta for instructions that increase register
// pressure. Instructions that decrease or keep reg pressure the same will be
// marked as RegExcess in tryCandidate() when they are compared with
@@ -406,6 +427,12 @@ void GCNSchedStrategy::initCandidate(SchedCandidate &Cand, SUnit *SU,
Cand.RPDelta.Excess.setUnitInc(NewVGPRPressure - VGPRExcessLimit);
}
+ if (ShouldTrackAGPRs && NewAGPRPressure >= AGPRExcessLimit) {
+ HasHighPressure = true;
+ Cand.RPDelta.Excess = PressureChange(AMDGPU::RegisterPressureSets::AGPR_32);
+ Cand.RPDelta.Excess.setUnitInc(NewAGPRPressure - AGPRExcessLimit);
+ }
+
if (ShouldTrackSGPRs && NewSGPRPressure >= SGPRExcessLimit) {
HasHighPressure = true;
Cand.RPDelta.Excess = PressureChange(AMDGPU::RegisterPressureSets::SReg_32);
@@ -414,22 +441,29 @@ void GCNSchedStrategy::initCandidate(SchedCandidate &Cand, SUnit *SU,
// Register pressure is considered 'CRITICAL' if it is approaching a value
// that would reduce the wave occupancy for the execution unit. When
- // register pressure is 'CRITICAL', increasing SGPR and VGPR pressure both
- // has the same cost, so we don't need to prefer one over the other.
+ // register pressure is 'CRITICAL', increasing SGPR, VGPR, and AGPR
+ // pressure all has the same cost, so we pick the most critical type.
int SGPRDelta = NewSGPRPressure - SGPRCriticalLimit;
int VGPRDelta = NewVGPRPressure - VGPRCriticalLimit;
+ int AGPRDelta = AGPRExcessLimit > 0 ? NewAGPRPressure - AGPRCriticalLimit
+ : std::numeric_limits<int>::min();
- if (SGPRDelta >= 0 || VGPRDelta >= 0) {
+ if (SGPRDelta >= 0 || VGPRDelta >= 0 || AGPRDelta >= 0) {
HasHighPressure = true;
- if (SGPRDelta > VGPRDelta) {
- Cand.RPDelta.CriticalMax =
- PressureChange(AMDGPU::RegisterPressureSets::SReg_32);
- Cand.RPDelta.CriticalMax.setUnitInc(SGPRDelta);
- } else {
+ // Pick the most critical type.
+ if (VGPRDelta >= SGPRDelta && VGPRDelta >= AGPRDelta) {
Cand.RPDelta.CriticalMax =
PressureChange(AMDGPU::RegisterPressureSets::VGPR_32);
Cand.RPDelta.CriticalMax.setUnitInc(VGPRDelta);
+ } else if (AGPRDelta >= SGPRDelta) {
+ Cand.RPDelta.CriticalMax =
+ PressureChange(AMDGPU::RegisterPressureSets::AGPR_32);
+ Cand.RPDelta.CriticalMax.setUnitInc(AGPRDelta);
+ } else {
+ Cand.RPDelta.CriticalMax =
+ PressureChange(AMDGPU::RegisterPressureSets::SReg_32);
+ Cand.RPDelta.CriticalMax.setUnitInc(SGPRDelta);
}
}
}
@@ -479,17 +513,20 @@ void GCNSchedStrategy::pickNodeFromQueue(SchedBoundary &Zone,
ArrayRef<unsigned> Pressure = RPTracker.getRegSetPressureAtPos();
unsigned SGPRPressure = 0;
unsigned VGPRPressure = 0;
+ unsigned AGPRPressure = 0;
IsPending = false;
if (DAG->isTrackingPressure()) {
if (!useGCNTrackers()) {
SGPRPressure = Pressure[AMDGPU::RegisterPressureSets::SReg_32];
VGPRPressure = Pressure[AMDGPU::RegisterPressureSets::VGPR_32];
+ AGPRPressure = Pressure[AMDGPU::RegisterPressureSets::AGPR_32];
} else {
GCNRPTracker *T = IsBottomUp
? static_cast<GCNRPTracker *>(&UpwardTracker)
: static_cast<GCNRPTracker *>(&DownwardTracker);
SGPRPressure = T->getPressure().getSGPRNum();
VGPRPressure = T->getPressure().getArchVGPRNum();
+ AGPRPressure = T->getPressure().getAGPRNum();
}
}
LLVM_DEBUG(dbgs() << "Available Q:\n");
@@ -498,7 +535,7 @@ void GCNSchedStrategy::pickNodeFromQueue(SchedBoundary &Zone,
SchedCandidate TryCand(ZonePolicy);
initCandidate(TryCand, SU, Zone.isTop(), RPTracker, SRI, SGPRPressure,
- VGPRPressure, IsBottomUp);
+ VGPRPressure, AGPRPressure, IsBottomUp);
// Pass SchedBoundary only when comparing nodes from the same boundary.
SchedBoundary *ZoneArg = Cand.AtTop == TryCand.AtTop ? &Zone : nullptr;
tryCandidate(Cand, TryCand, ZoneArg);
@@ -522,7 +559,7 @@ void GCNSchedStrategy::pickNodeFromQueue(SchedBoundary &Zone,
SchedCandidate TryCand(ZonePolicy);
initCandidate(TryCand, SU, Zone.isTop(), RPTracker, SRI, SGPRPressure,
- VGPRPressure, IsBottomUp);
+ VGPRPressure, AGPRPressure, IsBottomUp);
// Pass SchedBoundary only when comparing nodes from the same boundary.
SchedBoundary *ZoneArg = Cand.AtTop == TryCand.AtTop ? &Zone : nullptr;
tryPendingCandidate(Cand, TryCand, ZoneArg);
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
index 2059f4e6479ff..29393d035cc8c 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
@@ -57,7 +57,8 @@ class GCNSchedStrategy : public GenericScheduler {
void initCandidate(SchedCandidate &Cand, SUnit *SU, bool AtTop,
const RegPressureTracker &RPTracker,
const SIRegisterInfo *SRI, unsigned SGPRPressure,
- unsigned VGPRPressure, bool IsBottomUp);
+ unsigned VGPRPressure, unsigned AGPRPressure,
+ bool IsBottomUp);
/// Estimate how many cycles \p SU must wait due to structural hazards at the
/// current boundary cycle. Returns zero when no stall is required.
@@ -92,6 +93,8 @@ class GCNSchedStrategy : public GenericScheduler {
unsigned VGPRExcessLimit;
+ unsigned AGPRExcessLimit;
+
unsigned TargetOccupancy;
MachineFunction *MF;
@@ -136,6 +139,8 @@ class GCNSchedStrategy : public GenericScheduler {
unsigned VGPRCriticalLimit;
+ unsigned AGPRCriticalLimit;
+
unsigned SGPRLimitBias = 0;
unsigned VGPRLimitBias = 0;
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-csr.ll b/llvm/test/CodeGen/AMDGPU/agpr-csr.ll
index 016ac4eeb8867..c0805565190fb 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-csr.ll
+++ b/llvm/test/CodeGen/AMDGPU/agpr-csr.ll
@@ -180,34 +180,34 @@ define amdgpu_kernel void @test_call_empty() #0 {
; GFX908-NEXT: ;;#ASMSTART
; GFX908-NEXT: ; def a[0:31]
; GFX908-NEXT: ;;#ASMEND
-; GFX908-NEXT: v_accvgpr_read_b32 v6, a3
-; GFX908-NEXT: v_accvgpr_read_b32 v5, a2
-; GFX908-NEXT: v_accvgpr_read_b32 v4, a1
-; GFX908-NEXT: v_accvgpr_read_b32 v3, a0
-; GFX908-NEXT: v_accvgpr_read_b32 v10, a7
-; GFX908-NEXT: v_accvgpr_read_b32 v9, a6
-; GFX908-NEXT: v_accvgpr_read_b32 v8, a5
-; GFX908-NEXT: v_accvgpr_read_b32 v7, a4
-; GFX908-NEXT: v_accvgpr_read_b32 v14, a11
-; GFX908-NEXT: v_accvgpr_read_b32 v13, a10
-; GFX908-NEXT: v_accvgpr_read_b32 v12, a9
-; GFX908-NEXT: v_accvgpr_read_b32 v11, a8
-; GFX908-NEXT: v_accvgpr_read_b32 v18, a15
-; GFX908-NEXT: v_accvgpr_read_b32 v17, a14
-; GFX908-NEXT: v_accvgpr_read_b32 v16, a13
-; GFX908-NEXT: v_accvgpr_read_b32 v15, a12
-; GFX908-NEXT: v_accvgpr_read_b32 v22, a19
-; GFX908-NEXT: v_accvgpr_read_b32 v21, a18
-; GFX908-NEXT: v_accvgpr_read_b32 v20, a17
-; GFX908-NEXT: v_accvgpr_read_b32 v19, a16
-; GFX908-NEXT: v_accvgpr_read_b32 v26, a23
-; GFX908-NEXT: v_accvgpr_read_b32 v25, a22
-; GFX908-NEXT: v_accvgpr_read_b32 v24, a21
-; GFX908-NEXT: v_accvgpr_read_b32 v23, a20
-; GFX908-NEXT: v_accvgpr_read_b32 v30, a27
-; GFX908-NEXT: v_accvgpr_read_b32 v29, a26
-; GFX908-NEXT: v_accvgpr_read_b32 v28, a25
-; GFX908-NEXT: v_accvgpr_read_b32 v27, a24
+; GFX908-NEXT: v_accvgpr_read_b32 v3, a3
+; GFX908-NEXT: v_accvgpr_read_b32 v7, a7
+; GFX908-NEXT: v_accvgpr_read_b32 v11, a11
+; GFX908-NEXT: v_accvgpr_read_b32 v15, a15
+; GFX908-NEXT: v_accvgpr_read_b32 v19, a19
+; GFX908-NEXT: v_accvgpr_read_b32 v23, a23
+; GFX908-NEXT: v_accvgpr_read_b32 v27, a27
+; GFX908-NEXT: v_accvgpr_read_b32 v2, a2
+; GFX908-NEXT: v_accvgpr_read_b32 v1, a1
+; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
+; GFX908-NEXT: v_accvgpr_read_b32 v6, a6
+; GFX908-NEXT: v_accvgpr_read_b32 v5, a5
+; GFX908-NEXT: v_accvgpr_read_b32 v4, a4
+; GFX908-NEXT: v_accvgpr_read_b32 v10, a10
+; GFX908-NEXT: v_accvgpr_read_b32 v9, a9
+; GFX908-NEXT: v_accvgpr_read_b32 v8, a8
+; GFX908-NEXT: v_accvgpr_read_b32 v14, a14
+; GFX908-NEXT: v_accvgpr_read_b32 v13, a13
+; GFX908-NEXT: v_accvgpr_read_b32 v12, a12
+; GFX908-NEXT: v_accvgpr_read_b32 v18, a18
+; GFX908-NEXT: v_accvgpr_read_b32 v17, a17
+; GFX908-NEXT: v_accvgpr_read_b32 v16, a16
+; GFX908-NEXT: v_accvgpr_read_b32 v22, a22
+; GFX908-NEXT: v_accvgpr_read_b32 v21, a21
+; GFX908-NEXT: v_accvgpr_read_b32 v20, a20
+; GFX908-NEXT: v_accvgpr_read_b32 v26, a26
+; GFX908-NEXT: v_accvgpr_read_b32 v25, a25
+; GFX908-NEXT: v_accvgpr_read_b32 v24, a24
; GFX908-NEXT: v_accvgpr_read_b32 v35, a31
; GFX908-NEXT: v_accvgpr_read_b32 v34, a30
; GFX908-NEXT: v_accvgpr_read_b32 v33, a29
@@ -216,19 +216,19 @@ define amdgpu_kernel void @test_call_empty() #0 {
; GFX908-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX908-NEXT: global_store_dwordx4 v[0:1], v[32:35], off
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: global_store_dwordx4 v[0:1], v[27:30], off
+; GFX908-NEXT: global_store_dwordx4 v[0:1], v[24:27], off
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: global_store_dwordx4 v[0:1], v[23:26], off
+; GFX908-NEXT: global_store_dwordx4 v[0:1], v[20:23], off
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: global_store_dwordx4 v[0:1], v[19:22], off
+; GFX908-NEXT: global_store_dwordx4 v[0:1], v[16:19], off
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: global_store_dwordx4 v[0:1], v[15:18], off
+; GFX908-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: global_store_dwordx4 v[0:1], v[11:14], off
+; GFX908-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: global_store_dwordx4 v[0:1], v[7:10], off
+; GFX908-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
+; GFX908-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: s_endpgm
bb:
@@ -315,34 +315,34 @@ define amdgpu_kernel void @test_call_areg4() #0 {
; GFX908-NEXT: ;;#ASMSTART
; GFX908-NEXT: ; def a[0:31]
; GFX908-NEXT: ;;#ASMEND
-; GFX908-NEXT: v_accvgpr_read_b32 v6, a3
-; GFX908-NEXT: v_accvgpr_read_b32 v5, a2
-; GFX908-NEXT: v_accvgpr_read_b32 v4, a1
-; GFX908-NEXT: v_accvgpr_read_b32 v3, a0
-; GFX908-NEXT: v_accvgpr_read_b32 v10, a7
-; GFX908-NEXT: v_accvgpr_read_b32 v9, a6
-; GFX908-NEXT: v_accvgpr_read_b32 v8, a5
-; GFX908-NEXT: v_accvgpr_read_b32 v7, a4
-; GFX908-NEXT: v_accvgpr_read_b32 v14, a11
-; GFX908-NEXT: v_accvgpr_read_b32 v13, a10
-; GFX908-NEXT: v_accvgpr_read_b32 v12, a9
-; GFX908-NEXT: v_accvgpr_read_b32 v11, a8
-; GFX908-NEXT: v_accvgpr_read_b32 v18, a15
-; GFX908-NEXT: v_accvgpr_read_b32 v17, a14
-; GFX908-NEXT: v_accvgpr_read_b32 v16, a13
-; GFX908-NEXT: v_accvgpr_read_b32 v15, a12
-; GFX908-NEXT: v_accvgpr_read_b32 v22, a19
-; GFX908-NEXT: v_accvgpr_read_b32 v21, a18
-; GFX908-NEXT: v_accvgpr_read_b32 v20, a17
-; GFX908-NEXT: v_accvgpr_read_b32 v19, a16
-; GFX908-NEXT: v_accvgpr_read_b32 v26, a23
-; GFX908-NEXT: v_accvgpr_read_b32 v25, a22
-; GFX908-NEXT: v_accvgpr_read_b32 v24, a21
-; GFX908-NEXT: v_accvgpr_read_b32 v23, a20
-; GFX908-NEXT: v_accvgpr_read_b32 v30, a27
-; GFX908-NEXT: v_accvgpr_read_b32 v29, a26
-; GFX908-NEXT: v_accvgpr_read_b32 v28, a25
-; GFX908-NEXT: v_accvgpr_read_b32 v27, a24
+; GFX908-NEXT: v_accvgpr_read_b32 v3, a3
+; GFX908-NEXT: v_accvgpr_read_b32 v7, a7
+; GFX908-NEXT: v_accvgpr_read_b32 v11, a11
+; GFX908-NEXT: v_accvgpr_read_b32 v15, a15
+; GFX908-NEXT: v_accvgpr_read_b32 v19, a19
+; GFX908-NEXT: v_accvgpr_read_b32 v23, a23
+; GFX908-NEXT: v_accvgpr_read_b32 v27, a27
+; GFX908-NEXT: v_accvgpr_read_b32 v2, a2
+; GFX908-NEXT: v_accvgpr_read_b32 v1, a1
+; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
+; GFX908-NEXT: v_accvgpr_read_b32 v6, a6
+; GFX908-NEXT: v_accvgpr_read_b32 v5, a5
+; GFX908-NEXT: v_accvgpr_read_b32 v4, a4
+; GFX908-NEXT: v_accvgpr_read_b32 v10, a10
+; GFX908-NEXT: v_accvgpr_read_b32 v9, a9
+; GFX908-NEXT: v_accvgpr_read_b32 v8, a8
+; GFX908-NEXT: v_accvgpr_read_b32 v14, a14
+; GFX908-NEXT: v_accvgpr_read_b32 v13, a13
+; GFX908-NEXT: v_accvgpr_read_b32 v12, a12
+; GFX908-NEXT: v_accvgpr_read_b32 v18, a18
+; GFX908-NEXT: v_accvgpr_read_b32 v17, a17
+; GFX908-NEXT: v_accvgpr_read_b32 v16, a16
+; GFX908-NEXT: v_accvgpr_read_b32 v22, a22
+; GFX908-NEXT: v_accvgpr_read_b32 v21, a21
+; GFX908-NEXT: v_accvgpr_read_b...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/214745
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