[llvm] [RISCV] Turn certain cases of masked.load into vp.load + vp.merge (PR #214350)

[Craig Topper via llvm-commits]

================
@@ -20657,6 +20658,104 @@ static SDValue performVP_STORECombine(SDNode *N, SelectionDAG &DAG,
       VPStore->isCompressingStore());
 }
 
+/// Given
+/// ```
+/// %b = splat %base
+/// %s = <0, 1, 2, 3, ...>
+/// %a = add nuw %b, %s
+/// %N = splat %n
+/// %m = icmp ult %a, %N
+/// %v = mask.load %p, %m, %passthru
+/// ```
+/// we can turn this use a vp.load + vp.merge instead to avoid
+/// emitting mask. The VL of these two vp operations would be
+/// `min(%n - min(%n, %base + %offset), numElements)`
+/// where %offset is the start value of `%s` and numElements is the
+/// fixed vector size.
+static SDValue performMaskedLoadToVPLoadCombine(SDNode *N, SelectionDAG &DAG) {
+  using namespace SDPatternMatch;
+  auto *MLoad = cast<MaskedLoadSDNode>(N);
+  EVT MaskVT = MLoad->getMask().getValueType();
+  assert(MaskVT.isVector());
+  if (!MaskVT.isFixedLengthVector())
+    return SDValue();
+  unsigned NumElements = MaskVT.getVectorNumElements();
+  SDLoc DL(N);
+
+  SDValue SetCCLHS, SetCCRHS;
+  ISD::CondCode CC;
+  if (!sd_match(MLoad->getMask(), m_SetCC(m_Value(SetCCLHS), m_Value(SetCCRHS),
+                                          m_CondCode(CC))) ||
+      !(ISD::isUnsignedIntSetCC(CC) || ISD::isSignedIntSetCC(CC)))
----------------
topperc wrote:

Is this trying to rule out FP compares? FP uses SETUGT/UGE for "unordered" so it doens't work.

https://github.com/llvm/llvm-project/pull/214350