[llvm] [AMDGPU] Reschedule loads in clauses to improve throughput (PR #102595)

[via llvm-commits]

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@@ -137,6 +142,143 @@ bool SIPostRABundler::canBundle(const MachineInstr &MI,
          !isDependentLoad(NextMI);
 }
 
+static Register getDef(MachineInstr &MI) {
+  assert(MI.getNumExplicitDefs() > 0);
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ruiling wrote:

Shouldn't we assert `(MI.getNumExplicitDefs()` is exactly `1`? given that we only handle the first def.

https://github.com/llvm/llvm-project/pull/102595