[llvm] 3bdbc63 - fix partial reduce sumla expression (#209294)

[via llvm-commits]

Author: robertvirany
Date: 2026-08-06T09:16:48Z
New Revision: 3bdbc635ce70699bb819bb877e31458bdee83934

URL: https://github.com/llvm/llvm-project/commit/3bdbc635ce70699bb819bb877e31458bdee83934
DIFF: https://github.com/llvm/llvm-project/commit/3bdbc635ce70699bb819bb877e31458bdee83934.diff

LOG: fix partial reduce sumla expression (#209294)

Fixes #209193.

`TargetLowering::expandPartialReduceMLA` handled UMLA, SMLA, and FMLA,
but fell through to `llvm_unreachable` when expanding
`PARTIAL_REDUCE_SUMLA`.

This handles SUMLA by sign-extending the signed LHS and zero-extending
the unsigned RHS before multiplication.

The first commit precommits a SelectionDAG unit test that reproduces the
assertion and verifies that expansion creates the expected extensions.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/unittests/CodeGen/SelectionDAGNodeConstructionTest.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 46e11ede878a1..323911153522d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -13884,6 +13884,10 @@ SDValue TargetLowering::expandPartialReduceMLA(SDNode *N,
   case ISD::PARTIAL_REDUCE_SMLA:
     ExtOpcLHS = ExtOpcRHS = ISD::SIGN_EXTEND;
     break;
+  case ISD::PARTIAL_REDUCE_SUMLA:
+    ExtOpcLHS = ISD::SIGN_EXTEND;
+    ExtOpcRHS = ISD::ZERO_EXTEND;
+    break;
   case ISD::PARTIAL_REDUCE_FMLA:
     ExtOpcLHS = ExtOpcRHS = ISD::FP_EXTEND;
     break;

diff  --git a/llvm/unittests/CodeGen/SelectionDAGNodeConstructionTest.cpp b/llvm/unittests/CodeGen/SelectionDAGNodeConstructionTest.cpp
index 0899b04bfddb8..2449ec2f676f9 100644
--- a/llvm/unittests/CodeGen/SelectionDAGNodeConstructionTest.cpp
+++ b/llvm/unittests/CodeGen/SelectionDAGNodeConstructionTest.cpp
@@ -357,3 +357,28 @@ TEST_F(SelectionDAGNodeConstructionTest, CTLS) {
   SDValue Ctlsi1 = DAG->getNode(ISD::CTLS, DL, MVT::i32, i1Op);
   EXPECT_TRUE(isNullConstant(Ctlsi1));
 }
+
+TEST_F(SelectionDAGNodeConstructionTest, ExpandPartialReduceSUMLA) {
+  SDLoc DL;
+  SDValue Acc = DAG->getCopyFromReg(DAG->getEntryNode(), DL,
+                                    Register::index2VirtReg(1), MVT::v4i32);
+  SDValue LHS = DAG->getCopyFromReg(DAG->getEntryNode(), DL,
+                                    Register::index2VirtReg(2), MVT::v16i8);
+  SDValue RHS = DAG->getCopyFromReg(DAG->getEntryNode(), DL,
+                                    Register::index2VirtReg(3), MVT::v16i8);
+  SDValue PartialReduce =
+      DAG->getNode(ISD::PARTIAL_REDUCE_SUMLA, DL, MVT::v4i32, Acc, LHS, RHS);
+
+  SDValue Expanded = DAG->getTargetLoweringInfo().expandPartialReduceMLA(
+      PartialReduce.getNode(), *DAG);
+
+  unsigned NumSignExtends = 0;
+  unsigned NumZeroExtends = 0;
+  for (SDNode &N : DAG->allnodes()) {
+    NumSignExtends += N.getOpcode() == ISD::SIGN_EXTEND;
+    NumZeroExtends += N.getOpcode() == ISD::ZERO_EXTEND;
+  }
+  EXPECT_TRUE(Expanded);
+  EXPECT_EQ(NumSignExtends, 1u);
+  EXPECT_EQ(NumZeroExtends, 1u);
+}