[llvm] [AMDGPU] Add custom lowering of llvm.convert.to.arbitrary.fp for FP8 (PR #213813)

[Matt Arsenault via llvm-commits]

================
@@ -11013,6 +11025,73 @@ SITargetLowering::LowerCONVERT_FROM_ARBITRARY_FP(SDValue Op,
   return SDValue();
 }
 
+SDValue SITargetLowering::lowerToFP8(SDValue Op, bool IsBF8,
+                                     SelectionDAG &DAG) const {
+  SDLoc SL(Op);
+  SDValue Src = Op.getOperand(0);
+  EVT ResVT = Op.getValueType();
+  bool IsF16 = Src.getValueType().getScalarType() == MVT::f16;
+  assert((!IsF16 || Subtarget->hasF16FP8ConversionInsts()) &&
+         "f16 -> fp8/bf8 conversion requires F16FP8ConversionInsts");
+
+  if (IsF16) {
+    unsigned Opc =
+        IsBF8 ? AMDGPUISD::CVT_PK_BF8_F16 : AMDGPUISD::CVT_PK_FP8_F16;
+    SDValue Bytes = DAG.getNode(Opc, SL, MVT::i16, Src);
+    return DAG.getNode(ISD::BITCAST, SL, ResVT, Bytes);
+  }
+
+  unsigned Opc = IsBF8 ? AMDGPUISD::CVT_PK_BF8_F32 : AMDGPUISD::CVT_PK_FP8_F32;
+  SDValue PoisonI32 = DAG.getPOISON(MVT::i32);
+  SDValue WordSel = DAG.getTargetConstant(0, SL, MVT::i1);
+
+  if (!ResVT.isVector()) {
+    // Convert one lane, the second is unused.
+    SDValue Packed = DAG.getNode(Opc, SL, MVT::i32, Src,
+                                 DAG.getPOISON(MVT::f32), PoisonI32, WordSel);
----------------
arsenm wrote:

the result is better, though this seems more like a downstream codegen problem. we probably should have something smarter to fold SGPR poison uses into uses 

https://github.com/llvm/llvm-project/pull/213813