[llvm] [AMDGPU][GlobalISel] Add BF16 widening to V2BF16 for packed instructions (PR #214370)

[Lukas Sommer via llvm-commits]

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@@ -2286,6 +2290,40 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
   verify(*ST.getInstrInfo());
 }
 
+bool AMDGPULegalizerInfo::legalizeScalarBF16ToPackedBF16Op(
+    MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const {
+  Register Dst = MI.getOperand(0).getReg();
+  LLT DstTy = MRI.getType(Dst);
+
+  // Only handle scalar bf16
+  if (DstTy != LLT::bfloat16())
+    return false;
+
+  unsigned Opc = MI.getOpcode();
+  LLT V2BF16 = LLT::fixed_vector(2, LLT::bfloat16());
+  Register UndefBF16 = B.buildUndef(LLT::bfloat16()).getReg(0);
+
+  // Widen all source operands to v2bf16
+  SmallVector<Register, 3> WideSrcs;
+  for (unsigned I = 1, E = MI.getNumOperands(); I < E; ++I) {
+    Register Src = MI.getOperand(I).getReg();
+    Register WideSrc = B.buildBuildVector(V2BF16, {Src, UndefBF16}).getReg(0);
+    WideSrcs.push_back(WideSrc);
+  }
+
+  // Build the wide operation
+  auto MIB = B.buildInstr(Opc).addDef(MRI.createGenericVirtualRegister(V2BF16));
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sommerlukas wrote:

I think this doesn't preserve the flags on the original instruction, e.g., fast-math flags.

https://github.com/llvm/llvm-project/pull/214370