[llvm] fix partial reduce sumla expression (PR #209294)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/209294

>From db836612e7a43b3880eae646a21c6ccae5b047a3 Mon Sep 17 00:00:00 2001
From: Robert Virany <robertvirany at gmail.com>
Date: Mon, 13 Jul 2026 14:01:35 -0600
Subject: [PATCH 1/2] [DAG] Precommit PARTIAL_REDUCE_SUMLA test

---
 .../SelectionDAGNodeConstructionTest.cpp      | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/llvm/unittests/CodeGen/SelectionDAGNodeConstructionTest.cpp b/llvm/unittests/CodeGen/SelectionDAGNodeConstructionTest.cpp
index 0899b04bfddb8..2449ec2f676f9 100644
--- a/llvm/unittests/CodeGen/SelectionDAGNodeConstructionTest.cpp
+++ b/llvm/unittests/CodeGen/SelectionDAGNodeConstructionTest.cpp
@@ -357,3 +357,28 @@ TEST_F(SelectionDAGNodeConstructionTest, CTLS) {
   SDValue Ctlsi1 = DAG->getNode(ISD::CTLS, DL, MVT::i32, i1Op);
   EXPECT_TRUE(isNullConstant(Ctlsi1));
 }
+
+TEST_F(SelectionDAGNodeConstructionTest, ExpandPartialReduceSUMLA) {
+  SDLoc DL;
+  SDValue Acc = DAG->getCopyFromReg(DAG->getEntryNode(), DL,
+                                    Register::index2VirtReg(1), MVT::v4i32);
+  SDValue LHS = DAG->getCopyFromReg(DAG->getEntryNode(), DL,
+                                    Register::index2VirtReg(2), MVT::v16i8);
+  SDValue RHS = DAG->getCopyFromReg(DAG->getEntryNode(), DL,
+                                    Register::index2VirtReg(3), MVT::v16i8);
+  SDValue PartialReduce =
+      DAG->getNode(ISD::PARTIAL_REDUCE_SUMLA, DL, MVT::v4i32, Acc, LHS, RHS);
+
+  SDValue Expanded = DAG->getTargetLoweringInfo().expandPartialReduceMLA(
+      PartialReduce.getNode(), *DAG);
+
+  unsigned NumSignExtends = 0;
+  unsigned NumZeroExtends = 0;
+  for (SDNode &N : DAG->allnodes()) {
+    NumSignExtends += N.getOpcode() == ISD::SIGN_EXTEND;
+    NumZeroExtends += N.getOpcode() == ISD::ZERO_EXTEND;
+  }
+  EXPECT_TRUE(Expanded);
+  EXPECT_EQ(NumSignExtends, 1u);
+  EXPECT_EQ(NumZeroExtends, 1u);
+}

>From c3dff81e7cf7fcfc0049f36583220affa04d4e19 Mon Sep 17 00:00:00 2001
From: Robert Virany <robertvirany at gmail.com>
Date: Mon, 13 Jul 2026 14:04:57 -0600
Subject: [PATCH 2/2] [DAG] Handle PARTIAL_REDUCE_SUMLA expansion

Expand the signed LHS with SIGN_EXTEND and the unsigned RHS with
ZERO_EXTEND, matching PARTIAL_REDUCE_SUMLA semantics.

Fixes #209193.
---
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index bca34c5c347ee..e0a74c7cd7cc3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -13828,6 +13828,10 @@ SDValue TargetLowering::expandPartialReduceMLA(SDNode *N,
   case ISD::PARTIAL_REDUCE_SMLA:
     ExtOpcLHS = ExtOpcRHS = ISD::SIGN_EXTEND;
     break;
+  case ISD::PARTIAL_REDUCE_SUMLA:
+    ExtOpcLHS = ISD::SIGN_EXTEND;
+    ExtOpcRHS = ISD::ZERO_EXTEND;
+    break;
   case ISD::PARTIAL_REDUCE_FMLA:
     ExtOpcLHS = ExtOpcRHS = ISD::FP_EXTEND;
     break;