[llvm] 4395e6a - [AMDGPU] Add `isConvergent=1` to `DS_ATOMIC_*_BARRIER` instructions (#214166)

[via llvm-commits]

Author: Pierre van Houtryve
Date: 2026-08-06T10:19:51+02:00
New Revision: 4395e6ad2c876e2098adcc724f36e937b8f007fd

URL: https://github.com/llvm/llvm-project/commit/4395e6ad2c876e2098adcc724f36e937b8f007fd
DIFF: https://github.com/llvm/llvm-project/commit/4395e6ad2c876e2098adcc724f36e937b8f007fd.diff

LOG: [AMDGPU] Add `isConvergent=1` to `DS_ATOMIC_*_BARRIER` instructions (#214166)

The intrinsic already has it. The instructions may issue a wake-up
signal on barrier completion so the set of waves that execute the
instruction
may not change.

The test case shows taildup duplicating the MachineInstrs when
`isConvergent=0`.

Assisted-By: Claude Opus 4.8
Claude found the reproducer for me after I found the lack of
`isConvergent=1` on those
instructions.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/DSInstructions.td
    llvm/test/CodeGen/AMDGPU/ds-atomic-barrier-convergent.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 204cd89d4aefb..90713dfc1de7b 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -900,21 +900,25 @@ defm DS_LOAD_TR16_B128 : DS_1A_RET_NoM0<"ds_load_tr16_b128", VGPROp_128>;
 } // End WaveSizePredicate = isWave32, mayStore = 0
 
 let OtherPredicates = [HasLdsBarrierArriveAtomic] in {
-let ASYNC_CNT = 1, LGKM_CNT = 0, Uses = [EXEC, ASYNCcnt], Defs = [ASYNCcnt] in {
-def DS_ATOMIC_ASYNC_BARRIER_ARRIVE_B64 : DS_1A_Off16_NORET<"ds_atomic_async_barrier_arrive_b64">;
-}
+  let isConvergent = 1 in {
+    let ASYNC_CNT = 1, LGKM_CNT = 0, Uses = [EXEC, ASYNCcnt], Defs = [ASYNCcnt] in {
+      def DS_ATOMIC_ASYNC_BARRIER_ARRIVE_B64 : DS_1A_Off16_NORET<"ds_atomic_async_barrier_arrive_b64">;
+    }
 
-def : GCNPat <
-  (int_amdgcn_ds_atomic_async_barrier_arrive_b64 (DS1Addr1Offset i32:$ptr, i32:$offset)),
-  (DS_ATOMIC_ASYNC_BARRIER_ARRIVE_B64 VGPROp_32:$ptr, Offset:$offset, (i1 0))
->;
+    defm DS_ATOMIC_BARRIER_ARRIVE_RTN_B64 : DS_1A1D_RET_mc_gfx9<"ds_atomic_barrier_arrive_rtn_b64", VGPROp_64>;
+  } // End isConvergent = 1
 
-defm DS_ATOMIC_BARRIER_ARRIVE_RTN_B64 : DS_1A1D_RET_mc_gfx9<"ds_atomic_barrier_arrive_rtn_b64", VGPROp_64>;
+  def : GCNPat <
+    (int_amdgcn_ds_atomic_async_barrier_arrive_b64 (DS1Addr1Offset i32:$ptr, i32:$offset)),
+    (DS_ATOMIC_ASYNC_BARRIER_ARRIVE_B64 VGPROp_32:$ptr, Offset:$offset, (i1 0))
+  >;
 
-def : GCNPat<
-  (i64 (int_amdgcn_ds_atomic_barrier_arrive_rtn_b64 (DS1Addr1Offset i32:$ptr, i32:$offset), i64:$data)),
-  (DS_ATOMIC_BARRIER_ARRIVE_RTN_B64 $ptr, $data, Offset:$offset, (i1 0))
->;
+
+
+  def : GCNPat<
+    (i64 (int_amdgcn_ds_atomic_barrier_arrive_rtn_b64 (DS1Addr1Offset i32:$ptr, i32:$offset), i64:$data)),
+    (DS_ATOMIC_BARRIER_ARRIVE_RTN_B64 $ptr, $data, Offset:$offset, (i1 0))
+  >;
 } // End OtherPredicates = [HasLdsBarrierArriveAtomic]
 
 } // End SubtargetPredicate = isGFX1250Plus

diff  --git a/llvm/test/CodeGen/AMDGPU/ds-atomic-barrier-convergent.ll b/llvm/test/CodeGen/AMDGPU/ds-atomic-barrier-convergent.ll
index 417095ca69fd5..c42d8b4c9cc14 100644
--- a/llvm/test/CodeGen/AMDGPU/ds-atomic-barrier-convergent.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds-atomic-barrier-convergent.ll
@@ -18,25 +18,18 @@ define void @taildup_ds_atomic_barrier_arrive(ptr addrspace(1) %a, ptr addrspace
 ; GCN-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GCN-NEXT:    v_cmpx_ne_u32_e32 1, v3
 ; GCN-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GCN-NEXT:    s_cbranch_execnz .LBB0_3
-; GCN-NEXT:  ; %bb.1: ; %Flow
-; GCN-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GCN-NEXT:    s_cbranch_execnz .LBB0_4
-; GCN-NEXT:  .LBB0_2: ; %call
-; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GCN-NEXT:    ds_atomic_barrier_arrive_rtn_b64 v[2:3], v2, v[6:7]
-; GCN-NEXT:    s_wait_dscnt 0x0
-; GCN-NEXT:    global_store_b64 v[0:1], v[2:3], off
-; GCN-NEXT:    s_set_pc_i64 s[30:31]
-; GCN-NEXT:  .LBB0_3: ; %bb2
+; GCN-NEXT:    s_cbranch_execz .LBB0_2
+; GCN-NEXT:  ; %bb.1: ; %bb2
 ; GCN-NEXT:    v_mov_b32_e32 v3, 1
 ; GCN-NEXT:    global_store_b32 v[0:1], v3, off
+; GCN-NEXT:  .LBB0_2: ; %Flow
 ; GCN-NEXT:    s_wait_xcnt 0x0
 ; GCN-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GCN-NEXT:    s_cbranch_execz .LBB0_2
-; GCN-NEXT:  .LBB0_4: ; %bb1
+; GCN-NEXT:    s_cbranch_execz .LBB0_4
+; GCN-NEXT:  ; %bb.3: ; %bb1
 ; GCN-NEXT:    v_mov_b32_e32 v3, 0
 ; GCN-NEXT:    global_store_b32 v[0:1], v3, off
+; GCN-NEXT:  .LBB0_4: ; %call
 ; GCN-NEXT:    s_wait_xcnt 0x0
 ; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GCN-NEXT:    ds_atomic_barrier_arrive_rtn_b64 v[2:3], v2, v[6:7]
@@ -74,26 +67,19 @@ define void @taildup_ds_atomic_async_barrier_arrive(ptr addrspace(1) %a, ptr add
 ; GCN-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GCN-NEXT:    v_cmpx_ne_u32_e32 1, v3
 ; GCN-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GCN-NEXT:    s_cbranch_execnz .LBB1_3
-; GCN-NEXT:  ; %bb.1: ; %Flow
-; GCN-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GCN-NEXT:    s_cbranch_execnz .LBB1_4
-; GCN-NEXT:  .LBB1_2: ; %call
-; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GCN-NEXT:    s_wait_alu depctr_vm_vsrc(0)
-; GCN-NEXT:    ds_atomic_async_barrier_arrive_b64 v2
-; GCN-NEXT:    s_wait_alu depctr_vm_vsrc(0)
-; GCN-NEXT:    s_set_pc_i64 s[30:31]
-; GCN-NEXT:  .LBB1_3: ; %bb2
+; GCN-NEXT:    s_cbranch_execz .LBB1_2
+; GCN-NEXT:  ; %bb.1: ; %bb2
 ; GCN-NEXT:    v_mov_b32_e32 v3, 1
 ; GCN-NEXT:    global_store_b32 v[0:1], v3, off
 ; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; GCN-NEXT:  .LBB1_2: ; %Flow
 ; GCN-NEXT:    s_wait_xcnt 0x0
 ; GCN-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GCN-NEXT:    s_cbranch_execz .LBB1_2
-; GCN-NEXT:  .LBB1_4: ; %bb1
+; GCN-NEXT:    s_cbranch_execz .LBB1_4
+; GCN-NEXT:  ; %bb.3: ; %bb1
 ; GCN-NEXT:    v_mov_b32_e32 v3, 0
 ; GCN-NEXT:    global_store_b32 v[0:1], v3, off
+; GCN-NEXT:  .LBB1_4: ; %call
 ; GCN-NEXT:    s_wait_xcnt 0x0
 ; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GCN-NEXT:    s_wait_alu depctr_vm_vsrc(0)