[llvm] [SPIR-V] Set MIB insert point before widened type lookup in widenSignSensitiveOps (PR #214424)

[Arseniy Obolenskiy via llvm-commits]

https://github.com/aobolensk created https://github.com/llvm/llvm-project/pull/214424

Fix an assertion crash (release: null-MBB walk) when a sub-pow2 sign-sensitive op has no preceding G_TRUNC to set the insert point

>From 7586cc239a4e033074241158c5f1cd9e6cbc3d4e Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Thu, 6 Aug 2026 09:47:58 +0200
Subject: [PATCH] [SPIR-V] Set MIB insert point before widened type lookup in
 widenSignSensitiveOps

Fix an assertion crash (release: null-MBB walk) when a sub-pow2 sign-sensitive op has no preceding G_TRUNC to set the insert point
---
 llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp   |  2 +-
 .../SPIRV/legalization/signed-narrow-int.ll   | 20 +++++++++++++++++++
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 0a6a277f01bd9..2c77b23f2f5da 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -573,12 +573,12 @@ static void widenSignSensitiveOps(MachineFunction &MF, SPIRVGlobalRegistry *GR,
                            MachineInstr &MI) -> Register {
     unsigned NewW = widenBitWidthToNextPow2(OldW);
     LLT NewLLT = LLT::scalar(NewW);
+    MIB.setInsertPt(*MI.getParent(), MI.getIterator());
     SPIRVTypeInst SpvTy = GR->getOrCreateSPIRVIntegerType(NewW, MIB);
     Register SExted = MRI.createGenericVirtualRegister(NewLLT);
     GR->assignSPIRVTypeToVReg(SpvTy, SExted, MF);
     MRI.setRegClass(SExted, GR->getRegClass(SpvTy));
     MRI.setType(Reg, NewLLT);
-    MIB.setInsertPt(*MI.getParent(), MI.getIterator());
     MIB.buildSExtInReg(SExted, Reg, OldW);
     return SExted;
   };
diff --git a/llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll b/llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll
index 3ac752f9b8d9d..c2d9974939c21 100644
--- a/llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll
+++ b/llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll
@@ -250,6 +250,26 @@ define spir_kernel void @trunc_i8_to_i4_icmp_slt(i8 %a, i8 %b, ptr addrspace(1)
   ret void
 }
 
+; ----------------------------------------------------------------------------
+; CHECK: OpFunction
+; CHECK: %[[#GA:]] = OpLoad %[[#I32]]
+; CHECK: %[[#GB:]] = OpLoad %[[#I32]]
+; CHECK: %[[#SHLA8:]] = OpShiftLeftLogical %[[#I32]] %[[#GA]] %[[#K8]]
+; CHECK: %[[#SXA8:]] = OpShiftRightArithmetic %[[#I32]] %[[#SHLA8]] %[[#K8]]
+; CHECK: %[[#SHLB8:]] = OpShiftLeftLogical %[[#I32]] %[[#GB]] %[[#K8]]
+; CHECK: %[[#SXB8:]] = OpShiftRightArithmetic %[[#I32]] %[[#SHLB8]] %[[#K8]]
+; CHECK: OpSDiv %[[#I32]] %[[#SXA8]] %[[#SXB8]]
+ at ga = global i24 0
+ at gb = global i24 0
+ at out24 = global i24 0
+define spir_kernel void @sdiv_i24_from_globals() {
+  %a = load i24, ptr @ga
+  %b = load i24, ptr @gb
+  %r = sdiv i24 %a, %b
+  store i24 %r, ptr @out24
+  ret void
+}
+
 ; ----------------------------------------------------------------------------
 ; Negative test: unsigned compare must NOT emit sign-extension shifts.
 ; CHECK: OpFunction