[llvm] [RISCV] Teach the VL Optimizer about Zvzip instructions (PR #214405)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 5 23:31:06 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Pengcheng Wang (wangpc-pp)
<details>
<summary>Changes</summary>
Set ElementsDependOn = EltDepsNone on the five Zvzip instructions
(VZIP_VV, VUNZIPE_V, VUNZIPO_V, VPAIRE_VV, VPAIRO_VV) so the pass no
longer conservatively treats their result elements as depending on VL
and Mask (beyond masking of inactive lanes).
Wire the opcodes into the VL Optimizer's operand model:
- getOperandLog2EEW: all five instructions return MILog2SEW (source
and destination EEW both equal SEW).
- getOperandInfo: for VZIP_VV, widen the destination and passthru
EMUL by 2x since it interleaves two LMUL inputs into one 2xLMUL
result. For VUNZIPE_V / VUNZIPO_V, widen the EMUL of the vs2
source operand by 2x instead, as the split consumes a 2xLMUL
vector and produces an LMUL even/odd half. VPAIRE_VV / VPAIRO_VV
leave EMUL unchanged on every operand.
Assisted-by: TRAE CLI (Seed-2.1-Turbo)
---
Patch is 29.22 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/214405.diff
5 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td (+2-1)
- (modified) llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp (+50)
- (modified) llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir (+110-1)
- (modified) llvm/test/CodeGen/RISCV/rvv/vpaire.ll (+32-24)
- (modified) llvm/test/CodeGen/RISCV/rvv/vpairo.ll (+32-24)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td
index 6ed51a5da7478..5971832fac7c7 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td
@@ -15,7 +15,8 @@
// Instructions
//===----------------------------------------------------------------------===//
-let Predicates = [HasStdExtZvzip], Constraints = "@earlyclobber $vd" in {
+let Predicates = [HasStdExtZvzip], Constraints = "@earlyclobber $vd",
+ ElementsDependOn = EltDepsNone in {
let VS1VS2Constraint = WidenV in
def VZIP_VV : VALUVV<0b111110, OPMVV, "vzip.vv">;
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index f4a70ba4e52fb..800f437f82ffa 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -594,6 +594,13 @@ static std::optional<unsigned> getOperandLog2EEW(const MachineOperand &MO) {
case RISCV::VABS_V:
case RISCV::VABD_VV:
case RISCV::VABDU_VV:
+
+ // Zvzip
+ case RISCV::VZIP_VV:
+ case RISCV::VUNZIPE_V:
+ case RISCV::VUNZIPO_V:
+ case RISCV::VPAIRE_VV:
+ case RISCV::VPAIRO_VV:
return MILog2SEW;
// Vector Widening Shift Left Logical (Zvbb)
@@ -892,6 +899,49 @@ static std::optional<OperandInfo> getOperandInfo(const MachineOperand &MO) {
if (MO.getOperandNo() != 2)
return OperandInfo(*Log2EEW);
break;
+
+ // Zvzip - vzip.vv interleaves two LMUL vectors into a 2*LMUL result with
+ // the same SEW. Dest (and passthru) therefore have 2 * EMUL.
+ case RISCV::VZIP_VV: {
+ const MCInstrDesc &Desc = MI.getDesc();
+ const bool HasPassthru = RISCVII::isFirstDefTiedToFirstUse(Desc);
+ const bool IsMODef =
+ MO.getOperandNo() == 0 ||
+ (HasPassthru && MO.getOperandNo() == MI.getNumExplicitDefs());
+ auto EMUL = getEMULEqualsEEWDivSEWTimesLMUL(*Log2EEW, MI);
+ if (IsMODef) {
+ unsigned Num = EMUL.first;
+ bool IsFractional = EMUL.second;
+ if (IsFractional)
+ EMUL = std::make_pair(Num / 2, Num > 2);
+ else
+ EMUL = std::make_pair(Num * 2, false);
+ }
+ return OperandInfo(EMUL, *Log2EEW);
+ }
+ // Zvzip - vunzipe.v / vunzipo.v split a 2*LMUL vector into LMUL even/odd
+ // elements with the same SEW. The source (and passthru tied to dest which is
+ // also LMUL sized - so only the vs2 source) has 2 * EMUL.
+ case RISCV::VUNZIPE_V:
+ case RISCV::VUNZIPO_V: {
+ const MCInstrDesc &Desc = MI.getDesc();
+ const bool HasPassthru = RISCVII::isFirstDefTiedToFirstUse(Desc);
+ const bool IsMODef =
+ MO.getOperandNo() == 0 ||
+ (HasPassthru && MO.getOperandNo() == MI.getNumExplicitDefs());
+ unsigned VS2OpNo = HasPassthru ? 2 : 1;
+ bool IsVS2 = MO.getOperandNo() == VS2OpNo;
+ auto EMUL = getEMULEqualsEEWDivSEWTimesLMUL(*Log2EEW, MI);
+ if (IsVS2 && !IsMODef) {
+ unsigned Num = EMUL.first;
+ bool IsFractional = EMUL.second;
+ if (IsFractional)
+ EMUL = std::make_pair(Num / 2, Num > 2);
+ else
+ EMUL = std::make_pair(Num * 2, false);
+ }
+ return OperandInfo(EMUL, *Log2EEW);
+ }
};
// All others have EMUL=EEW/SEW*LMUL
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
index 8fcf81697681c..46e003659f463 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vl-optimizer -verify-machineinstrs | FileCheck %s
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v,+experimental-zvzip \
+# RUN: -run-pass=riscv-vl-optimizer -verify-machineinstrs | FileCheck %s
---
name: vop_vi
@@ -2423,3 +2424,111 @@ body: |
%2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */
PseudoVSOXSEG3EI32_V_M1_M2 $noreg, $noreg, %2, 1, 6 /* e64 */
...
+---
+name: vzip_vv_vd
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vzip_vv_vd
+ ; CHECK: early-clobber %0:vrm2 = PseudoVZIP_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 $noreg, %0, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]]
+ early-clobber %0:vrm2 = PseudoVZIP_VV_M1 $noreg, $noreg, $noreg, -1, 5, 0
+ %1:vrm2 = PseudoVADD_VV_M2 $noreg, %0, $noreg, 1, 5, 0
+ $v8m2 = COPY %1
+...
+---
+name: vzip_vv_incompatible_eew
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vzip_vv_incompatible_eew
+ ; CHECK: early-clobber %0:vrm2 = PseudoVZIP_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 $noreg, %0, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */
+ ; CHECK-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]]
+ early-clobber %0:vrm2 = PseudoVZIP_VV_M1 $noreg, $noreg, $noreg, -1, 5, 0
+ %1:vrm2 = PseudoVADD_VV_M2 $noreg, %0, $noreg, 1, 4, 0
+ $v8m2 = COPY %1
+...
+---
+name: vunzipe_v
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vunzipe_v
+ ; CHECK: early-clobber %0:vr = PseudoVUNZIPE_V_M1 $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, %0, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]]
+ early-clobber %0:vr = PseudoVUNZIPE_V_M1 $noreg, $noreg, -1, 5, 0
+ %1:vr = PseudoVADD_VV_M1 $noreg, %0, $noreg, 1, 5, 0
+ $v8 = COPY %1
+...
+---
+name: vunzipo_v
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vunzipo_v
+ ; CHECK: early-clobber %0:vr = PseudoVUNZIPO_V_M1 $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, %0, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]]
+ early-clobber %0:vr = PseudoVUNZIPO_V_M1 $noreg, $noreg, -1, 5, 0
+ %1:vr = PseudoVADD_VV_M1 $noreg, %0, $noreg, 1, 5, 0
+ $v8 = COPY %1
+...
+---
+name: vunzipe_incompatible_eew
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vunzipe_incompatible_eew
+ ; CHECK: early-clobber %0:vr = PseudoVUNZIPE_V_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, %0, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */
+ ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]]
+ early-clobber %0:vr = PseudoVUNZIPE_V_M1 $noreg, $noreg, -1, 5, 0
+ %1:vr = PseudoVADD_VV_M1 $noreg, %0, $noreg, 1, 4, 0
+ $v8 = COPY %1
+...
+---
+name: vunzipe_src_propagate
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vunzipe_src_propagate
+ ; CHECK: %src:vrm2 = PseudoVADD_VV_M2 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: early-clobber %1:vr = PseudoVUNZIPE_V_M1 $noreg, %src, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: $v8 = COPY %1
+ %src:vrm2 = PseudoVADD_VV_M2 $noreg, $noreg, $noreg, -1, 5, 0
+ early-clobber %1:vr = PseudoVUNZIPE_V_M1 $noreg, %src, 1, 5, 0
+ $v8 = COPY %1
+...
+---
+name: vpaire_vv
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vpaire_vv
+ ; CHECK: early-clobber %0:vr = PseudoVPAIRE_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, %0, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]]
+ early-clobber %0:vr = PseudoVPAIRE_VV_M1 $noreg, $noreg, $noreg, -1, 5, 0
+ %1:vr = PseudoVADD_VV_M1 $noreg, %0, $noreg, 1, 5, 0
+ $v8 = COPY %1
+...
+---
+name: vpairo_vv
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vpairo_vv
+ ; CHECK: early-clobber %0:vr = PseudoVPAIRO_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, %0, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]]
+ early-clobber %0:vr = PseudoVPAIRO_VV_M1 $noreg, $noreg, $noreg, -1, 5, 0
+ %1:vr = PseudoVADD_VV_M1 $noreg, %0, $noreg, 1, 5, 0
+ $v8 = COPY %1
+...
+---
+name: vpaire_incompatible_eew
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vpaire_incompatible_eew
+ ; CHECK: early-clobber %0:vr = PseudoVPAIRE_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, %0, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */
+ ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]]
+ early-clobber %0:vr = PseudoVPAIRE_VV_M1 $noreg, $noreg, $noreg, -1, 5, 0
+ %1:vr = PseudoVADD_VV_M1 $noreg, %0, $noreg, 1, 4, 0
+ $v8 = COPY %1
+...
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpaire.ll b/llvm/test/CodeGen/RISCV/rvv/vpaire.ll
index 8bc8f46882d48..4c689b907f02f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpaire.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpaire.ll
@@ -181,8 +181,9 @@ define <vscale x 32 x i8> @test_vpaire_mask_i8m4(<vscale x 32 x i8> %passthru, <
define <vscale x 64 x i8> @test_vpaire_i8m8(<vscale x 64 x i8> %passthru, <vscale x 64 x i8> %arg1, <vscale x 64 x i8> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vpaire_i8m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8r.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vle8.v v24, (a0)
+; CHECK-NEXT: vsetvli zero, zero, e8, m8, tu, ma
; CHECK-NEXT: vpaire.vv v8, v16, v24
; CHECK-NEXT: ret
%a = call <vscale x 64 x i8> @llvm.riscv.vpaire(
@@ -196,8 +197,8 @@ define <vscale x 64 x i8> @test_vpaire_i8m8(<vscale x 64 x i8> %passthru, <vscal
define <vscale x 64 x i8> @test_vpaire_mask_i8m8(<vscale x 64 x i8> %passthru, <vscale x 64 x i8> %arg1, <vscale x 64 x i8> %arg2, <vscale x 64 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vpaire_mask_i8m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
+; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vpaire.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 64 x i8> @llvm.riscv.vpaire.mask(
@@ -357,8 +358,9 @@ define <vscale x 16 x i16> @test_vpaire_mask_i16m4(<vscale x 16 x i16> %passthru
define <vscale x 32 x i16> @test_vpaire_i16m8(<vscale x 32 x i16> %passthru, <vscale x 32 x i16> %arg1, <vscale x 32 x i16> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vpaire_i16m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8re16.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, tu, ma
+; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; CHECK-NEXT: vle16.v v24, (a0)
+; CHECK-NEXT: vsetvli zero, zero, e16, m8, tu, ma
; CHECK-NEXT: vpaire.vv v8, v16, v24
; CHECK-NEXT: ret
%a = call <vscale x 32 x i16> @llvm.riscv.vpaire(
@@ -372,8 +374,8 @@ define <vscale x 32 x i16> @test_vpaire_i16m8(<vscale x 32 x i16> %passthru, <vs
define <vscale x 32 x i16> @test_vpaire_mask_i16m8(<vscale x 32 x i16> %passthru, <vscale x 32 x i16> %arg1, <vscale x 32 x i16> %arg2, <vscale x 32 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vpaire_mask_i16m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
+; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vpaire.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 32 x i16> @llvm.riscv.vpaire.mask(
@@ -504,8 +506,9 @@ define <vscale x 8 x i32> @test_vpaire_mask_i32m4(<vscale x 8 x i32> %passthru,
define <vscale x 16 x i32> @test_vpaire_i32m8(<vscale x 16 x i32> %passthru, <vscale x 16 x i32> %arg1, <vscale x 16 x i32> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vpaire_i32m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8re32.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT: vle32.v v24, (a0)
+; CHECK-NEXT: vsetvli zero, zero, e32, m8, tu, ma
; CHECK-NEXT: vpaire.vv v8, v16, v24
; CHECK-NEXT: ret
%a = call <vscale x 16 x i32> @llvm.riscv.vpaire(
@@ -519,8 +522,8 @@ define <vscale x 16 x i32> @test_vpaire_i32m8(<vscale x 16 x i32> %passthru, <vs
define <vscale x 16 x i32> @test_vpaire_mask_i32m8(<vscale x 16 x i32> %passthru, <vscale x 16 x i32> %arg1, <vscale x 16 x i32> %arg2, <vscale x 16 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vpaire_mask_i32m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
+; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vpaire.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 16 x i32> @llvm.riscv.vpaire.mask(
@@ -622,8 +625,9 @@ define <vscale x 4 x i64> @test_vpaire_mask_i64m4(<vscale x 4 x i64> %passthru,
define <vscale x 8 x i64> @test_vpaire_i64m8(<vscale x 8 x i64> %passthru, <vscale x 8 x i64> %arg1, <vscale x 8 x i64> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vpaire_i64m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8re64.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, ma
+; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; CHECK-NEXT: vle64.v v24, (a0)
+; CHECK-NEXT: vsetvli zero, zero, e64, m8, tu, ma
; CHECK-NEXT: vpaire.vv v8, v16, v24
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.riscv.vpaire(
@@ -637,8 +641,8 @@ define <vscale x 8 x i64> @test_vpaire_i64m8(<vscale x 8 x i64> %passthru, <vsca
define <vscale x 8 x i64> @test_vpaire_mask_i64m8(<vscale x 8 x i64> %passthru, <vscale x 8 x i64> %arg1, <vscale x 8 x i64> %arg2, <vscale x 8 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vpaire_mask_i64m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vpaire.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.riscv.vpaire.mask(
@@ -806,8 +810,9 @@ define <vscale x 16 x half> @test_vpaire_mask_f16m4(<vscale x 16 x half> %passth
define <vscale x 32 x half> @test_vpaire_f16m8(<vscale x 32 x half> %passthru, <vscale x 32 x half> %a1, <vscale x 32 x half> %a2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vpaire_f16m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8re16.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, tu, ma
+; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; CHECK-NEXT: vle16.v v24, (a0)
+; CHECK-NEXT: vsetvli zero, zero, e16, m8, tu, ma
; CHECK-NEXT: vpaire.vv v8, v16, v24
; CHECK-NEXT: ret
%r = call <vscale x 32 x half> @llvm.riscv.vpaire(
@@ -821,8 +826,8 @@ define <vscale x 32 x half> @test_vpaire_f16m8(<vscale x 32 x half> %passthru, <
define <vscale x 32 x half> @test_vpaire_mask_f16m8(<vscale x 32 x half> %passthru, <vscale x 32 x half> %a1, <vscale x 32 x half> %a2, <vscale x 32 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vpaire_mask_f16m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
+; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vpaire.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 32 x half> @llvm.riscv.vpaire.mask(
@@ -989,8 +994,9 @@ define <vscale x 16 x bfloat> @test_vpaire_mask_bf16m4(<vscale x 16 x bfloat> %p
define <vscale x 32 x bfloat> @test_vpaire_bf16m8(<vscale x 32 x bfloat> %passthru, <vscale x 32 x bfloat> %a1, <vscale x 32 x bfloat> %a2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vpaire_bf16m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8re16.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, tu, ma
+; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; CHECK-NEXT: vle16.v v24, (a0)
+; CHECK-NEXT: vsetvli zero, zero, e16, m8, tu, ma
; CHECK-NEXT: vpaire.vv v8, v16, v24
; CHECK-NEXT: ret
%r = call <vscale x 32 x bfloat> @llvm.riscv.vpaire(
@@ -1004,8 +1010,8 @@ define <vscale x 32 x bfloat> @test_vpaire_bf16m8(<vscale x 32 x bfloat> %passth
define <vscale x 32 x bfloat> @test_vpaire_mask_bf16m8(<vscale x 32 x bfloat> %passthru, <vscale x 32 x bfloat> %a1, <vscale x 32 x bfloat> %a2, <vscale x 32 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vpaire_mask_bf16m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
+; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vpaire.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.mask(
@@ -1142,8 +1148,9 @@ define <vscale x 8 x float> @test_vpaire_mask_f32m4(<vscale x 8 x float> %passth
define <vscale x 16 x float> @test_vpaire_f32m8(<vscale x 16 x float> %passthru, <vscale x 16 x float> %a1, <vscale x 16 x float> %a2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vpaire_f32m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8re32.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT: vle32.v v24, (a0)
+; CHECK-NEXT: vsetvli zero, zero, e32, m8, tu, ma
; CHECK-NEXT: vpaire.vv v8, v16, v24
; CHECK-NEXT: ret
%r = call <vscale x 16 x float> @llvm.riscv.vpaire(
@@ -1157,8 +1164,8 @@ define <vscale x 16 x float> @test_vpaire_f32m8(<vscale x 16 x float> %passthru,
define <vscale x 16 x float> @test_vpaire_mask_f32m8(<vscale x 16 x float> %passthru, <vscale x 16 x float> %a1, <vscale x 16 x float> %a2, <vscale x 16 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vpaire_mask_f32m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
+; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vpaire.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 16 x float> @llvm.riscv.vpaire.mask(
@@ -1265,8 +1272,9 @@ define <vscale x 4 x double> @test_vpaire_mask_f64m4(<vscale x 4 x double> %pass
define <vscale x 8 x double> @test_vpaire_f64m8(<vscale x 8 x double> %passthru, <vscale x 8 x double> %a1, <vscale x 8 x double> %a2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vpaire_f64m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8re64.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, ma
+; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; CHECK-NEXT: vle64.v v24, (a0)
+; CHECK-NEXT: vsetvli zero, zero, e64, m8, tu, ma
; CHECK-NEXT: vpaire.vv v8, v16, v24
; CHECK-NEXT: ret
%r = call <vscale x 8 x double> @llvm.riscv.vpaire(
@@ -1280,8 +1288,8 @@ define <vscale x 8 x double> @test_vpaire_f64m8(<vscale x 8 x double> %passthru,
define <vscale x 8 x double> @test_vpaire_mask_f64m8(<vscale x 8 x double> %passthru, <vscale x 8 x double> %a1, <vscale x 8 x double> %a2, <vscale x 8 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vpaire_mask_f64m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vpaire.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 8 x double> @llvm.riscv.vpaire.mask(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpairo.ll b/llvm/test/CodeGen/RISCV/rvv/vpairo.ll
index 78e63cfe4f3f4..aa7c408e426bb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpairo.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpairo.ll
@@ -181,8 +181,9 @@ define <vscale x 32 x i8> @test_vpairo_mask_i8m4(<vscale x 32 x i8> %passthru, <
define <vscale x 64 x i8> @test_vpairo_i8m8(<vscale x 64 x i8> %passthru, <vscale x 64 x i8> %arg1, <vscale x 64 x i8> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vpairo_i8m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8r.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vle8.v v24, (a0)
+; CHECK-NEXT: vsetvli zero, zero, e8, m8, tu, ma
; CHECK-NEXT: vpairo.vv v8, v16, v24
; CHECK-NEXT: ret
%a = call <vscale x 64 x i8> @llvm.riscv.vpairo(
@@ -196,8 +197,8 @@ define <vscale x 64 x i8> @test_...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/214405
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