[llvm] [AMDGPU][GlobalISel] Pre-commit tests for readanylane merge regbank combine (NFC) (PR #214355)

[Anshil Gandhi via llvm-commits]

https://github.com/gandhi56 updated https://github.com/llvm/llvm-project/pull/214355

>From 16366138a74c0d87707f348ff8aad0b8a360c7aa Mon Sep 17 00:00:00 2001
From: Anshil Gandhi <Anshil.Gandhi at amd.com>
Date: Wed, 5 Aug 2026 17:34:19 -0500
Subject: [PATCH] [AMDGPU][GlobalISel] Pre-commit tests for readanylane merge
 regbank combine (NFC)

Add regbank-combiner tests covering a copy to vgpr whose source is a
merge or build_vector of G_AMDGPU_READANYLANE results and uniform
values. These currently keep the round trip through sgprs, and also
cover the cases where the merge has another user and where all merge
sources are uniform.

Co-authored-by: Cursor <cursoragent at cursor.com>
---
 .../regbankcombiner-merge-readanylane.mir     | 103 ++++++++++++++++++
 1 file changed, 103 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir
new file mode 100644
index 0000000000000..790bac28defbf
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir
@@ -0,0 +1,103 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -mcpu=gfx1200 -run-pass=amdgpu-regbank-combiner %s -verify-machineinstrs -o - | FileCheck %s
+
+---
+name: readanylane_and_uniform_merge_to_virtual_vgpr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+
+    ; CHECK-LABEL: name: readanylane_and_uniform_merge_to_virtual_vgpr
+    ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
+    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY3]](s32)
+    ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[COPY4]]
+    ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[FCANONICALIZE]]
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[AMDGPU_READANYLANE]](s32)
+    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(<2 x s32>) = COPY [[BUILD_VECTOR]](<2 x s32>)
+    ; CHECK-NEXT: G_STORE [[COPY5]](<2 x s32>), [[MV]](p1) :: (store (<2 x s32>), addrspace 1)
+    ; CHECK-NEXT: S_ENDPGM 0
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:sgpr(p1) = G_MERGE_VALUES %0(s32), %1(s32)
+    %3:sgpr(s32) = COPY $sgpr2
+    %4:sgpr(s32) = COPY $sgpr3
+    %5:vgpr(s32) = COPY %4(s32)
+    %6:vgpr(s32) = G_FCANONICALIZE %5
+    %7:sgpr(s32) = G_AMDGPU_READANYLANE %6
+    %8:sgpr(<2 x s32>) = G_BUILD_VECTOR %3(s32), %7(s32)
+    %9:vgpr(<2 x s32>) = COPY %8(<2 x s32>)
+    G_STORE %9(<2 x s32>), %2(p1) :: (store (<2 x s32>), addrspace 1)
+    S_ENDPGM 0
+...
+
+# The sgpr merge is still needed by its other user.
+---
+name: readanylane_and_uniform_merge_multiple_uses
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1, $vgpr0
+
+    ; CHECK-LABEL: name: readanylane_and_uniform_merge_multiple_uses
+    ; CHECK: liveins: $sgpr0, $sgpr1, $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[COPY2]]
+    ; CHECK-NEXT: [[MV1:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY]](s32), [[AMDGPU_READANYLANE]](s32)
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[MV1]](s64)
+    ; CHECK-NEXT: G_STORE [[MV1]](s64), [[MV]](p1) :: (store (s64), addrspace 1)
+    ; CHECK-NEXT: G_STORE [[COPY3]](s64), [[MV]](p1) :: (store (s64), addrspace 1)
+    ; CHECK-NEXT: S_ENDPGM 0
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:sgpr(p1) = G_MERGE_VALUES %0(s32), %1(s32)
+    %3:vgpr(s32) = COPY $vgpr0
+    %4:sgpr(s32) = G_AMDGPU_READANYLANE %3
+    %5:sgpr(s64) = G_MERGE_VALUES %0(s32), %4(s32)
+    %6:vgpr(s64) = COPY %5(s64)
+    G_STORE %5(s64), %2(p1) :: (store (s64), addrspace 1)
+    G_STORE %6(s64), %2(p1) :: (store (s64), addrspace 1)
+    S_ENDPGM 0
+...
+
+# All merge sources are uniform, moving the copy to the sources would not
+# remove any readanylane.
+---
+name: uniform_merge_to_virtual_vgpr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+
+    ; CHECK-LABEL: name: uniform_merge_to_virtual_vgpr
+    ; CHECK: liveins: $sgpr0, $sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s32>) = COPY [[BUILD_VECTOR]](<2 x s32>)
+    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](<2 x s32>)
+    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0_vgpr1
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:sgpr(<2 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32)
+    %3:vgpr(<2 x s32>) = COPY %2(<2 x s32>)
+    $vgpr0_vgpr1 = COPY %3(<2 x s32>)
+    SI_RETURN_TO_EPILOG implicit $vgpr0_vgpr1
+...