[llvm] [AMDGPU][GISel] RegBankLegalize rule for amdgcn_alignbyte (PR #214323)
Chinmay Deshpande via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 5 12:56:54 PDT 2026
https://github.com/chinmaydd created https://github.com/llvm/llvm-project/pull/214323
None
>From fdc2d844b4de4123aad53a5cbaf3449e01354518 Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Wed, 5 Aug 2026 12:13:25 -0700
Subject: [PATCH] [AMDGPU][GISel] RegBankLegalize rule for amdgcn_alignbyte
llvm.amdgcn.alignbyte reached AMDGPURegBankLegalize without a rule and failed
with "No AMDGPU RegBankLegalize rules defined for opcode". Its shape matches
amdgcn_perm exactly - i32 result from three VGPR i32 sources - so add it to
that rule set. All V_ALIGNBYTE_B32 selection patterns, including the true16
one that extracts lo16 from src2, take a VGPR_32 src2, so a single mapping
covers every subtarget.
Enable GlobalISel in the lit test and regenerate the checks.
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 2 +-
.../CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll | 502 ++++++++++++------
2 files changed, 338 insertions(+), 166 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 499a018828957..6cfbacac0c566 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1957,7 +1957,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
addRulesForIOpcs({amdgcn_permlane_idx_gen}, Standard)
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32, SgprB32_ReadFirstLane}});
- addRulesForIOpcs({amdgcn_perm}, Standard)
+ addRulesForIOpcs({amdgcn_alignbyte, amdgcn_perm}, Standard)
.Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}})
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}});
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
index 914eb2108d442..de05fe56b8428 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
@@ -1,179 +1,345 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -mtriple=amdgpu10.30 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s
-; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu10.30 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu10.30 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-TRUE16,GFX11-TRUE16-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-TRUE16,GFX11-TRUE16-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-FAKE16,GFX11-FAKE16-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-FAKE16,GFX11-FAKE16-GISEL %s
declare i32 @llvm.amdgcn.alignbyte(i32, i32, i32) #0
define amdgpu_kernel void @v_alignbyte_b32(ptr addrspace(1) %out, i32 %src1, i32 %src2, i32 %src3) #1 {
-; GCN-LABEL: v_alignbyte_b32:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mov_b32_e32 v0, s1
-; GCN-NEXT: v_mov_b32_e32 v1, s2
-; GCN-NEXT: v_alignbyte_b32 v0, s0, v0, v1
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_alignbyte_b32:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_mov_b32_e32 v2, s2
-; GFX9-NEXT: v_alignbyte_b32 v1, s0, v1, v2
-; GFX9-NEXT: global_store_dword v0, v1, s[6:7]
-; GFX9-NEXT: s_endpgm
-;
-; GFX10-LABEL: v_alignbyte_b32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_clause 0x1
-; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
-; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
-; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GFX10-NEXT: v_alignbyte_b32 v0, s0, s1, v0
-; GFX10-NEXT: global_store_dword v1, v0, s[4:5]
-; GFX10-NEXT: s_endpgm
-;
-; GFX11-TRUE16-LABEL: v_alignbyte_b32:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_alignbyte_b32 v0, s0, s1, v0.l
-; GFX11-TRUE16-NEXT: global_store_b32 v1, v0, s[4:5]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: v_alignbyte_b32:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_alignbyte_b32 v0, s0, s1, v0
-; GFX11-FAKE16-NEXT: global_store_b32 v1, v0, s[4:5]
-; GFX11-FAKE16-NEXT: s_endpgm
+; GCN-SDAG-LABEL: v_alignbyte_b32:
+; GCN-SDAG: ; %bb.0:
+; GCN-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
+; GCN-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; GCN-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GCN-SDAG-NEXT: s_mov_b32 s6, -1
+; GCN-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-SDAG-NEXT: v_mov_b32_e32 v0, s1
+; GCN-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; GCN-SDAG-NEXT: v_alignbyte_b32 v0, s0, v0, v1
+; GCN-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GCN-SDAG-NEXT: s_endpgm
+;
+; GCN-GISEL-LABEL: v_alignbyte_b32:
+; GCN-GISEL: ; %bb.0:
+; GCN-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GCN-GISEL-NEXT: s_load_dword s4, s[4:5], 0xd
+; GCN-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GCN-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; GCN-GISEL-NEXT: v_alignbyte_b32 v0, s2, v0, v1
+; GCN-GISEL-NEXT: s_mov_b32 s2, -1
+; GCN-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GCN-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GCN-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: v_alignbyte_b32:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-SDAG-NEXT: v_alignbyte_b32 v1, s0, v1, v2
+; GFX9-SDAG-NEXT: global_store_dword v0, v1, s[6:7]
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: v_alignbyte_b32:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_load_dword s6, s[4:5], 0x34
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX9-GISEL-NEXT: v_alignbyte_b32 v0, s2, v0, v1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX10-SDAG-LABEL: v_alignbyte_b32:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_clause 0x1
+; GFX10-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; GFX10-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; GFX10-SDAG-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX10-SDAG-NEXT: v_alignbyte_b32 v0, s0, s1, v0
+; GFX10-SDAG-NEXT: global_store_dword v1, v0, s[4:5]
+; GFX10-SDAG-NEXT: s_endpgm
+;
+; GFX10-GISEL-LABEL: v_alignbyte_b32:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_clause 0x1
+; GFX10-GISEL-NEXT: s_load_dword s6, s[4:5], 0x34
+; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX10-GISEL-NEXT: v_alignbyte_b32 v0, s2, s3, v0
+; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX10-GISEL-NEXT: s_endpgm
+;
+; GFX11-TRUE16-SDAG-LABEL: v_alignbyte_b32:
+; GFX11-TRUE16-SDAG: ; %bb.0:
+; GFX11-TRUE16-SDAG-NEXT: s_clause 0x1
+; GFX11-TRUE16-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX11-TRUE16-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-TRUE16-SDAG-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-SDAG-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-SDAG-NEXT: v_alignbyte_b32 v0, s0, s1, v0.l
+; GFX11-TRUE16-SDAG-NEXT: global_store_b32 v1, v0, s[4:5]
+; GFX11-TRUE16-SDAG-NEXT: s_endpgm
+;
+; GFX11-TRUE16-GISEL-LABEL: v_alignbyte_b32:
+; GFX11-TRUE16-GISEL: ; %bb.0:
+; GFX11-TRUE16-GISEL-NEXT: s_clause 0x1
+; GFX11-TRUE16-GISEL-NEXT: s_load_b32 s6, s[4:5], 0x34
+; GFX11-TRUE16-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s6
+; GFX11-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-GISEL-NEXT: v_alignbyte_b32 v0, s2, s3, v0.l
+; GFX11-TRUE16-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-TRUE16-GISEL-NEXT: s_endpgm
+;
+; GFX11-FAKE16-SDAG-LABEL: v_alignbyte_b32:
+; GFX11-FAKE16-SDAG: ; %bb.0:
+; GFX11-FAKE16-SDAG-NEXT: s_clause 0x1
+; GFX11-FAKE16-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX11-FAKE16-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-FAKE16-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX11-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-SDAG-NEXT: v_alignbyte_b32 v0, s0, s1, v0
+; GFX11-FAKE16-SDAG-NEXT: global_store_b32 v1, v0, s[4:5]
+; GFX11-FAKE16-SDAG-NEXT: s_endpgm
+;
+; GFX11-FAKE16-GISEL-LABEL: v_alignbyte_b32:
+; GFX11-FAKE16-GISEL: ; %bb.0:
+; GFX11-FAKE16-GISEL-NEXT: s_clause 0x1
+; GFX11-FAKE16-GISEL-NEXT: s_load_b32 s6, s[4:5], 0x34
+; GFX11-FAKE16-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s6
+; GFX11-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-GISEL-NEXT: v_alignbyte_b32 v0, s2, s3, v0
+; GFX11-FAKE16-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-FAKE16-GISEL-NEXT: s_endpgm
%val = call i32 @llvm.amdgcn.alignbyte(i32 %src1, i32 %src2, i32 %src3) #0
store i32 %val, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v_alignbyte_b32_2(ptr addrspace(1) %out, ptr addrspace(1) %src1, ptr addrspace(1) %src2, i32 %src3) #1 {
-; GCN-LABEL: v_alignbyte_b32_2:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GCN-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s14, 0
-; GCN-NEXT: s_mov_b32 s15, s7
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_mov_b64 s[12:13], s[2:3]
-; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: s_mov_b64 s[10:11], s[14:15]
-; GCN-NEXT: buffer_load_dword v2, v[0:1], s[12:15], 0 addr64 glc
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 glc
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: s_load_dword s2, s[4:5], 0xf
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_mov_b32 s4, s0
-; GCN-NEXT: s_mov_b32 s5, s1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_alignbyte_b32 v0, v2, v0, s2
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_alignbyte_b32_2:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: global_load_dword v2, v0, s[6:7] glc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x3c
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_alignbyte_b32 v1, v1, v2, s2
-; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GFX10-LABEL: v_alignbyte_b32_2:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_clause 0x1
-; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: global_load_dword v1, v0, s[2:3] glc dlc
-; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: global_load_dword v0, v0, s[6:7] glc dlc
-; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: s_load_dword s2, s[4:5], 0x3c
-; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_alignbyte_b32 v0, v1, v0, s2
-; GFX10-NEXT: global_store_dword v2, v0, s[0:1]
-; GFX10-NEXT: s_endpgm
-;
-; GFX11-TRUE16-LABEL: v_alignbyte_b32_2:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-TRUE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b32 v1, v0, s[2:3] glc dlc
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b32 v0, v0, s[6:7] glc dlc
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x3c
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_alignbyte_b32 v0, v1, v0, s2
-; GFX11-TRUE16-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: v_alignbyte_b32_2:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: global_load_b32 v1, v0, s[2:3] glc dlc
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: global_load_b32 v0, v0, s[6:7] glc dlc
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x3c
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_alignbyte_b32 v0, v1, v0, s2
-; GFX11-FAKE16-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX11-FAKE16-NEXT: s_endpgm
+; GCN-SDAG-LABEL: v_alignbyte_b32_2:
+; GCN-SDAG: ; %bb.0:
+; GCN-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GCN-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
+; GCN-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; GCN-SDAG-NEXT: s_mov_b32 s14, 0
+; GCN-SDAG-NEXT: s_mov_b32 s15, s7
+; GCN-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-SDAG-NEXT: s_mov_b64 s[12:13], s[2:3]
+; GCN-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0
+; GCN-SDAG-NEXT: s_mov_b64 s[10:11], s[14:15]
+; GCN-SDAG-NEXT: buffer_load_dword v2, v[0:1], s[12:15], 0 addr64 glc
+; GCN-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GCN-SDAG-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 glc
+; GCN-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GCN-SDAG-NEXT: s_load_dword s2, s[4:5], 0xf
+; GCN-SDAG-NEXT: s_mov_b32 s6, -1
+; GCN-SDAG-NEXT: s_mov_b32 s4, s0
+; GCN-SDAG-NEXT: s_mov_b32 s5, s1
+; GCN-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-SDAG-NEXT: v_alignbyte_b32 v0, v2, v0, s2
+; GCN-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GCN-SDAG-NEXT: s_endpgm
+;
+; GCN-GISEL-LABEL: v_alignbyte_b32_2:
+; GCN-GISEL: ; %bb.0:
+; GCN-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GCN-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
+; GCN-GISEL-NEXT: s_mov_b32 s14, 0
+; GCN-GISEL-NEXT: s_mov_b32 s15, 0xf000
+; GCN-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GCN-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-GISEL-NEXT: s_mov_b64 s[12:13], s[2:3]
+; GCN-GISEL-NEXT: s_mov_b64 s[10:11], s[14:15]
+; GCN-GISEL-NEXT: buffer_load_dword v2, v[0:1], s[12:15], 0 addr64 glc
+; GCN-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GCN-GISEL-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 glc
+; GCN-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GCN-GISEL-NEXT: s_load_dword s2, s[4:5], 0xf
+; GCN-GISEL-NEXT: s_mov_b32 s14, -1
+; GCN-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-GISEL-NEXT: v_alignbyte_b32 v0, v2, v0, s2
+; GCN-GISEL-NEXT: s_mov_b64 s[2:3], s[14:15]
+; GCN-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GCN-GISEL-NEXT: s_endpgm
+;
+; GFX9-SDAG-LABEL: v_alignbyte_b32_2:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: global_load_dword v1, v0, s[2:3] glc
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX9-SDAG-NEXT: global_load_dword v2, v0, s[6:7] glc
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX9-SDAG-NEXT: s_load_dword s2, s[4:5], 0x3c
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_alignbyte_b32 v1, v1, v2, s2
+; GFX9-SDAG-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX9-SDAG-NEXT: s_endpgm
+;
+; GFX9-GISEL-LABEL: v_alignbyte_b32_2:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: global_load_dword v1, v0, s[2:3] glc
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9-GISEL-NEXT: global_load_dword v2, v0, s[6:7] glc
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x3c
+; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_alignbyte_b32 v0, v1, v2, s2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX9-GISEL-NEXT: s_endpgm
+;
+; GFX10-SDAG-LABEL: v_alignbyte_b32_2:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_clause 0x1
+; GFX10-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX10-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-SDAG-NEXT: global_load_dword v1, v0, s[2:3] glc dlc
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX10-SDAG-NEXT: global_load_dword v0, v0, s[6:7] glc dlc
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX10-SDAG-NEXT: s_load_dword s2, s[4:5], 0x3c
+; GFX10-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_alignbyte_b32 v0, v1, v0, s2
+; GFX10-SDAG-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX10-SDAG-NEXT: s_endpgm
+;
+; GFX10-GISEL-LABEL: v_alignbyte_b32_2:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_clause 0x1
+; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX10-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-GISEL-NEXT: global_load_dword v1, v0, s[2:3] glc dlc
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX10-GISEL-NEXT: global_load_dword v0, v0, s[6:7] glc dlc
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX10-GISEL-NEXT: s_load_dword s2, s[4:5], 0x3c
+; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_alignbyte_b32 v0, v1, v0, s2
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX10-GISEL-NEXT: s_endpgm
+;
+; GFX11-TRUE16-SDAG-LABEL: v_alignbyte_b32_2:
+; GFX11-TRUE16-SDAG: ; %bb.0:
+; GFX11-TRUE16-SDAG-NEXT: s_clause 0x1
+; GFX11-TRUE16-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
+; GFX11-TRUE16-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-TRUE16-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-TRUE16-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-SDAG-NEXT: global_load_b32 v1, v0, s[2:3] glc dlc
+; GFX11-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-SDAG-NEXT: global_load_b32 v0, v0, s[6:7] glc dlc
+; GFX11-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x3c
+; GFX11-TRUE16-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-SDAG-NEXT: v_alignbyte_b32 v0, v1, v0, s2
+; GFX11-TRUE16-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX11-TRUE16-SDAG-NEXT: s_endpgm
+;
+; GFX11-TRUE16-GISEL-LABEL: v_alignbyte_b32_2:
+; GFX11-TRUE16-GISEL: ; %bb.0:
+; GFX11-TRUE16-GISEL-NEXT: s_clause 0x1
+; GFX11-TRUE16-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
+; GFX11-TRUE16-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-TRUE16-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-GISEL-NEXT: global_load_b32 v1, v0, s[2:3] glc dlc
+; GFX11-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-GISEL-NEXT: global_load_b32 v0, v0, s[6:7] glc dlc
+; GFX11-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x3c
+; GFX11-TRUE16-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-GISEL-NEXT: v_alignbyte_b32 v0, v1, v0, v2.l
+; GFX11-TRUE16-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-TRUE16-GISEL-NEXT: s_endpgm
+;
+; GFX11-FAKE16-SDAG-LABEL: v_alignbyte_b32_2:
+; GFX11-FAKE16-SDAG: ; %bb.0:
+; GFX11-FAKE16-SDAG-NEXT: s_clause 0x1
+; GFX11-FAKE16-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
+; GFX11-FAKE16-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-FAKE16-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-FAKE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-FAKE16-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-SDAG-NEXT: global_load_b32 v1, v0, s[2:3] glc dlc
+; GFX11-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-SDAG-NEXT: global_load_b32 v0, v0, s[6:7] glc dlc
+; GFX11-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x3c
+; GFX11-FAKE16-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-SDAG-NEXT: v_alignbyte_b32 v0, v1, v0, s2
+; GFX11-FAKE16-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX11-FAKE16-SDAG-NEXT: s_endpgm
+;
+; GFX11-FAKE16-GISEL-LABEL: v_alignbyte_b32_2:
+; GFX11-FAKE16-GISEL: ; %bb.0:
+; GFX11-FAKE16-GISEL-NEXT: s_clause 0x1
+; GFX11-FAKE16-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
+; GFX11-FAKE16-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-FAKE16-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-GISEL-NEXT: global_load_b32 v1, v0, s[2:3] glc dlc
+; GFX11-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-GISEL-NEXT: global_load_b32 v0, v0, s[6:7] glc dlc
+; GFX11-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x3c
+; GFX11-FAKE16-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-GISEL-NEXT: v_alignbyte_b32 v0, v1, v0, s2
+; GFX11-FAKE16-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-FAKE16-GISEL-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%a.gep = getelementptr inbounds i32, ptr addrspace(1) %src1, i32 %tid
%b.gep = getelementptr inbounds i32, ptr addrspace(1) %src2, i32 %tid
@@ -187,3 +353,9 @@ define amdgpu_kernel void @v_alignbyte_b32_2(ptr addrspace(1) %out, ptr addrspac
attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GCN: {{.*}}
+; GFX10: {{.*}}
+; GFX11-FAKE16: {{.*}}
+; GFX11-TRUE16: {{.*}}
+; GFX9: {{.*}}
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