[llvm] [AArch64] Add widening for vector interleave (PR #214313)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions h,cpp -- llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 41ef7ac78..e2286762e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -1081,7 +1081,7 @@ private:
   SDValue WidenVecRes_GET_ACTIVE_LANE_MASK(SDNode *N);
   void WidenVecRes_VECTOR_DEINTERLEAVE(SDNode *N);
   void WidenVecRes_VECTOR_INTERLEAVE(SDNode *N);
-  
+
   SDValue WidenVecRes_Ternary(SDNode *N);
   SDValue WidenVecRes_Binary(SDNode *N);
   SDValue WidenVecRes_MaskedBinary(SDNode *N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index f511c51f0..9262d4658 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -5330,7 +5330,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
     break;
   case ISD::VECTOR_INTERLEAVE:
     WidenVecRes_VECTOR_INTERLEAVE(N);
-    break; 
+    break;
   case ISD::VECTOR_DEINTERLEAVE:
     WidenVecRes_VECTOR_DEINTERLEAVE(N);
     break;

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https://github.com/llvm/llvm-project/pull/214313