[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for uniform i16 extending loads (PR #214267)
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 5 09:01:59 PDT 2026
https://github.com/petar-avramovic created https://github.com/llvm/llvm-project/pull/214267
Extending loads, i8 to i16, are legal on targets with true16.
>From 05fbed0fe1b931e047cf7b9a7a4bb4d73d716d68 Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Wed, 5 Aug 2026 17:59:06 +0200
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for uniform i16
extending loads
Extending loads, i8 to i16, are legal on targets with true16.
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 5 +
.../load-zero-and-sign-extending-uniform.ll | 180 ++++++++++++++++++
2 files changed, 185 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 4bdbce7c2aa8e..39c1ff1bcfdfa 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1197,6 +1197,8 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{DivS32, P1}, {{Vgpr32}, {VgprP1}}})
.Any({{DivS16, P1}, {{Vgpr16}, {VgprP1}}}, usesTrue16)
+ .Any({{UniS16, P1}, {{Sgpr32Trunc}, {SgprP1}}}, usesTrue16 && hasSMRDSmall)
+ .Any({{UniS16, P1}, {{UniInVgprS16}, {SgprP1}}}, usesTrue16 && !hasSMRDSmall)
.Any({{{UniS32, P1}, isAlign4 && isUL}, {{Sgpr32}, {SgprP1}, WidenMMOToS32}}, !hasSMRDSmall)
.Any({{{UniS32, P1}, isNaturalAligned && isUL}, {{Sgpr32}, {SgprP1}}}, hasSMRDSmall)
.Any({{{UniS32, P1}, !isAlign4 || !isUL}, {{UniInVgprS32}, {SgprP1}}}, !hasSMRDSmall)
@@ -1204,10 +1206,13 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{DivS32, P3}, {{Vgpr32}, {VgprP3}}})
.Any({{DivS16, P3}, {{Vgpr16}, {VgprP3}}}, usesTrue16)
+ .Any({{UniS16, P3}, {{UniInVgprS16}, {SgprP3}}}, usesTrue16)
.Any({{UniS32, P3}, {{UniInVgprS32}, {VgprP3}}})
.Any({{DivS32, P4}, {{Vgpr32}, {VgprP4}}})
.Any({{DivS16, P4}, {{Vgpr16}, {VgprP4}}}, usesTrue16)
+ .Any({{UniS16, P4}, {{Sgpr32Trunc}, {SgprP4}}}, usesTrue16 && hasSMRDSmall)
+ .Any({{UniS16, P4}, {{UniInVgprS16}, {SgprP4}}}, usesTrue16 && !hasSMRDSmall)
.Any({{{UniS32, P4}, isAlign4 && isUL}, {{Sgpr32}, {SgprP4}, WidenMMOToS32}}, !hasSMRDSmall)
.Any({{{UniS32, P4}, isNaturalAligned && isUL}, {{Sgpr32}, {SgprP4}}}, hasSMRDSmall)
.Any({{{UniS32, P4}, !isAlign4 || !isUL}, {{UniInVgprS32}, {SgprP4}}}, !hasSMRDSmall)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform.ll
index f52ab933d9de9..17a76293ff656 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform.ll
@@ -229,3 +229,183 @@ define amdgpu_ps void @zextload_P1_i16_align4_gfx11(ptr addrspace(1) inreg %ptra
store i32 %res, ptr addrspace(1) %out
ret void
}
+
+; i8 -> i16 uniform extending loads (UniS16)
+
+define amdgpu_ps void @sextload_P1_i8_to_i16(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {
+; GFX11-LABEL: sextload_P1_i8_to_i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: global_load_d16_i8 v2, v2, s[0:1]
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v2
+; GFX11-NEXT: s_add_i32 s0, s0, s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-NEXT: global_store_b16 v[0:1], v2, off
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: sextload_P1_i8_to_i16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_i8 s0, s[0:1], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_add_co_i32 s0, s0, s0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-NEXT: s_endpgm
+ %a = load i8, ptr addrspace(1) %ptra
+ %a16 = sext i8 %a to i16
+ %res = add i16 %a16, %a16
+ store i16 %res, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @sextload_P3_i8_to_i16(ptr addrspace(3) inreg %ptra, ptr addrspace(1) %out) {
+; GFX11-LABEL: sextload_P3_i8_to_i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v2, s0
+; GFX11-NEXT: ds_load_i8_d16 v2, v2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v2
+; GFX11-NEXT: s_add_i32 s0, s0, s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-NEXT: global_store_b16 v[0:1], v2, off
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: sextload_P3_i8_to_i16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_mov_b32_e32 v2, s0
+; GFX12-NEXT: ds_load_i8_d16 v2, v2
+; GFX12-NEXT: s_wait_dscnt 0x0
+; GFX12-NEXT: v_readfirstlane_b32 s0, v2
+; GFX12-NEXT: s_add_co_i32 s0, s0, s0
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-NEXT: s_endpgm
+ %a = load i8, ptr addrspace(3) %ptra
+ %a16 = sext i8 %a to i16
+ %res = add i16 %a16, %a16
+ store i16 %res, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @sextload_P4_i8_to_i16(ptr addrspace(4) inreg %ptra, ptr addrspace(1) %out) {
+; GFX11-LABEL: sextload_P4_i8_to_i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: global_load_d16_i8 v2, v2, s[0:1]
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v2
+; GFX11-NEXT: s_add_i32 s0, s0, s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-NEXT: global_store_b16 v[0:1], v2, off
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: sextload_P4_i8_to_i16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_i8 s0, s[0:1], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_add_co_i32 s0, s0, s0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-NEXT: s_endpgm
+ %a = load i8, ptr addrspace(4) %ptra
+ %a16 = sext i8 %a to i16
+ %res = add i16 %a16, %a16
+ store i16 %res, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @zextload_P1_i8_to_i16(ptr addrspace(1) inreg %ptra, ptr addrspace(1) %out) {
+; GFX11-LABEL: zextload_P1_i8_to_i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: global_load_d16_u8 v2, v2, s[0:1]
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v2
+; GFX11-NEXT: s_add_i32 s0, s0, s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-NEXT: global_store_b16 v[0:1], v2, off
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: zextload_P1_i8_to_i16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_add_co_i32 s0, s0, s0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-NEXT: s_endpgm
+ %a = load i8, ptr addrspace(1) %ptra
+ %a16 = zext i8 %a to i16
+ %res = add i16 %a16, %a16
+ store i16 %res, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @zextload_P3_i8_to_i16(ptr addrspace(3) inreg %ptra, ptr addrspace(1) %out) {
+; GFX11-LABEL: zextload_P3_i8_to_i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v2, s0
+; GFX11-NEXT: ds_load_u8_d16 v2, v2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v2
+; GFX11-NEXT: s_add_i32 s0, s0, s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-NEXT: global_store_b16 v[0:1], v2, off
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: zextload_P3_i8_to_i16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_mov_b32_e32 v2, s0
+; GFX12-NEXT: ds_load_u8_d16 v2, v2
+; GFX12-NEXT: s_wait_dscnt 0x0
+; GFX12-NEXT: v_readfirstlane_b32 s0, v2
+; GFX12-NEXT: s_add_co_i32 s0, s0, s0
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-NEXT: s_endpgm
+ %a = load i8, ptr addrspace(3) %ptra
+ %a16 = zext i8 %a to i16
+ %res = add i16 %a16, %a16
+ store i16 %res, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_ps void @zextload_P4_i8_to_i16(ptr addrspace(4) inreg %ptra, ptr addrspace(1) %out) {
+; GFX11-LABEL: zextload_P4_i8_to_i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: global_load_d16_u8 v2, v2, s[0:1]
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v2
+; GFX11-NEXT: s_add_i32 s0, s0, s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-NEXT: global_store_b16 v[0:1], v2, off
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: zextload_P4_i8_to_i16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_add_co_i32 s0, s0, s0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-NEXT: s_endpgm
+ %a = load i8, ptr addrspace(4) %ptra
+ %a16 = zext i8 %a to i16
+ %res = add i16 %a16, %a16
+ store i16 %res, ptr addrspace(1) %out
+ ret void
+}
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