[llvm] 8723e31 - AMDGPU/GlobalISel: Switch more FP opcodes to extended LLTs (part 6) (#214031)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 5 08:18:46 PDT 2026
Author: vangthao95
Date: 2026-08-05T08:18:41-07:00
New Revision: 8723e3139f7bfb046124938305ef3d05c4ad726f
URL: https://github.com/llvm/llvm-project/commit/8723e3139f7bfb046124938305ef3d05c4ad726f
DIFF: https://github.com/llvm/llvm-project/commit/8723e3139f7bfb046124938305ef3d05c4ad726f.diff
LOG: AMDGPU/GlobalISel: Switch more FP opcodes to extended LLTs (part 6) (#214031)
Migrate G_LROUND, G_LLROUND, G_INTRINSIC_LRINT, G_INTRINSIC_LLRINT,
G_FCOPYSIGN, and G_ATOMICRMW_FADD to extended LLTs.
Update the relevant MIR tests.
Added:
Modified:
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 11d3c04e8de3d..16a87a8d28833 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -9223,7 +9223,7 @@ LegalizerHelper::lowerFCopySign(MachineInstr &MI) {
auto ShiftAmt = MIRBuilder.buildConstant(Src0IntTy, Src0Size - Src1Size);
auto Zext = MIRBuilder.buildZExt(Src0IntTy, Src1Int);
auto Shift = MIRBuilder.buildShl(Src0IntTy, Zext, ShiftAmt);
- And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask).getReg(0);
+ And1 = MIRBuilder.buildAnd(Src0IntTy, Shift, SignBitMask).getReg(0);
} else {
auto ShiftAmt = MIRBuilder.buildConstant(Src1IntTy, Src1Size - Src0Size);
auto Shift = MIRBuilder.buildLShr(Src1IntTy, Src1Int, ShiftAmt);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index f4c30b7907b32..d3ce8fa5e2974 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1252,7 +1252,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
// clang-format on
getActionDefinitionsBuilder({G_LROUND, G_LLROUND})
- .clampScalar(0, S16, S64)
+ .clampScalar(0, I16, I64)
.scalarize(0)
.lower();
@@ -1267,7 +1267,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.lower();
getActionDefinitionsBuilder({G_INTRINSIC_LRINT, G_INTRINSIC_LLRINT})
- .clampScalar(0, S16, S64)
+ .clampScalar(0, I16, I64)
.scalarize(0)
.lower();
@@ -1820,26 +1820,22 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
// TODO: v2bf16 operations, and fat buffer pointer support.
auto &Atomic = getActionDefinitionsBuilder(G_ATOMICRMW_FADD);
if (ST.hasLDSFPAtomicAddF32()) {
- Atomic.legalFor({{S32, LocalPtr}, {S32, RegionPtr}});
+ Atomic.legalFor({{F32, LocalPtr}, {F32, RegionPtr}});
if (ST.hasLdsAtomicAddF64())
- Atomic.legalFor({{S64, LocalPtr}});
+ Atomic.legalFor({{F64, LocalPtr}});
if (ST.hasAtomicDsPkAdd16Insts())
Atomic.legalFor({{V2F16, LocalPtr}, {V2BF16, LocalPtr}});
}
if (ST.hasAtomicFaddInsts())
- Atomic.legalFor({{S32, GlobalPtr}});
+ Atomic.legalFor({{F32, GlobalPtr}});
if (ST.hasFlatAtomicFaddF32Inst())
- Atomic.legalFor({{S32, FlatPtr}});
+ Atomic.legalFor({{F32, FlatPtr}});
if (ST.hasGFX90AInsts() || ST.hasGFX1250Insts()) {
// These are legal with some caveats, and should have undergone expansion in
// the IR in most situations
// TODO: Move atomic expansion into legalizer
- Atomic.legalFor({
- {S32, GlobalPtr},
- {S64, GlobalPtr},
- {S64, FlatPtr}
- });
+ Atomic.legalFor({{F32, GlobalPtr}, {F64, GlobalPtr}, {F64, FlatPtr}});
}
if (ST.hasAtomicBufferGlobalPkAddF16NoRtnInsts() ||
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
index 3d826bae8a583..71cc602bb1d22 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
@@ -1380,89 +1380,89 @@ body: |
...
---
-name: fold_fcopysign_into_select_s32_0
+name: fold_fcopysign_into_select_f32_0
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: fold_fcopysign_into_select_s32_0
+ ; CHECK-LABEL: name: fold_fcopysign_into_select_f32_0
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %reg:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
- ; CHECK-NEXT: %two:_(s32) = G_FCONSTANT float 2.000000e+00
- ; CHECK-NEXT: %four:_(s32) = G_FCONSTANT float 4.000000e+00
- ; CHECK-NEXT: %select:_(s32) = G_SELECT %cond(s1), %two, %four
- ; CHECK-NEXT: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
- ; CHECK-NEXT: %fcopysign:_(s32) = nnan G_FCOPYSIGN %select, %sixteen(s32)
- ; CHECK-NEXT: S_ENDPGM 0, implicit %fcopysign(s32)
- %reg:_(s32) = COPY $vgpr0
- %zero:_(s32) = G_CONSTANT i32 0
- %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero
- %two:_(s32) = G_FCONSTANT float 2.0
- %four:_(s32) = G_FCONSTANT float 4.0
- %select:_(s32) = G_SELECT %cond, %two, %four
- %sixteen:_(s32) = G_FCONSTANT float 16.0
- %fcopysign:_(s32) = nnan G_FCOPYSIGN %select, %sixteen
+ ; CHECK-NEXT: %reg:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: %zero:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: %cond:_(i1) = G_ICMP intpred(eq), %reg(i32), %zero
+ ; CHECK-NEXT: %two:_(f32) = G_FCONSTANT float 2.000000e+00
+ ; CHECK-NEXT: %four:_(f32) = G_FCONSTANT float 4.000000e+00
+ ; CHECK-NEXT: %select:_(f32) = G_SELECT %cond(i1), %two, %four
+ ; CHECK-NEXT: %sixteen:_(f32) = G_FCONSTANT float 1.600000e+01
+ ; CHECK-NEXT: %fcopysign:_(f32) = nnan G_FCOPYSIGN %select, %sixteen(f32)
+ ; CHECK-NEXT: S_ENDPGM 0, implicit %fcopysign(f32)
+ %reg:_(i32) = COPY $vgpr0
+ %zero:_(i32) = G_CONSTANT i32 0
+ %cond:_(i1) = G_ICMP intpred(eq), %reg, %zero
+ %two:_(f32) = G_FCONSTANT float 2.0
+ %four:_(f32) = G_FCONSTANT float 4.0
+ %select:_(f32) = G_SELECT %cond, %two, %four
+ %sixteen:_(f32) = G_FCONSTANT float 16.0
+ %fcopysign:_(f32) = nnan G_FCOPYSIGN %select, %sixteen
S_ENDPGM 0, implicit %fcopysign
...
---
-name: fold_fcopysign_into_select_s32_s64_0
+name: fold_fcopysign_into_select_f32_f64_0
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: fold_fcopysign_into_select_s32_s64_0
+ ; CHECK-LABEL: name: fold_fcopysign_into_select_f32_f64_0
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %reg:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
- ; CHECK-NEXT: %two:_(s32) = G_FCONSTANT float 2.000000e+00
- ; CHECK-NEXT: %four:_(s32) = G_FCONSTANT float 4.000000e+00
- ; CHECK-NEXT: %select:_(s32) = G_SELECT %cond(s1), %two, %four
- ; CHECK-NEXT: %sixteen:_(s64) = G_FCONSTANT double 1.600000e+01
- ; CHECK-NEXT: %fcopysign:_(s32) = nnan G_FCOPYSIGN %select, %sixteen(s64)
- ; CHECK-NEXT: S_ENDPGM 0, implicit %fcopysign(s32)
- %reg:_(s32) = COPY $vgpr0
- %zero:_(s32) = G_CONSTANT i32 0
- %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero
- %two:_(s32) = G_FCONSTANT float 2.0
- %four:_(s32) = G_FCONSTANT float 4.0
- %select:_(s32) = G_SELECT %cond, %two, %four
- %sixteen:_(s64) = G_FCONSTANT double 16.0
- %fcopysign:_(s32) = nnan G_FCOPYSIGN %select, %sixteen
+ ; CHECK-NEXT: %reg:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: %zero:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: %cond:_(i1) = G_ICMP intpred(eq), %reg(i32), %zero
+ ; CHECK-NEXT: %two:_(f32) = G_FCONSTANT float 2.000000e+00
+ ; CHECK-NEXT: %four:_(f32) = G_FCONSTANT float 4.000000e+00
+ ; CHECK-NEXT: %select:_(f32) = G_SELECT %cond(i1), %two, %four
+ ; CHECK-NEXT: %sixteen:_(f64) = G_FCONSTANT double 1.600000e+01
+ ; CHECK-NEXT: %fcopysign:_(f32) = nnan G_FCOPYSIGN %select, %sixteen(f64)
+ ; CHECK-NEXT: S_ENDPGM 0, implicit %fcopysign(f32)
+ %reg:_(i32) = COPY $vgpr0
+ %zero:_(i32) = G_CONSTANT i32 0
+ %cond:_(i1) = G_ICMP intpred(eq), %reg, %zero
+ %two:_(f32) = G_FCONSTANT float 2.0
+ %four:_(f32) = G_FCONSTANT float 4.0
+ %select:_(f32) = G_SELECT %cond, %two, %four
+ %sixteen:_(f64) = G_FCONSTANT double 16.0
+ %fcopysign:_(f32) = nnan G_FCOPYSIGN %select, %sixteen
S_ENDPGM 0, implicit %fcopysign
...
---
-name: fold_fcopysign_into_select_s64_s32_0
+name: fold_fcopysign_into_select_f64_f32_0
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: fold_fcopysign_into_select_s64_s32_0
+ ; CHECK-LABEL: name: fold_fcopysign_into_select_f64_f32_0
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %reg:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
- ; CHECK-NEXT: %two:_(s64) = G_FCONSTANT double 2.000000e+00
- ; CHECK-NEXT: %four:_(s64) = G_FCONSTANT double 4.000000e+00
- ; CHECK-NEXT: %select:_(s64) = G_SELECT %cond(s1), %two, %four
- ; CHECK-NEXT: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
- ; CHECK-NEXT: %fcopysign:_(s64) = nnan G_FCOPYSIGN %select, %sixteen(s32)
- ; CHECK-NEXT: S_ENDPGM 0, implicit %fcopysign(s64)
- %reg:_(s32) = COPY $vgpr0
- %zero:_(s32) = G_CONSTANT i32 0
- %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero
- %two:_(s64) = G_FCONSTANT double 2.0
- %four:_(s64) = G_FCONSTANT double 4.0
- %select:_(s64) = G_SELECT %cond, %two, %four
- %sixteen:_(s32) = G_FCONSTANT float 16.0
- %fcopysign:_(s64) = nnan G_FCOPYSIGN %select, %sixteen
+ ; CHECK-NEXT: %reg:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: %zero:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: %cond:_(i1) = G_ICMP intpred(eq), %reg(i32), %zero
+ ; CHECK-NEXT: %two:_(f64) = G_FCONSTANT double 2.000000e+00
+ ; CHECK-NEXT: %four:_(f64) = G_FCONSTANT double 4.000000e+00
+ ; CHECK-NEXT: %select:_(f64) = G_SELECT %cond(i1), %two, %four
+ ; CHECK-NEXT: %sixteen:_(f32) = G_FCONSTANT float 1.600000e+01
+ ; CHECK-NEXT: %fcopysign:_(f64) = nnan G_FCOPYSIGN %select, %sixteen(f32)
+ ; CHECK-NEXT: S_ENDPGM 0, implicit %fcopysign(f64)
+ %reg:_(i32) = COPY $vgpr0
+ %zero:_(i32) = G_CONSTANT i32 0
+ %cond:_(i1) = G_ICMP intpred(eq), %reg, %zero
+ %two:_(f64) = G_FCONSTANT double 2.0
+ %four:_(f64) = G_FCONSTANT double 4.0
+ %select:_(f64) = G_SELECT %cond, %two, %four
+ %sixteen:_(f32) = G_FCONSTANT float 16.0
+ %fcopysign:_(f64) = nnan G_FCOPYSIGN %select, %sixteen
S_ENDPGM 0, implicit %fcopysign
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir
index cfe4bf863b95f..7b8bb44b0f01c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir
@@ -293,14 +293,14 @@ body: |
; CHECK-LABEL: name: test_frint
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
- ; CHECK-NEXT: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[FNEG]]
- ; CHECK-NEXT: $vgpr0 = COPY [[FRINT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FRINT %0
- %2:_(s32) = G_FNEG %1
- $vgpr0 = COPY %2(s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[COPY]]
+ ; CHECK-NEXT: [[FRINT:%[0-9]+]]:_(f32) = G_FRINT [[FNEG]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FRINT]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FRINT %0
+ %2:_(f32) = G_FNEG %1
+ $vgpr0 = COPY %2(f32)
...
---
@@ -312,14 +312,14 @@ body: |
; CHECK-LABEL: name: test_fnearbyint
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
- ; CHECK-NEXT: [[FNEARBYINT:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FNEG]]
- ; CHECK-NEXT: $vgpr0 = COPY [[FNEARBYINT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FNEARBYINT %0
- %2:_(s32) = G_FNEG %1
- $vgpr0 = COPY %2(s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[COPY]]
+ ; CHECK-NEXT: [[FNEARBYINT:%[0-9]+]]:_(f32) = G_FNEARBYINT [[FNEG]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FNEARBYINT]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FNEARBYINT %0
+ %2:_(f32) = G_FNEG %1
+ $vgpr0 = COPY %2(f32)
...
---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir
index a3fa298e81547..77a6762f1c1bf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir
@@ -4,19 +4,19 @@
# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -O0 -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel.*' -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s
-# ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(s32) = G_ATOMICRMW_FADD %0:_(p1), %1:_ :: (load store seq_cst (s32), addrspace 1) (in function: atomicrmw_fadd_global_i32)
+# ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(f32) = G_ATOMICRMW_FADD %0:_(p1), %1:_ :: (load store seq_cst (f32), addrspace 1) (in function: atomicrmw_fadd_global_f32)
---
-name: atomicrmw_fadd_global_i32
+name: atomicrmw_fadd_global_f32
body: |
bb.0:
liveins: $sgpr0_sgpr1, $sgpr2
- ; CHECK-LABEL: name: atomicrmw_fadd_global_i32
+ ; CHECK-LABEL: name: atomicrmw_fadd_global_f32
; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $sgpr0_sgpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
- ; CHECK-NEXT: [[ATOMICRMW_FADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_FADD [[COPY]](p1), [[COPY1]] :: (load store seq_cst (s32), addrspace 1)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $sgpr2
+ ; CHECK-NEXT: [[ATOMICRMW_FADD:%[0-9]+]]:_(f32) = G_ATOMICRMW_FADD [[COPY]](p1), [[COPY1]] :: (load store seq_cst (f32), addrspace 1)
%0:_(p1) = COPY $sgpr0_sgpr1
- %1:_(s32) = COPY $sgpr2
- %2:_(s32) = G_ATOMICRMW_FADD %0, %1 :: (load store seq_cst (s32), addrspace 1)
+ %1:_(f32) = COPY $sgpr2
+ %2:_(f32) = G_ATOMICRMW_FADD %0, %1 :: (load store seq_cst (f32), addrspace 1)
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir
index 615ae6eef8848..a5b57a828ed6d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir
@@ -4,19 +4,19 @@
# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -O0 -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel.*' -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s
# RUN: llc -mtriple=amdgpu7.01-mesa-mesa3d -O0 -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel.*' -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s
-# ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(s32) = G_ATOMICRMW_FADD %0:_(p3), %1:_ :: (load store seq_cst (s32), addrspace 3) (in function: atomicrmw_fadd_local_i32)
+# ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(f32) = G_ATOMICRMW_FADD %0:_(p3), %1:_ :: (load store seq_cst (f32), addrspace 3) (in function: atomicrmw_fadd_local_f32)
---
-name: atomicrmw_fadd_local_i32
+name: atomicrmw_fadd_local_f32
body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; CHECK-LABEL: name: atomicrmw_fadd_local_i32
+ ; CHECK-LABEL: name: atomicrmw_fadd_local_f32
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $sgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
- ; CHECK-NEXT: [[ATOMICRMW_FADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_FADD [[COPY]](p3), [[COPY1]] :: (load store seq_cst (s32), addrspace 3)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $sgpr1
+ ; CHECK-NEXT: [[ATOMICRMW_FADD:%[0-9]+]]:_(f32) = G_ATOMICRMW_FADD [[COPY]](p3), [[COPY1]] :: (load store seq_cst (f32), addrspace 3)
%0:_(p3) = COPY $sgpr0
- %1:_(s32) = COPY $sgpr1
- %2:_(s32) = G_ATOMICRMW_FADD %0, %1 :: (load store seq_cst (s32), addrspace 3)
+ %1:_(f32) = COPY $sgpr1
+ %2:_(f32) = G_ATOMICRMW_FADD %0, %1 :: (load store seq_cst (f32), addrspace 3)
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
index bb4a5467cfba3..659a2f4a35a27 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
@@ -1,808 +1,1102 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s
# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
-# RUN: llc -mtriple=amdgpu9.00-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9 %s
-# RUN: llc -mtriple=amdgpu10.10-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9 %s
-# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgpu9.00-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck -check-prefixes=GCN,GFX9 %s
+# RUN: llc -mtriple=amdgpu10.10-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck -check-prefixes=GCN,GFX10 %s
+# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck -check-prefixes=GCN,GFX11 %s
---
-name: test_copysign_s16_s16
+name: test_copysign_f16_f16
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; SI-LABEL: name: test_copysign_s16_s16
+ ; SI-LABEL: name: test_copysign_f16_f16
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
; SI-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; SI-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
; SI-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; VI-LABEL: name: test_copysign_s16_s16
+ ; VI-LABEL: name: test_copysign_f16_f16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
; VI-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; VI-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
; VI-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; GFX9-LABEL: name: test_copysign_s16_s16
+ ; GFX9-LABEL: name: test_copysign_f16_f16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; GFX9-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
; GFX9-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s16) = G_TRUNC %0
- %3:_(s16) = G_TRUNC %1
- %4:_(s16) = G_FCOPYSIGN %2, %3
- %5:_(s32) = G_ANYEXT %4
- $vgpr0 = COPY %5
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ ;
+ ; GFX10-LABEL: name: test_copysign_f16_f16
+ ; GFX10: liveins: $vgpr0, $vgpr1
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
+ ; GFX10-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C1]]
+ ; GFX10-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
+ ; GFX10-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ ;
+ ; GFX11-LABEL: name: test_copysign_f16_f16
+ ; GFX11: liveins: $vgpr0, $vgpr1
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC1]](i16)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i16) = G_BITCAST [[BITCAST]](f16)
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(i16) = G_BITCAST [[BITCAST1]](f16)
+ ; GFX11-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
+ ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
+ ; GFX11-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[BITCAST2]], [[C1]]
+ ; GFX11-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[BITCAST3]], [[C]]
+ ; GFX11-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f16) = G_BITCAST [[OR]](i16)
+ ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(i16) = G_BITCAST [[BITCAST4]](f16)
+ ; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[BITCAST5]](i16)
+ ; GFX11-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(i32) = COPY $vgpr1
+ %2:_(i16) = G_TRUNC %0
+ %3:_(i16) = G_TRUNC %1
+ %4:_(f16) = G_BITCAST %2
+ %5:_(f16) = G_BITCAST %3
+ %6:_(f16) = G_FCOPYSIGN %4, %5
+ %7:_(i16) = G_BITCAST %6
+ %8:_(i32) = G_ANYEXT %7
+ $vgpr0 = COPY %8
...
---
-name: test_copysign_s32_s32
+name: test_copysign_f32_f32
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; SI-LABEL: name: test_copysign_s32_s32
+ ; SI-LABEL: name: test_copysign_f32_f32
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; SI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C1]]
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C]]
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](f32)
;
- ; VI-LABEL: name: test_copysign_s32_s32
+ ; VI-LABEL: name: test_copysign_f32_f32
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; VI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; VI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C1]]
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; VI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C]]
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: $vgpr0 = COPY [[BITCAST2]](f32)
;
- ; GFX9-LABEL: name: test_copysign_s32_s32
- ; GFX9: liveins: $vgpr0, $vgpr1
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C1]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = G_FCOPYSIGN %0, %1
+ ; GCN-LABEL: name: test_copysign_f32_f32
+ ; GCN: liveins: $vgpr0, $vgpr1
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
+ ; GCN-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GCN-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
+ ; GCN-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C]]
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GCN-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GCN-NEXT: $vgpr0 = COPY [[BITCAST2]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = G_FCOPYSIGN %0, %1
$vgpr0 = COPY %2
...
---
-name: test_copysign_s64_s64
+name: test_copysign_f64_f64
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
- ; SI-LABEL: name: test_copysign_s64_s64
+ ; SI-LABEL: name: test_copysign_f64_f64
; SI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[COPY1]](f64)
; SI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
; SI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; SI-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[COPY]], [[C1]]
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C1]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[BITCAST1]], [[C]]
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST2]](f64)
;
- ; VI-LABEL: name: test_copysign_s64_s64
+ ; VI-LABEL: name: test_copysign_f64_f64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[COPY1]](f64)
; VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
; VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; VI-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[COPY]], [[C1]]
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[COPY1]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; VI-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C1]]
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[BITCAST1]], [[C]]
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST2]](f64)
;
- ; GFX9-LABEL: name: test_copysign_s64_s64
- ; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[COPY]], [[C1]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[COPY1]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = COPY $vgpr2_vgpr3
- %2:_(s64) = G_FCOPYSIGN %0, %1
+ ; GCN-LABEL: name: test_copysign_f64_f64
+ ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
+ ; GCN-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[COPY1]](f64)
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
+ ; GCN-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C1]]
+ ; GCN-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[BITCAST1]], [[C]]
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND1]]
+ ; GCN-NEXT: [[BITCAST2:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST2]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = COPY $vgpr2_vgpr3
+ %2:_(f64) = G_FCOPYSIGN %0, %1
$vgpr0_vgpr1 = COPY %2
...
---
-name: test_copysign_s64_s32
+name: test_copysign_f64_f32
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
- ; SI-LABEL: name: test_copysign_s64_s32
+ ; SI-LABEL: name: test_copysign_f64_f32
; SI: liveins: $vgpr0_vgpr1, $vgpr2
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
; SI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
; SI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; SI-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[COPY]], [[C1]]
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY1]](s32)
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C1]]
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[BITCAST1]](i32)
; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
; SI-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[ZEXT]], [[C2]](i32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C]]
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST2]](f64)
;
- ; VI-LABEL: name: test_copysign_s64_s32
+ ; VI-LABEL: name: test_copysign_f64_f32
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
; VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
; VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; VI-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[COPY]], [[C1]]
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY1]](s32)
+ ; VI-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C1]]
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[BITCAST1]](i32)
; VI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
; VI-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[ZEXT]], [[C2]](i32)
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C]]
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST2]](f64)
;
- ; GFX9-LABEL: name: test_copysign_s64_s32
- ; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[COPY]], [[C1]]
- ; GFX9-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY1]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
- ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[ZEXT]], [[C2]](i32)
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s32) = COPY $vgpr2
- %2:_(s64) = G_FCOPYSIGN %0, %1
+ ; GCN-LABEL: name: test_copysign_f64_f32
+ ; GCN: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
+ ; GCN-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
+ ; GCN-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C1]]
+ ; GCN-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[BITCAST1]](i32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[ZEXT]], [[C2]](i32)
+ ; GCN-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C]]
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND1]]
+ ; GCN-NEXT: [[BITCAST2:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST2]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f32) = COPY $vgpr2
+ %2:_(f64) = G_FCOPYSIGN %0, %1
$vgpr0_vgpr1 = COPY %2
...
---
-name: test_copysign_s32_s64
+name: test_copysign_f32_f64
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2
- ; SI-LABEL: name: test_copysign_s32_s64
+ ; SI-LABEL: name: test_copysign_f32_f64
; SI: liveins: $vgpr0, $vgpr1_vgpr2
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr1_vgpr2
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr1_vgpr2
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[COPY1]](f64)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; SI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C1]]
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
- ; SI-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[COPY1]], [[C2]](i32)
+ ; SI-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[BITCAST1]], [[C2]](i32)
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[LSHR]](i64)
; SI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[TRUNC]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](f32)
;
- ; VI-LABEL: name: test_copysign_s32_s64
+ ; VI-LABEL: name: test_copysign_f32_f64
; VI: liveins: $vgpr0, $vgpr1_vgpr2
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr1_vgpr2
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr1_vgpr2
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[COPY1]](f64)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; VI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; VI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C1]]
+ ; VI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
; VI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
- ; VI-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[COPY1]], [[C2]](i32)
+ ; VI-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[BITCAST1]], [[C2]](i32)
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[LSHR]](i64)
; VI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[TRUNC]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: $vgpr0 = COPY [[BITCAST2]](f32)
;
- ; GFX9-LABEL: name: test_copysign_s32_s64
- ; GFX9: liveins: $vgpr0, $vgpr1_vgpr2
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr1_vgpr2
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C1]]
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
- ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[COPY1]], [[C2]](i32)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[LSHR]](i64)
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[TRUNC]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s64) = COPY $vgpr1_vgpr2
- %2:_(s32) = G_FCOPYSIGN %0, %1
+ ; GCN-LABEL: name: test_copysign_f32_f64
+ ; GCN: liveins: $vgpr0, $vgpr1_vgpr2
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr1_vgpr2
+ ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
+ ; GCN-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[COPY1]](f64)
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GCN-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
+ ; GCN-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[BITCAST1]], [[C2]](i32)
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[LSHR]](i64)
+ ; GCN-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[TRUNC]], [[C]]
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GCN-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GCN-NEXT: $vgpr0 = COPY [[BITCAST2]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f64) = COPY $vgpr1_vgpr2
+ %2:_(f32) = G_FCOPYSIGN %0, %1
$vgpr0 = COPY %2
...
---
-name: test_copysign_s16_s32
+name: test_copysign_f16_f32
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; SI-LABEL: name: test_copysign_s16_s32
+ ; SI-LABEL: name: test_copysign_f16_f32
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
; SI-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; SI-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
; SI-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C1]]
; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
- ; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[COPY1]], [[C2]](i32)
+ ; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C2]](i32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
; SI-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; VI-LABEL: name: test_copysign_s16_s32
+ ; VI-LABEL: name: test_copysign_f16_f32
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
; VI-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; VI-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
; VI-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C1]]
; VI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
- ; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[COPY1]], [[C2]](i32)
+ ; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C2]](i32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; GFX9-LABEL: name: test_copysign_s16_s32
+ ; GFX9-LABEL: name: test_copysign_f16_f32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; GFX9-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
; GFX9-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C1]]
; GFX9-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
- ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[COPY1]], [[C2]](i32)
+ ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C2]](i32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s16) = G_TRUNC %0
- %3:_(s16) = G_FCOPYSIGN %2, %1
- %4:_(s32) = G_ANYEXT %3
- $vgpr0 = COPY %4
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ ;
+ ; GFX10-LABEL: name: test_copysign_f16_f32
+ ; GFX10: liveins: $vgpr0, $vgpr1
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
+ ; GFX10-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C1]]
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; GFX10-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C2]](i32)
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
+ ; GFX10-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
+ ; GFX10-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ ;
+ ; GFX11-LABEL: name: test_copysign_f16_f32
+ ; GFX11: liveins: $vgpr0, $vgpr1
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i16) = G_BITCAST [[BITCAST]](f16)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
+ ; GFX11-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
+ ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
+ ; GFX11-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[BITCAST1]], [[C1]]
+ ; GFX11-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C2]](i32)
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
+ ; GFX11-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
+ ; GFX11-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[OR]](i16)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(i16) = G_BITCAST [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[BITCAST4]](i16)
+ ; GFX11-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(i16) = G_TRUNC %0
+ %3:_(f16) = G_BITCAST %2
+ %4:_(f16) = G_FCOPYSIGN %3, %1
+ %5:_(i16) = G_BITCAST %4
+ %6:_(i32) = G_ANYEXT %5
+ $vgpr0 = COPY %6
...
---
-name: test_copysign_s32_s16
+name: test_copysign_f32_f16
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; SI-LABEL: name: test_copysign_s32_s16
+ ; SI-LABEL: name: test_copysign_f32_f16
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; SI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C1]]
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C2]](i32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C]]
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](f32)
;
- ; VI-LABEL: name: test_copysign_s32_s16
+ ; VI-LABEL: name: test_copysign_f32_f16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; VI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; VI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C1]]
+ ; VI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
; VI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
; VI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C2]](i32)
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C]]
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](f32)
;
- ; GFX9-LABEL: name: test_copysign_s32_s16
+ ; GFX9-LABEL: name: test_copysign_f32_f16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C1]]
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
; GFX9-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C2]](i32)
- ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s16) = G_TRUNC %1
- %3:_(s32) = G_FCOPYSIGN %0, %2
- $vgpr0 = COPY %3
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[BITCAST1]](f32)
+ ;
+ ; GFX10-LABEL: name: test_copysign_f32_f16
+ ; GFX10: liveins: $vgpr0, $vgpr1
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX10-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; GFX10-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
+ ; GFX10-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
+ ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C2]](i32)
+ ; GFX10-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C]]
+ ; GFX10-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND2]]
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX10-NEXT: $vgpr0 = COPY [[BITCAST1]](f32)
+ ;
+ ; GFX11-LABEL: name: test_copysign_f32_f16
+ ; GFX11: liveins: $vgpr0, $vgpr1
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i16) = G_BITCAST [[BITCAST]](f16)
+ ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX11-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C1]]
+ ; GFX11-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; GFX11-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[BITCAST2]](i16)
+ ; GFX11-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT]], [[C2]](i32)
+ ; GFX11-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C]]
+ ; GFX11-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST3]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(i32) = COPY $vgpr1
+ %2:_(i16) = G_TRUNC %1
+ %3:_(f16) = G_BITCAST %2
+ %4:_(f32) = G_FCOPYSIGN %0, %3
+ $vgpr0 = COPY %4
...
---
-name: test_copysign_s64_s16
+name: test_copysign_f64_f16
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
- ; SI-LABEL: name: test_copysign_s64_s16
+ ; SI-LABEL: name: test_copysign_f64_f16
; SI: liveins: $vgpr0_vgpr1, $vgpr2
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
; SI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
; SI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; SI-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[COPY]], [[C1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT [[COPY1]](s32)
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C1]]
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT [[COPY1]](i32)
; SI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 65535
; SI-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[ANYEXT]], [[C2]]
; SI-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 48
; SI-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[AND1]], [[C3]](i32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C]]
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST1]](f64)
;
- ; VI-LABEL: name: test_copysign_s64_s16
+ ; VI-LABEL: name: test_copysign_f64_f16
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
; VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
; VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; VI-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[COPY]], [[C1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT [[COPY1]](s32)
+ ; VI-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT [[COPY1]](i32)
; VI-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 65535
; VI-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[ANYEXT]], [[C2]]
; VI-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 48
; VI-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[AND1]], [[C3]](i32)
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C]]
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST1]](f64)
;
- ; GFX9-LABEL: name: test_copysign_s64_s16
+ ; GFX9-LABEL: name: test_copysign_f64_f16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
; GFX9-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[COPY]], [[C1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT [[COPY1]](s32)
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT [[COPY1]](i32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 65535
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[ANYEXT]], [[C2]]
; GFX9-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 48
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[AND1]], [[C3]](i32)
- ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s32) = COPY $vgpr2
- %2:_(s16) = G_TRUNC %1
- %3:_(s64) = G_FCOPYSIGN %0, %2
- $vgpr0_vgpr1 = COPY %3
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST1]](f64)
+ ;
+ ; GFX10-LABEL: name: test_copysign_f64_f16
+ ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
+ ; GFX10-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C1]]
+ ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT [[COPY1]](i32)
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 65535
+ ; GFX10-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[ANYEXT]], [[C2]]
+ ; GFX10-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 48
+ ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[AND1]], [[C3]](i32)
+ ; GFX10-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C]]
+ ; GFX10-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND2]]
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST1]](f64)
+ ;
+ ; GFX11-LABEL: name: test_copysign_f64_f16
+ ; GFX11: liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr2
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i16) = G_BITCAST [[BITCAST]](f16)
+ ; GFX11-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
+ ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
+ ; GFX11-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[BITCAST1]], [[C1]]
+ ; GFX11-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[BITCAST2]](i16)
+ ; GFX11-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 48
+ ; GFX11-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[ZEXT]], [[C2]](i32)
+ ; GFX11-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C]]
+ ; GFX11-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST3]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(i32) = COPY $vgpr2
+ %2:_(i16) = G_TRUNC %1
+ %3:_(f16) = G_BITCAST %2
+ %4:_(f64) = G_FCOPYSIGN %0, %3
+ $vgpr0_vgpr1 = COPY %4
...
---
-name: test_copysign_s16_s64
+name: test_copysign_f16_f64
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2
- ; SI-LABEL: name: test_copysign_s16_s64
+ ; SI-LABEL: name: test_copysign_f16_f64
; SI: liveins: $vgpr0, $vgpr1_vgpr2
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr1_vgpr2
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr1_vgpr2
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY1]](f64)
; SI-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; SI-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
; SI-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C1]]
; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 48
- ; SI-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[COPY1]], [[C2]](i32)
+ ; SI-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[BITCAST]], [[C2]](i32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i64)
; SI-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; VI-LABEL: name: test_copysign_s16_s64
+ ; VI-LABEL: name: test_copysign_f16_f64
; VI: liveins: $vgpr0, $vgpr1_vgpr2
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr1_vgpr2
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr1_vgpr2
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY1]](f64)
; VI-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; VI-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
; VI-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C1]]
; VI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 48
- ; VI-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[COPY1]], [[C2]](i32)
+ ; VI-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[BITCAST]], [[C2]](i32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i64)
; VI-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; GFX9-LABEL: name: test_copysign_s16_s64
+ ; GFX9-LABEL: name: test_copysign_f16_f64
; GFX9: liveins: $vgpr0, $vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr1_vgpr2
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr1_vgpr2
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY1]](f64)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; GFX9-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
; GFX9-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C1]]
; GFX9-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 48
- ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[COPY1]], [[C2]](i32)
+ ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[BITCAST]], [[C2]](i32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i64)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s64) = COPY $vgpr1_vgpr2
- %2:_(s16) = G_TRUNC %0
- %3:_(s16) = G_FCOPYSIGN %2, %1
- %4:_(s32) = G_ANYEXT %3
- $vgpr0 = COPY %4
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ ;
+ ; GFX10-LABEL: name: test_copysign_f16_f64
+ ; GFX10: liveins: $vgpr0, $vgpr1_vgpr2
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr1_vgpr2
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY1]](f64)
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
+ ; GFX10-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C1]]
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 48
+ ; GFX10-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[BITCAST]], [[C2]](i32)
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i64)
+ ; GFX10-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
+ ; GFX10-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ ;
+ ; GFX11-LABEL: name: test_copysign_f16_f64
+ ; GFX11: liveins: $vgpr0, $vgpr1_vgpr2
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr1_vgpr2
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i16) = G_BITCAST [[BITCAST]](f16)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i64) = G_BITCAST [[COPY1]](f64)
+ ; GFX11-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
+ ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
+ ; GFX11-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[BITCAST1]], [[C1]]
+ ; GFX11-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 48
+ ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[BITCAST2]], [[C2]](i32)
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i64)
+ ; GFX11-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
+ ; GFX11-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[OR]](i16)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(i16) = G_BITCAST [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[BITCAST4]](i16)
+ ; GFX11-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(f64) = COPY $vgpr1_vgpr2
+ %2:_(i16) = G_TRUNC %0
+ %3:_(f16) = G_BITCAST %2
+ %4:_(f16) = G_FCOPYSIGN %3, %1
+ %5:_(i16) = G_BITCAST %4
+ %6:_(i32) = G_ANYEXT %5
+ $vgpr0 = COPY %6
...
---
-name: test_copysign_v2s16_v2s16
+name: test_copysign_v2f16_v2f16
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; SI-LABEL: name: test_copysign_v2s16_v2s16
+ ; SI-LABEL: name: test_copysign_v2f16_v2f16
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[COPY]](<2 x f16>)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[COPY1]](<2 x f16>)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 32768
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[C]], [[C1]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[C]], [[SHL]]
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[OR]](i32)
; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32767
; SI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[C2]], [[C1]](i32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[C2]], [[SHL1]]
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[OR1]](i32)
- ; SI-NEXT: [[AND:%[0-9]+]]:_(<2 x i16>) = G_AND [[COPY]], [[BITCAST1]]
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(<2 x i16>) = G_AND [[COPY1]], [[BITCAST]]
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0 = COPY [[OR2]](<2 x s16>)
+ ; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[OR1]](i32)
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(<2 x i16>) = G_AND [[BITCAST]], [[BITCAST3]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(<2 x i16>) = G_AND [[BITCAST1]], [[BITCAST2]]
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(<2 x i16>) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR2]](<2 x i16>)
+ ; SI-NEXT: $vgpr0 = COPY [[BITCAST4]](<2 x f16>)
;
- ; VI-LABEL: name: test_copysign_v2s16_v2s16
+ ; VI-LABEL: name: test_copysign_v2f16_v2f16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[COPY]](<2 x f16>)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[COPY1]](<2 x f16>)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 32768
; VI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[C]], [[C1]](i32)
; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[C]], [[SHL]]
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[OR]](i32)
; VI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32767
; VI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[C2]], [[C1]](i32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[C2]], [[SHL1]]
- ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[OR1]](i32)
- ; VI-NEXT: [[AND:%[0-9]+]]:_(<2 x i16>) = G_AND [[COPY]], [[BITCAST1]]
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(<2 x i16>) = G_AND [[COPY1]], [[BITCAST]]
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0 = COPY [[OR2]](<2 x s16>)
+ ; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[OR1]](i32)
+ ; VI-NEXT: [[AND:%[0-9]+]]:_(<2 x i16>) = G_AND [[BITCAST]], [[BITCAST3]]
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(<2 x i16>) = G_AND [[BITCAST1]], [[BITCAST2]]
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(<2 x i16>) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR2]](<2 x i16>)
+ ; VI-NEXT: $vgpr0 = COPY [[BITCAST4]](<2 x f16>)
;
- ; GFX9-LABEL: name: test_copysign_v2s16_v2s16
- ; GFX9: liveins: $vgpr0, $vgpr1
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[C]](i16), [[C]](i16)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
- ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[C1]](i16), [[C1]](i16)
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(<2 x i16>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(<2 x i16>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[OR]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = COPY $vgpr1
- %2:_(<2 x s16>) = G_FCOPYSIGN %0, %1
+ ; GCN-LABEL: name: test_copysign_v2f16_v2f16
+ ; GCN: liveins: $vgpr0, $vgpr1
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GCN-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
+ ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[C]](i16), [[C]](i16)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
+ ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[C1]](i16), [[C1]](i16)
+ ; GCN-NEXT: [[AND:%[0-9]+]]:_(<2 x i16>) = G_AND [[BITCAST]], [[BUILD_VECTOR1]]
+ ; GCN-NEXT: [[AND1:%[0-9]+]]:_(<2 x i16>) = G_AND [[BITCAST1]], [[BUILD_VECTOR]]
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(<2 x i16>) = disjoint G_OR [[AND]], [[AND1]]
+ ; GCN-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](<2 x i16>)
+ ; GCN-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = COPY $vgpr1
+ %2:_(<2 x f16>) = G_FCOPYSIGN %0, %1
$vgpr0 = COPY %2
...
---
-name: test_copysign_v2s32_v2s32
+name: test_copysign_v2f32_v2f32
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
- ; SI-LABEL: name: test_copysign_v2s32_v2s32
+ ; SI-LABEL: name: test_copysign_v2f32_v2f32
; SI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[COPY]](<2 x f32>)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[COPY1]](<2 x f32>)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C]](i32)
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; SI-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C1]](i32)
- ; SI-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(<2 x i32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[BITCAST]], [[BUILD_VECTOR1]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(<2 x i32>) = G_AND [[BITCAST1]], [[BUILD_VECTOR]]
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(<2 x i32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[OR]](<2 x i32>)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST2]](<2 x f32>)
;
- ; VI-LABEL: name: test_copysign_v2s32_v2s32
+ ; VI-LABEL: name: test_copysign_v2f32_v2f32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[COPY]](<2 x f32>)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[COPY1]](<2 x f32>)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C]](i32)
; VI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; VI-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C1]](i32)
- ; VI-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(<2 x i32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
+ ; VI-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[BITCAST]], [[BUILD_VECTOR1]]
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(<2 x i32>) = G_AND [[BITCAST1]], [[BUILD_VECTOR]]
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(<2 x i32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[OR]](<2 x i32>)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST2]](<2 x f32>)
;
- ; GFX9-LABEL: name: test_copysign_v2s32_v2s32
- ; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C]](i32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C1]](i32)
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(<2 x i32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
- %2:_(<2 x s32>) = G_FCOPYSIGN %0, %1
+ ; GCN-LABEL: name: test_copysign_v2f32_v2f32
+ ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[COPY]](<2 x f32>)
+ ; GCN-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[COPY1]](<2 x f32>)
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C]](i32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C1]](i32)
+ ; GCN-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[BITCAST]], [[BUILD_VECTOR1]]
+ ; GCN-NEXT: [[AND1:%[0-9]+]]:_(<2 x i32>) = G_AND [[BITCAST1]], [[BUILD_VECTOR]]
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(<2 x i32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; GCN-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[OR]](<2 x i32>)
+ ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST2]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ %2:_(<2 x f32>) = G_FCOPYSIGN %0, %1
$vgpr0_vgpr1 = COPY %2
...
---
-name: test_copysign_v2s64_v2s64
+name: test_copysign_v2f64_v2f64
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
- ; SI-LABEL: name: test_copysign_v2s64_v2s64
+ ; SI-LABEL: name: test_copysign_v2f64_v2f64
; SI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[COPY]](<2 x f64>)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[COPY1]](<2 x f64>)
; SI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
; SI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[BITCAST]](<2 x i64>)
; SI-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[UV]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[UV1]], [[C1]]
- ; SI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
+ ; SI-NEXT: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[BITCAST1]](<2 x i64>)
; SI-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[UV2]], [[C]]
; SI-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[UV3]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(i64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[OR]](i64), [[OR1]](i64)
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[BUILD_VECTOR]](<2 x i64>)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST2]](<2 x f64>)
;
- ; VI-LABEL: name: test_copysign_v2s64_v2s64
+ ; VI-LABEL: name: test_copysign_v2f64_v2f64
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[COPY]](<2 x f64>)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[COPY1]](<2 x f64>)
; VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
; VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[BITCAST]](<2 x i64>)
; VI-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[UV]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[UV1]], [[C1]]
- ; VI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
+ ; VI-NEXT: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[BITCAST1]](<2 x i64>)
; VI-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[UV2]], [[C]]
; VI-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[UV3]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: [[OR1:%[0-9]+]]:_(i64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[OR]](i64), [[OR1]](i64)
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[BUILD_VECTOR]](<2 x i64>)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST2]](<2 x f64>)
;
- ; GFX9-LABEL: name: test_copysign_v2s64_v2s64
- ; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[UV]], [[C1]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[UV1]], [[C1]]
- ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
- ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[UV2]], [[C]]
- ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[UV3]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- %2:_(<2 x s64>) = G_FCOPYSIGN %0, %1
+ ; GCN-LABEL: name: test_copysign_v2f64_v2f64
+ ; GCN: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[COPY]](<2 x f64>)
+ ; GCN-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[COPY1]](<2 x f64>)
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
+ ; GCN-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[BITCAST]](<2 x i64>)
+ ; GCN-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[UV]], [[C1]]
+ ; GCN-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[UV1]], [[C1]]
+ ; GCN-NEXT: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[BITCAST1]](<2 x i64>)
+ ; GCN-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[UV2]], [[C]]
+ ; GCN-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[UV3]], [[C]]
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND2]]
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[OR]](i64), [[OR1]](i64)
+ ; GCN-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[BUILD_VECTOR]](<2 x i64>)
+ ; GCN-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST2]](<2 x f64>)
+ %0:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<2 x f64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ %2:_(<2 x f64>) = G_FCOPYSIGN %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
...
---
-name: test_copysign_v2s64_v2s32
+name: test_copysign_v2f64_v2f32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
- ; SI-LABEL: name: test_copysign_v2s64_v2s32
+ ; SI-LABEL: name: test_copysign_v2f64_v2f32
; SI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr4_vgpr5
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[COPY]](<2 x f64>)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[COPY1]](<2 x f32>)
; SI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
; SI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[BITCAST]](<2 x i64>)
; SI-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[UV]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[UV1]], [[C1]]
- ; SI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[UV2]](s32)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i64) = G_ZEXT [[UV3]](s32)
+ ; SI-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST1]](<2 x i32>)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[UV2]](i32)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i64) = G_ZEXT [[UV3]](i32)
; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
; SI-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[C2]](i32)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[ZEXT]], [[COPY2]](i32)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(i64) = G_SHL [[ZEXT1]], [[C2]](i32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[SHL1]], [[C]]
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(i64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[OR]](i64), [[OR1]](i64)
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[BUILD_VECTOR]](<2 x i64>)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST2]](<2 x f64>)
;
- ; VI-LABEL: name: test_copysign_v2s64_v2s32
+ ; VI-LABEL: name: test_copysign_v2f64_v2f32
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr4_vgpr5
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[COPY]](<2 x f64>)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[COPY1]](<2 x f32>)
; VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
; VI-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[BITCAST]](<2 x i64>)
; VI-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[UV]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[UV1]], [[C1]]
- ; VI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[UV2]](s32)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i64) = G_ZEXT [[UV3]](s32)
+ ; VI-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST1]](<2 x i32>)
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[UV2]](i32)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i64) = G_ZEXT [[UV3]](i32)
; VI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
; VI-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[C2]](i32)
; VI-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[ZEXT]], [[COPY2]](i32)
; VI-NEXT: [[SHL1:%[0-9]+]]:_(i64) = G_SHL [[ZEXT1]], [[C2]](i32)
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; VI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C]]
+ ; VI-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[SHL1]], [[C]]
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: [[OR1:%[0-9]+]]:_(i64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[OR]](i64), [[OR1]](i64)
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[BUILD_VECTOR]](<2 x i64>)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST2]](<2 x f64>)
;
- ; GFX9-LABEL: name: test_copysign_v2s64_v2s32
- ; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[UV]], [[C1]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[UV1]], [[C1]]
- ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX9-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[UV2]](s32)
- ; GFX9-NEXT: [[ZEXT1:%[0-9]+]]:_(i64) = G_ZEXT [[UV3]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[C2]](i32)
- ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[ZEXT]], [[COPY2]](i32)
- ; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(i64) = G_SHL [[ZEXT1]], [[C2]](i32)
- ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<2 x s32>) = COPY $vgpr4_vgpr5
- %2:_(<2 x s64>) = G_FCOPYSIGN %0, %1
+ ; GCN-LABEL: name: test_copysign_v2f64_v2f32
+ ; GCN: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr4_vgpr5
+ ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[COPY]](<2 x f64>)
+ ; GCN-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[COPY1]](<2 x f32>)
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
+ ; GCN-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[BITCAST]](<2 x i64>)
+ ; GCN-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[UV]], [[C1]]
+ ; GCN-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[UV1]], [[C1]]
+ ; GCN-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST1]](<2 x i32>)
+ ; GCN-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[UV2]](i32)
+ ; GCN-NEXT: [[ZEXT1:%[0-9]+]]:_(i64) = G_ZEXT [[UV3]](i32)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
+ ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[C2]](i32)
+ ; GCN-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[ZEXT]], [[COPY2]](i32)
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(i64) = G_SHL [[ZEXT1]], [[C2]](i32)
+ ; GCN-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C]]
+ ; GCN-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[SHL1]], [[C]]
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND2]]
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(i64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[OR]](i64), [[OR1]](i64)
+ ; GCN-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[BUILD_VECTOR]](<2 x i64>)
+ ; GCN-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST2]](<2 x f64>)
+ %0:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<2 x f32>) = COPY $vgpr4_vgpr5
+ %2:_(<2 x f64>) = G_FCOPYSIGN %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
...
---
-name: test_copysign_v2s32_v2s64
+name: test_copysign_v2f32_v2f64
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
- ; SI-LABEL: name: test_copysign_v2s32_v2s64
+ ; SI-LABEL: name: test_copysign_v2f32_v2f64
; SI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[COPY]](<2 x f32>)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[COPY1]](<2 x f64>)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C]](i32)
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; SI-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C1]](i32)
- ; SI-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[BITCAST]], [[BUILD_VECTOR1]]
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[BITCAST1]](<2 x i64>)
; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
; SI-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[C2]](i32)
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[UV]], [[COPY2]](i32)
@@ -811,20 +1105,23 @@ body: |
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC [[LSHR1]](i64)
; SI-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[TRUNC]](i32), [[TRUNC1]](i32)
; SI-NEXT: [[AND1:%[0-9]+]]:_(<2 x i32>) = G_AND [[BUILD_VECTOR2]], [[BUILD_VECTOR]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(<2 x i32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[OR]](<2 x i32>)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST2]](<2 x f32>)
;
- ; VI-LABEL: name: test_copysign_v2s32_v2s64
+ ; VI-LABEL: name: test_copysign_v2f32_v2f64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[COPY]](<2 x f32>)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[COPY1]](<2 x f64>)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C]](i32)
; VI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
; VI-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C1]](i32)
- ; VI-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
+ ; VI-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[BITCAST]], [[BUILD_VECTOR1]]
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[BITCAST1]](<2 x i64>)
; VI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
; VI-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[C2]](i32)
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[UV]], [[COPY2]](i32)
@@ -833,204 +1130,307 @@ body: |
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC [[LSHR1]](i64)
; VI-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[TRUNC]](i32), [[TRUNC1]](i32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(<2 x i32>) = G_AND [[BUILD_VECTOR2]], [[BUILD_VECTOR]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(<2 x i32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[OR]](<2 x i32>)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST2]](<2 x f32>)
;
- ; GFX9-LABEL: name: test_copysign_v2s32_v2s64
- ; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C]](i32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C1]](i32)
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[C2]](i32)
- ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[UV]], [[COPY2]](i32)
- ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i64) = G_LSHR [[UV1]], [[C2]](i32)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[LSHR]](i64)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC [[LSHR1]](i64)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[TRUNC]](i32), [[TRUNC1]](i32)
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(<2 x i32>) = G_AND [[BUILD_VECTOR2]], [[BUILD_VECTOR]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
- %2:_(<2 x s32>) = G_FCOPYSIGN %0, %1
+ ; GCN-LABEL: name: test_copysign_v2f32_v2f64
+ ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
+ ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[COPY]](<2 x f32>)
+ ; GCN-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[COPY1]](<2 x f64>)
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C]](i32)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GCN-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C1]](i32)
+ ; GCN-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[BITCAST]], [[BUILD_VECTOR1]]
+ ; GCN-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[BITCAST1]](<2 x i64>)
+ ; GCN-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
+ ; GCN-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[C2]](i32)
+ ; GCN-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[UV]], [[COPY2]](i32)
+ ; GCN-NEXT: [[LSHR1:%[0-9]+]]:_(i64) = G_LSHR [[UV1]], [[C2]](i32)
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[LSHR]](i64)
+ ; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC [[LSHR1]](i64)
+ ; GCN-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[TRUNC]](i32), [[TRUNC1]](i32)
+ ; GCN-NEXT: [[AND1:%[0-9]+]]:_(<2 x i32>) = G_AND [[BUILD_VECTOR2]], [[BUILD_VECTOR]]
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(<2 x i32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; GCN-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[OR]](<2 x i32>)
+ ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST2]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
+ %2:_(<2 x f32>) = G_FCOPYSIGN %0, %1
$vgpr0_vgpr1 = COPY %2
...
---
-name: test_copysign_s32_s32_flagss
+name: test_copysign_f32_f32_flagss
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; SI-LABEL: name: test_copysign_s32_s32_flagss
+ ; SI-LABEL: name: test_copysign_f32_f32_flagss
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; SI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C1]]
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C]]
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](f32)
;
- ; VI-LABEL: name: test_copysign_s32_s32_flagss
+ ; VI-LABEL: name: test_copysign_f32_f32_flagss
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; VI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; VI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C1]]
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; VI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C]]
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: $vgpr0 = COPY [[BITCAST2]](f32)
;
- ; GFX9-LABEL: name: test_copysign_s32_s32_flagss
- ; GFX9: liveins: $vgpr0, $vgpr1
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C1]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = nnan G_FCOPYSIGN %0, %1
+ ; GCN-LABEL: name: test_copysign_f32_f32_flagss
+ ; GCN: liveins: $vgpr0, $vgpr1
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
+ ; GCN-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GCN-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
+ ; GCN-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C]]
+ ; GCN-NEXT: [[OR:%[0-9]+]]:_(i32) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; GCN-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GCN-NEXT: $vgpr0 = COPY [[BITCAST2]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = nnan G_FCOPYSIGN %0, %1
$vgpr0 = COPY %2
...
---
-name: test_copysign_s32_s16_flags
+name: test_copysign_f32_f16_flags
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; SI-LABEL: name: test_copysign_s32_s16_flags
+ ; SI-LABEL: name: test_copysign_f32_f16_flags
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; SI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C1]]
+ ; SI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C2]](i32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C]]
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = nnan disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](f32)
;
- ; VI-LABEL: name: test_copysign_s32_s16_flags
+ ; VI-LABEL: name: test_copysign_f32_f16_flags
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; VI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; VI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C1]]
+ ; VI-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
; VI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
; VI-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C2]](i32)
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C]]
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = nnan disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](f32)
;
- ; GFX9-LABEL: name: test_copysign_s32_s16_flags
+ ; GFX9-LABEL: name: test_copysign_f32_f16_flags
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C1]]
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
; GFX9-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C2]](i32)
- ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s16) = G_TRUNC %1
- %3:_(s32) = nnan G_FCOPYSIGN %0, %2
- $vgpr0 = COPY %3
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = nnan disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[BITCAST1]](f32)
+ ;
+ ; GFX10-LABEL: name: test_copysign_f32_f16_flags
+ ; GFX10: liveins: $vgpr0, $vgpr1
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX10-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; GFX10-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
+ ; GFX10-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C3]]
+ ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C2]](i32)
+ ; GFX10-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C]]
+ ; GFX10-NEXT: [[OR:%[0-9]+]]:_(i32) = nnan disjoint G_OR [[AND]], [[AND2]]
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX10-NEXT: $vgpr0 = COPY [[BITCAST1]](f32)
+ ;
+ ; GFX11-LABEL: name: test_copysign_f32_f16_flags
+ ; GFX11: liveins: $vgpr0, $vgpr1
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i16) = G_BITCAST [[BITCAST]](f16)
+ ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; GFX11-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C1]]
+ ; GFX11-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; GFX11-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[BITCAST2]](i16)
+ ; GFX11-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT]], [[C2]](i32)
+ ; GFX11-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C]]
+ ; GFX11-NEXT: [[OR:%[0-9]+]]:_(i32) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST3]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(i32) = COPY $vgpr1
+ %2:_(i16) = G_TRUNC %1
+ %3:_(f16) = G_BITCAST %2
+ %4:_(f32) = nnan G_FCOPYSIGN %0, %3
+ $vgpr0 = COPY %4
...
---
-name: test_copysign_s16_s32_flags
+name: test_copysign_f16_f32_flags
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; SI-LABEL: name: test_copysign_s16_s32_flags
+ ; SI-LABEL: name: test_copysign_f16_f32_flags
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
; SI-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; SI-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
; SI-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C1]]
; SI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
- ; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[COPY1]], [[C2]](i32)
+ ; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C2]](i32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
; SI-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(i16) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; VI-LABEL: name: test_copysign_s16_s32_flags
+ ; VI-LABEL: name: test_copysign_f16_f32_flags
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
; VI-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; VI-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
; VI-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C1]]
; VI-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
- ; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[COPY1]], [[C2]](i32)
+ ; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C2]](i32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(i16) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; GFX9-LABEL: name: test_copysign_s16_s32_flags
+ ; GFX9-LABEL: name: test_copysign_f16_f32_flags
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; GFX9-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
; GFX9-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C1]]
; GFX9-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
- ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[COPY1]], [[C2]](i32)
+ ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C2]](i32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s16) = G_TRUNC %0
- %3:_(s16) = nnan G_FCOPYSIGN %2, %1
- %4:_(s32) = G_ANYEXT %3
- $vgpr0 = COPY %4
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i16) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ ;
+ ; GFX10-LABEL: name: test_copysign_f16_f32_flags
+ ; GFX10: liveins: $vgpr0, $vgpr1
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
+ ; GFX10-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C1]]
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; GFX10-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C2]](i32)
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
+ ; GFX10-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
+ ; GFX10-NEXT: [[OR:%[0-9]+]]:_(i16) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ ;
+ ; GFX11-LABEL: name: test_copysign_f16_f32_flags
+ ; GFX11: liveins: $vgpr0, $vgpr1
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i16) = G_BITCAST [[BITCAST]](f16)
+ ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](f32)
+ ; GFX11-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
+ ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
+ ; GFX11-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[BITCAST1]], [[C1]]
+ ; GFX11-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C2]](i32)
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
+ ; GFX11-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C]]
+ ; GFX11-NEXT: [[OR:%[0-9]+]]:_(i16) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f16) = G_BITCAST [[OR]](i16)
+ ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(i16) = G_BITCAST [[BITCAST3]](f16)
+ ; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[BITCAST4]](i16)
+ ; GFX11-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(i16) = G_TRUNC %0
+ %3:_(f16) = G_BITCAST %2
+ %4:_(f16) = nnan G_FCOPYSIGN %3, %1
+ %5:_(i16) = G_BITCAST %4
+ %6:_(i32) = G_ANYEXT %5
+ $vgpr0 = COPY %6
...
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