[llvm] [AArch64] Lower fixed-length interleaved stores with SVE (PR #213692)

[Kamlesh Kumar via llvm-commits]

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@@ -27820,6 +27822,37 @@ performInterleavedStoreCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
                                    DAG.getVTList(MVT::Other), Ops,
                                    MemN->getMemoryVT(), MemN->getMemOperand());
   }
+
+  // Fixed-length vectors using SVE
+  if (!Subtarget.isSVEorStreamingSVEAvailable())
+    return SDValue();
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kamleshbhalui wrote:

there is already a check  for this above at line 27776. I will add the test.

https://github.com/llvm/llvm-project/pull/213692