[llvm] 9629318 - [AMDGPU] Fix Dwarf CFI emission for exec to vcc spills (#213115)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 5 06:40:42 PDT 2026
Author: Emma Pilkington
Date: 2026-08-05T09:40:35-04:00
New Revision: 9629318c9c54c01fda351425c656a0007414ac28
URL: https://github.com/llvm/llvm-project/commit/9629318c9c54c01fda351425c656a0007414ac28
DIFF: https://github.com/llvm/llvm-project/commit/9629318c9c54c01fda351425c656a0007414ac28.diff
LOG: [AMDGPU] Fix Dwarf CFI emission for exec to vcc spills (#213115)
Added:
Modified:
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index c1fa828f38bbf..158a83fd61cf4 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -410,14 +410,14 @@ class PrologEpilogSGPRSpillBuilder {
ArrayRef<int16_t> DstSplitParts = TRI.getRegSplitParts(RC, EltSize);
assert(NumSubRegs == (DstSplitParts.empty() ? 1 : DstSplitParts.size()));
MCRegister CFISuperReg = getCFISuperReg();
- if (NumSubRegs == 1) {
- TFI->buildCFI(
- MBB, MI, DL,
- MCCFIInstruction::createRegister(
- nullptr,
- MCRI->getDwarfRegNum(
- CFISuperReg ? CFISuperReg : SuperReg.asMCReg(), false),
- MCRI->getDwarfRegNum(DstReg, false)));
+ if (!CFISuperReg)
+ CFISuperReg = SuperReg;
+ int64_t DwarfCFISuperReg = MCRI->getDwarfRegNum(CFISuperReg, false);
+ int64_t DwarfDstSuperReg = MCRI->getDwarfRegNum(DstReg, false);
+ if (DwarfCFISuperReg >= 0 && DwarfDstSuperReg >= 0) {
+ TFI->buildCFI(MBB, MI, DL,
+ MCCFIInstruction::createRegister(
+ nullptr, DwarfCFISuperReg, DwarfDstSuperReg));
} else if (isExec(CFISuperReg)) {
assert(NumSubRegs == 2 && "EXEC larger than 64-bit");
TFI->buildCFIForRegToSGPRPairSpill(MBB, MI, DL, CFISuperReg, DstReg);
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index 31f927709e682..a410ffedc784d 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -160,7 +160,8 @@ multiclass SIRegLoHi16 <string n, bits<10> regIdx, bit ArtificialHigh = 1,
}
// Special Registers
-defm VCC_LO : SIRegLoHi16<"vcc_lo", 106>;
+defm VCC_LO : SIRegLoHi16<"vcc_lo", 106, /*ArtificialHigh=*/1, /*isVGPR=*/0,
+ /*isAGPR=*/0, /*DwarfEncodings=*/[512, 512]>;
defm VCC_HI : SIRegLoHi16<"vcc_hi", 107>;
// Pseudo-registers: Used as placeholders during isel and immediately
@@ -178,7 +179,7 @@ def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16, 16]> {
}
// VCC for 64-bit instructions
-def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> {
+def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]>, DwarfRegNum<[768, 512]> {
let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1];
let HWEncoding = VCC_LO.HWEncoding;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll
index c8a2c0aaf72e3..a7950a63ee835 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll
@@ -2911,6 +2911,160 @@ define void @need_to_spill_pc_to_mem() #3 {
ret void
}
+define void @spill_exec_to_vcc() #3 {
+; WAVE64-LABEL: spill_exec_to_vcc:
+; WAVE64: .Lfunc_begin8:
+; WAVE64-NEXT: .cfi_startproc
+; WAVE64-NEXT: ; %bb.0:
+; WAVE64-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6
+; WAVE64-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32
+; WAVE64-NEXT: .cfi_undefined 36
+; WAVE64-NEXT: .cfi_undefined 37
+; WAVE64-NEXT: .cfi_undefined 38
+; WAVE64-NEXT: .cfi_undefined 39
+; WAVE64-NEXT: .cfi_undefined 40
+; WAVE64-NEXT: .cfi_undefined 41
+; WAVE64-NEXT: .cfi_undefined 42
+; WAVE64-NEXT: .cfi_undefined 43
+; WAVE64-NEXT: .cfi_undefined 44
+; WAVE64-NEXT: .cfi_undefined 45
+; WAVE64-NEXT: .cfi_undefined 46
+; WAVE64-NEXT: .cfi_undefined 47
+; WAVE64-NEXT: .cfi_undefined 48
+; WAVE64-NEXT: .cfi_undefined 49
+; WAVE64-NEXT: .cfi_undefined 50
+; WAVE64-NEXT: .cfi_undefined 51
+; WAVE64-NEXT: .cfi_undefined 52
+; WAVE64-NEXT: .cfi_undefined 53
+; WAVE64-NEXT: .cfi_undefined 54
+; WAVE64-NEXT: .cfi_undefined 55
+; WAVE64-NEXT: .cfi_undefined 56
+; WAVE64-NEXT: .cfi_undefined 57
+; WAVE64-NEXT: .cfi_undefined 58
+; WAVE64-NEXT: .cfi_undefined 59
+; WAVE64-NEXT: .cfi_undefined 60
+; WAVE64-NEXT: .cfi_undefined 61
+; WAVE64-NEXT: .cfi_undefined 72
+; WAVE64-NEXT: .cfi_undefined 73
+; WAVE64-NEXT: .cfi_undefined 74
+; WAVE64-NEXT: .cfi_undefined 75
+; WAVE64-NEXT: .cfi_undefined 76
+; WAVE64-NEXT: .cfi_undefined 77
+; WAVE64-NEXT: .cfi_undefined 78
+; WAVE64-NEXT: .cfi_undefined 79
+; WAVE64-NEXT: .cfi_undefined 88
+; WAVE64-NEXT: .cfi_undefined 89
+; WAVE64-NEXT: .cfi_undefined 90
+; WAVE64-NEXT: .cfi_undefined 91
+; WAVE64-NEXT: .cfi_undefined 92
+; WAVE64-NEXT: .cfi_undefined 93
+; WAVE64-NEXT: .cfi_undefined 94
+; WAVE64-NEXT: .cfi_undefined 95
+; WAVE64-NEXT: .cfi_undefined 1096
+; WAVE64-NEXT: .cfi_undefined 1097
+; WAVE64-NEXT: .cfi_undefined 1098
+; WAVE64-NEXT: .cfi_undefined 1099
+; WAVE64-NEXT: .cfi_undefined 1100
+; WAVE64-NEXT: .cfi_undefined 1101
+; WAVE64-NEXT: .cfi_undefined 1102
+; WAVE64-NEXT: .cfi_undefined 1103
+; WAVE64-NEXT: .cfi_undefined 1112
+; WAVE64-NEXT: .cfi_undefined 1113
+; WAVE64-NEXT: .cfi_undefined 1114
+; WAVE64-NEXT: .cfi_undefined 1115
+; WAVE64-NEXT: .cfi_undefined 1116
+; WAVE64-NEXT: .cfi_undefined 1117
+; WAVE64-NEXT: .cfi_undefined 1118
+; WAVE64-NEXT: .cfi_undefined 1119
+; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; WAVE64-NEXT: s_mov_b64 vcc, exec
+; WAVE64-NEXT: .cfi_register 17, 768
+; WAVE64-NEXT: ;;#ASMSTART
+; WAVE64-NEXT: ; clobber scratch SGPRs
+; WAVE64-NEXT: ;;#ASMEND
+; WAVE64-NEXT: s_setpc_b64 s[30:31]
+;
+; WAVE32-LABEL: spill_exec_to_vcc:
+; WAVE32: .Lfunc_begin8:
+; WAVE32-NEXT: .cfi_startproc
+; WAVE32-NEXT: ; %bb.0:
+; WAVE32-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6
+; WAVE32-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32
+; WAVE32-NEXT: .cfi_undefined 36
+; WAVE32-NEXT: .cfi_undefined 37
+; WAVE32-NEXT: .cfi_undefined 38
+; WAVE32-NEXT: .cfi_undefined 39
+; WAVE32-NEXT: .cfi_undefined 40
+; WAVE32-NEXT: .cfi_undefined 41
+; WAVE32-NEXT: .cfi_undefined 42
+; WAVE32-NEXT: .cfi_undefined 43
+; WAVE32-NEXT: .cfi_undefined 44
+; WAVE32-NEXT: .cfi_undefined 45
+; WAVE32-NEXT: .cfi_undefined 46
+; WAVE32-NEXT: .cfi_undefined 47
+; WAVE32-NEXT: .cfi_undefined 48
+; WAVE32-NEXT: .cfi_undefined 49
+; WAVE32-NEXT: .cfi_undefined 50
+; WAVE32-NEXT: .cfi_undefined 51
+; WAVE32-NEXT: .cfi_undefined 52
+; WAVE32-NEXT: .cfi_undefined 53
+; WAVE32-NEXT: .cfi_undefined 54
+; WAVE32-NEXT: .cfi_undefined 55
+; WAVE32-NEXT: .cfi_undefined 56
+; WAVE32-NEXT: .cfi_undefined 57
+; WAVE32-NEXT: .cfi_undefined 58
+; WAVE32-NEXT: .cfi_undefined 59
+; WAVE32-NEXT: .cfi_undefined 60
+; WAVE32-NEXT: .cfi_undefined 61
+; WAVE32-NEXT: .cfi_undefined 72
+; WAVE32-NEXT: .cfi_undefined 73
+; WAVE32-NEXT: .cfi_undefined 74
+; WAVE32-NEXT: .cfi_undefined 75
+; WAVE32-NEXT: .cfi_undefined 76
+; WAVE32-NEXT: .cfi_undefined 77
+; WAVE32-NEXT: .cfi_undefined 78
+; WAVE32-NEXT: .cfi_undefined 79
+; WAVE32-NEXT: .cfi_undefined 88
+; WAVE32-NEXT: .cfi_undefined 89
+; WAVE32-NEXT: .cfi_undefined 90
+; WAVE32-NEXT: .cfi_undefined 91
+; WAVE32-NEXT: .cfi_undefined 92
+; WAVE32-NEXT: .cfi_undefined 93
+; WAVE32-NEXT: .cfi_undefined 94
+; WAVE32-NEXT: .cfi_undefined 95
+; WAVE32-NEXT: .cfi_undefined 1096
+; WAVE32-NEXT: .cfi_undefined 1097
+; WAVE32-NEXT: .cfi_undefined 1098
+; WAVE32-NEXT: .cfi_undefined 1099
+; WAVE32-NEXT: .cfi_undefined 1100
+; WAVE32-NEXT: .cfi_undefined 1101
+; WAVE32-NEXT: .cfi_undefined 1102
+; WAVE32-NEXT: .cfi_undefined 1103
+; WAVE32-NEXT: .cfi_undefined 1112
+; WAVE32-NEXT: .cfi_undefined 1113
+; WAVE32-NEXT: .cfi_undefined 1114
+; WAVE32-NEXT: .cfi_undefined 1115
+; WAVE32-NEXT: .cfi_undefined 1116
+; WAVE32-NEXT: .cfi_undefined 1117
+; WAVE32-NEXT: .cfi_undefined 1118
+; WAVE32-NEXT: .cfi_undefined 1119
+; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; WAVE32-NEXT: s_mov_b32 vcc_lo, exec_lo
+; WAVE32-NEXT: .cfi_register 1, 512
+; WAVE32-NEXT: ;;#ASMSTART
+; WAVE32-NEXT: ; clobber scratch SGPRs
+; WAVE32-NEXT: ;;#ASMEND
+; WAVE32-NEXT: s_setpc_b64 s[30:31]
+ call void asm sideeffect "; clobber scratch SGPRs",
+ "~{s4},~{s5},~{s6},~{s7},~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14}
+ ,~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24}
+ ,~{s25},~{s26},~{s27},~{s28},~{s29},~{s40},~{s41},~{s42},~{s43},~{s44}
+ ,~{s45},~{s46},~{s47},~{s56},~{s57},~{s58},~{s59},~{s60},~{s61},~{s62}
+ ,~{s63},~{s72},~{s73},~{s74},~{s75},~{s76},~{s77},~{s78},~{s79},~{s88}
+ ,~{s89},~{s90},~{s91},~{s92},~{s93},~{s94},~{s95}"()
+ ret void
+}
+
attributes #0 = { nounwind }
attributes #1 = { nounwind "amdgpu-waves-per-eu"="10,10" }
attributes #2 = { nounwind "frame-pointer"="all" "amdgpu-waves-per-eu"="10,10" }
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